1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/agp/agppriv.h> 43 #include <dev/agp/agpreg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <sys/rman.h> 53 54 MALLOC_DECLARE(M_AGP); 55 56 #define READ2(off) bus_space_read_2(sc->bst, sc->bsh, off) 57 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off) 58 #define WRITE2(off,v) bus_space_write_2(sc->bst, sc->bsh, off, v) 59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) 60 61 struct agp_amd_gatt { 62 u_int32_t ag_entries; 63 u_int32_t *ag_virtual; /* virtual address of gatt */ 64 vm_offset_t ag_physical; 65 u_int32_t *ag_vdir; /* virtual address of page dir */ 66 vm_offset_t ag_pdir; /* physical address of page dir */ 67 }; 68 69 struct agp_amd_softc { 70 struct agp_softc agp; 71 struct resource *regs; /* memory mapped control registers */ 72 bus_space_tag_t bst; /* bus_space tag */ 73 bus_space_handle_t bsh; /* bus_space handle */ 74 u_int32_t initial_aperture; /* aperture size at startup */ 75 struct agp_amd_gatt *gatt; 76 }; 77 78 static struct agp_amd_gatt * 79 agp_amd_alloc_gatt(device_t dev) 80 { 81 u_int32_t apsize = AGP_GET_APERTURE(dev); 82 u_int32_t entries = apsize >> AGP_PAGE_SHIFT; 83 struct agp_amd_gatt *gatt; 84 int i, npages, pdir_offset; 85 86 if (bootverbose) 87 device_printf(dev, 88 "allocating GATT for aperture of size %dM\n", 89 apsize / (1024*1024)); 90 91 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT); 92 if (!gatt) 93 return 0; 94 95 /* 96 * The AMD751 uses a page directory to map a non-contiguous 97 * gatt so we don't need to use contigmalloc. 98 * Malloc individual gatt pages and map them into the page 99 * directory. 100 */ 101 gatt->ag_entries = entries; 102 gatt->ag_virtual = malloc(entries * sizeof(u_int32_t), 103 M_AGP, M_NOWAIT); 104 if (!gatt->ag_virtual) { 105 if (bootverbose) 106 device_printf(dev, "allocation failed\n"); 107 free(gatt, M_AGP); 108 return 0; 109 } 110 bzero(gatt->ag_virtual, entries * sizeof(u_int32_t)); 111 112 /* 113 * Allocate the page directory. 114 */ 115 gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT); 116 if (!gatt->ag_vdir) { 117 if (bootverbose) 118 device_printf(dev, 119 "failed to allocate page directory\n"); 120 free(gatt->ag_virtual, M_AGP); 121 free(gatt, M_AGP); 122 return 0; 123 } 124 bzero(gatt->ag_vdir, AGP_PAGE_SIZE); 125 126 gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir); 127 if(bootverbose) 128 device_printf(dev, "gatt -> ag_pdir %#lx\n", 129 (u_long)gatt->ag_pdir); 130 /* 131 * Allocate the gatt pages 132 */ 133 gatt->ag_entries = entries; 134 if(bootverbose) 135 device_printf(dev, "allocating GATT for %d AGP page entries\n", 136 gatt->ag_entries); 137 138 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 139 140 /* 141 * Map the pages of the GATT into the page directory. 142 * 143 * The GATT page addresses are mapped into the directory offset by 144 * an amount dependent on the base address of the aperture. This 145 * is and offset into the page directory, not an offset added to 146 * the addresses of the gatt pages. 147 */ 148 149 pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22; 150 151 npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1) 152 >> AGP_PAGE_SHIFT); 153 154 for (i = 0; i < npages; i++) { 155 vm_offset_t va; 156 vm_offset_t pa; 157 158 va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE; 159 pa = vtophys(va); 160 gatt->ag_vdir[i + pdir_offset] = pa | 1; 161 } 162 163 /* 164 * Make sure the chipset can see everything. 165 */ 166 agp_flush_cache(); 167 168 return gatt; 169 } 170 171 static void 172 agp_amd_free_gatt(struct agp_amd_gatt *gatt) 173 { 174 free(gatt->ag_virtual, M_AGP); 175 free(gatt->ag_vdir, M_AGP); 176 free(gatt, M_AGP); 177 } 178 179 static const char* 180 agp_amd_match(device_t dev) 181 { 182 if (pci_get_class(dev) != PCIC_BRIDGE 183 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 184 return NULL; 185 186 if (agp_find_caps(dev) == 0) 187 return NULL; 188 189 switch (pci_get_devid(dev)) { 190 case 0x70061022: 191 return ("AMD 751 host to AGP bridge"); 192 case 0x700e1022: 193 return ("AMD 761 host to AGP bridge"); 194 case 0x700c1022: 195 return ("AMD 762 host to AGP bridge"); 196 }; 197 198 return NULL; 199 } 200 201 static int 202 agp_amd_probe(device_t dev) 203 { 204 const char *desc; 205 206 if (resource_disabled("agp", device_get_unit(dev))) 207 return (ENXIO); 208 desc = agp_amd_match(dev); 209 if (desc) { 210 device_set_desc(dev, desc); 211 return BUS_PROBE_DEFAULT; 212 } 213 214 return ENXIO; 215 } 216 217 static int 218 agp_amd_attach(device_t dev) 219 { 220 struct agp_amd_softc *sc = device_get_softc(dev); 221 struct agp_amd_gatt *gatt; 222 int error, rid; 223 224 error = agp_generic_attach(dev); 225 if (error) 226 return error; 227 228 rid = AGP_AMD751_REGISTERS; 229 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 230 RF_ACTIVE); 231 if (!sc->regs) { 232 agp_generic_detach(dev); 233 return ENOMEM; 234 } 235 236 sc->bst = rman_get_bustag(sc->regs); 237 sc->bsh = rman_get_bushandle(sc->regs); 238 239 sc->initial_aperture = AGP_GET_APERTURE(dev); 240 241 for (;;) { 242 gatt = agp_amd_alloc_gatt(dev); 243 if (gatt) 244 break; 245 246 /* 247 * Probably contigmalloc failure. Try reducing the 248 * aperture so that the gatt size reduces. 249 */ 250 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 251 return ENOMEM; 252 } 253 sc->gatt = gatt; 254 255 /* Install the gatt. */ 256 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir); 257 258 /* Enable synchronisation between host and agp. */ 259 pci_write_config(dev, 260 AGP_AMD751_MODECTRL, 261 AGP_AMD751_MODECTRL_SYNEN, 1); 262 263 /* Set indexing mode for two-level and enable page dir cache */ 264 pci_write_config(dev, 265 AGP_AMD751_MODECTRL2, 266 AGP_AMD751_MODECTRL2_GPDCE, 1); 267 268 /* Enable the TLB and flush */ 269 WRITE2(AGP_AMD751_STATUS, 270 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); 271 AGP_FLUSH_TLB(dev); 272 273 return 0; 274 } 275 276 static int 277 agp_amd_detach(device_t dev) 278 { 279 struct agp_amd_softc *sc = device_get_softc(dev); 280 281 agp_free_cdev(dev); 282 283 /* Disable the TLB.. */ 284 WRITE2(AGP_AMD751_STATUS, 285 READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE); 286 287 /* Disable host-agp sync */ 288 pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1); 289 290 /* Clear the GATT base */ 291 WRITE4(AGP_AMD751_ATTBASE, 0); 292 293 /* Put the aperture back the way it started. */ 294 AGP_SET_APERTURE(dev, sc->initial_aperture); 295 296 agp_amd_free_gatt(sc->gatt); 297 agp_free_res(dev); 298 299 bus_release_resource(dev, SYS_RES_MEMORY, 300 AGP_AMD751_REGISTERS, sc->regs); 301 302 return 0; 303 } 304 305 static u_int32_t 306 agp_amd_get_aperture(device_t dev) 307 { 308 int vas; 309 310 /* 311 * The aperture size is equal to 32M<<vas. 312 */ 313 vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1; 314 return (32*1024*1024) << vas; 315 } 316 317 static int 318 agp_amd_set_aperture(device_t dev, u_int32_t aperture) 319 { 320 int vas; 321 322 /* 323 * Check for a power of two and make sure its within the 324 * programmable range. 325 */ 326 if (aperture & (aperture - 1) 327 || aperture < 32*1024*1024 328 || aperture > 2U*1024*1024*1024) 329 return EINVAL; 330 331 vas = ffs(aperture / 32*1024*1024) - 1; 332 333 /* 334 * While the size register is bits 1-3 of APCTRL, bit 0 must be 335 * set for the size value to be 'valid' 336 */ 337 pci_write_config(dev, AGP_AMD751_APCTRL, 338 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06) 339 | ((vas << 1) | 1))), 1); 340 341 return 0; 342 } 343 344 static int 345 agp_amd_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 346 { 347 struct agp_amd_softc *sc = device_get_softc(dev); 348 349 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 350 return EINVAL; 351 352 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1; 353 354 /* invalidate the cache */ 355 AGP_FLUSH_TLB(dev); 356 return 0; 357 } 358 359 static int 360 agp_amd_unbind_page(device_t dev, vm_offset_t offset) 361 { 362 struct agp_amd_softc *sc = device_get_softc(dev); 363 364 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 365 return EINVAL; 366 367 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 368 return 0; 369 } 370 371 static void 372 agp_amd_flush_tlb(device_t dev) 373 { 374 struct agp_amd_softc *sc = device_get_softc(dev); 375 376 /* Set the cache invalidate bit and wait for the chipset to clear */ 377 WRITE4(AGP_AMD751_TLBCTRL, 1); 378 do { 379 DELAY(1); 380 } while (READ4(AGP_AMD751_TLBCTRL)); 381 } 382 383 static device_method_t agp_amd_methods[] = { 384 /* Device interface */ 385 DEVMETHOD(device_probe, agp_amd_probe), 386 DEVMETHOD(device_attach, agp_amd_attach), 387 DEVMETHOD(device_detach, agp_amd_detach), 388 DEVMETHOD(device_shutdown, bus_generic_shutdown), 389 DEVMETHOD(device_suspend, bus_generic_suspend), 390 DEVMETHOD(device_resume, bus_generic_resume), 391 392 /* AGP interface */ 393 DEVMETHOD(agp_get_aperture, agp_amd_get_aperture), 394 DEVMETHOD(agp_set_aperture, agp_amd_set_aperture), 395 DEVMETHOD(agp_bind_page, agp_amd_bind_page), 396 DEVMETHOD(agp_unbind_page, agp_amd_unbind_page), 397 DEVMETHOD(agp_flush_tlb, agp_amd_flush_tlb), 398 DEVMETHOD(agp_enable, agp_generic_enable), 399 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 400 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 401 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 402 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 403 404 { 0, 0 } 405 }; 406 407 static driver_t agp_amd_driver = { 408 "agp", 409 agp_amd_methods, 410 sizeof(struct agp_amd_softc), 411 }; 412 413 static devclass_t agp_devclass; 414 415 DRIVER_MODULE(agp_amd, hostb, agp_amd_driver, agp_devclass, 0, 0); 416 MODULE_DEPEND(agp_amd, agp, 1, 1, 1); 417 MODULE_DEPEND(agp_amd, pci, 1, 1, 1); 418