1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _IF_AGEVAR_H 33 #define _IF_AGEVAR_H 34 35 #define AGE_TX_RING_CNT 256 36 #define AGE_RX_RING_CNT 256 37 #define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) 38 /* The following ring alignments are just guessing. */ 39 #define AGE_TX_RING_ALIGN 16 40 #define AGE_RX_RING_ALIGN 16 41 #define AGE_RR_RING_ALIGN 16 42 #define AGE_CMB_ALIGN 16 43 #define AGE_SMB_ALIGN 16 44 45 #define AGE_TSO_MAXSEGSIZE 4096 46 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 47 #define AGE_MAXTXSEGS 35 48 #define AGE_RX_BUF_ALIGN 8 49 #ifndef __NO_STRICT_ALIGNMENT 50 #define AGE_RX_BUF_SIZE (MCLBYTES - AGE_RX_BUF_ALIGN) 51 #else 52 #define AGE_RX_BUF_SIZE (MCLBYTES) 53 #endif 54 55 #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 56 #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) 57 58 #define AGE_MSI_MESSAGES 1 59 #define AGE_MSIX_MESSAGES 1 60 61 /* TODO : Should get real jumbo MTU size. */ 62 #define AGE_JUMBO_FRAMELEN 10240 63 #define AGE_JUMBO_MTU \ 64 (AGE_JUMBO_FRAMELEN - ETHER_VLAN_ENCAP_LEN - \ 65 ETHER_HDR_LEN - ETHER_CRC_LEN) 66 67 #define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 68 69 #define AGE_PROC_MIN 30 70 #define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) 71 #define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) 72 73 struct age_txdesc { 74 struct mbuf *tx_m; 75 bus_dmamap_t tx_dmamap; 76 struct tx_desc *tx_desc; 77 }; 78 79 struct age_rxdesc { 80 struct mbuf *rx_m; 81 bus_dmamap_t rx_dmamap; 82 struct rx_desc *rx_desc; 83 }; 84 85 struct age_chain_data{ 86 bus_dma_tag_t age_parent_tag; 87 bus_dma_tag_t age_buffer_tag; 88 bus_dma_tag_t age_tx_tag; 89 struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; 90 bus_dma_tag_t age_rx_tag; 91 struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; 92 bus_dma_tag_t age_tx_ring_tag; 93 bus_dmamap_t age_tx_ring_map; 94 bus_dma_tag_t age_rx_ring_tag; 95 bus_dmamap_t age_rx_ring_map; 96 bus_dmamap_t age_rx_sparemap; 97 bus_dma_tag_t age_rr_ring_tag; 98 bus_dmamap_t age_rr_ring_map; 99 bus_dma_tag_t age_cmb_block_tag; 100 bus_dmamap_t age_cmb_block_map; 101 bus_dma_tag_t age_smb_block_tag; 102 bus_dmamap_t age_smb_block_map; 103 104 int age_tx_prod; 105 int age_tx_cons; 106 int age_tx_cnt; 107 int age_rx_cons; 108 int age_rr_cons; 109 int age_rxlen; 110 111 struct mbuf *age_rxhead; 112 struct mbuf *age_rxtail; 113 struct mbuf *age_rxprev_tail; 114 }; 115 116 struct age_ring_data { 117 struct tx_desc *age_tx_ring; 118 bus_addr_t age_tx_ring_paddr; 119 struct rx_desc *age_rx_ring; 120 bus_addr_t age_rx_ring_paddr; 121 struct rx_rdesc *age_rr_ring; 122 bus_addr_t age_rr_ring_paddr; 123 struct cmb *age_cmb_block; 124 bus_addr_t age_cmb_block_paddr; 125 struct smb *age_smb_block; 126 bus_addr_t age_smb_block_paddr; 127 }; 128 129 #define AGE_TX_RING_SZ \ 130 (sizeof(struct tx_desc) * AGE_TX_RING_CNT) 131 #define AGE_RX_RING_SZ \ 132 (sizeof(struct rx_desc) * AGE_RX_RING_CNT) 133 #define AGE_RR_RING_SZ \ 134 (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) 135 #define AGE_CMB_BLOCK_SZ sizeof(struct cmb) 136 #define AGE_SMB_BLOCK_SZ sizeof(struct smb) 137 138 struct age_stats { 139 /* Rx stats. */ 140 uint64_t rx_frames; 141 uint64_t rx_bcast_frames; 142 uint64_t rx_mcast_frames; 143 uint32_t rx_pause_frames; 144 uint32_t rx_control_frames; 145 uint32_t rx_crcerrs; 146 uint32_t rx_lenerrs; 147 uint64_t rx_bytes; 148 uint32_t rx_runts; 149 uint64_t rx_fragments; 150 uint64_t rx_pkts_64; 151 uint64_t rx_pkts_65_127; 152 uint64_t rx_pkts_128_255; 153 uint64_t rx_pkts_256_511; 154 uint64_t rx_pkts_512_1023; 155 uint64_t rx_pkts_1024_1518; 156 uint64_t rx_pkts_1519_max; 157 uint64_t rx_pkts_truncated; 158 uint32_t rx_fifo_oflows; 159 uint32_t rx_desc_oflows; 160 uint32_t rx_alignerrs; 161 uint64_t rx_bcast_bytes; 162 uint64_t rx_mcast_bytes; 163 uint64_t rx_pkts_filtered; 164 /* Tx stats. */ 165 uint64_t tx_frames; 166 uint64_t tx_bcast_frames; 167 uint64_t tx_mcast_frames; 168 uint32_t tx_pause_frames; 169 uint32_t tx_excess_defer; 170 uint32_t tx_control_frames; 171 uint32_t tx_deferred; 172 uint64_t tx_bytes; 173 uint64_t tx_pkts_64; 174 uint64_t tx_pkts_65_127; 175 uint64_t tx_pkts_128_255; 176 uint64_t tx_pkts_256_511; 177 uint64_t tx_pkts_512_1023; 178 uint64_t tx_pkts_1024_1518; 179 uint64_t tx_pkts_1519_max; 180 uint32_t tx_single_colls; 181 uint32_t tx_multi_colls; 182 uint32_t tx_late_colls; 183 uint32_t tx_excess_colls; 184 uint32_t tx_underrun; 185 uint32_t tx_desc_underrun; 186 uint32_t tx_lenerrs; 187 uint32_t tx_pkts_truncated; 188 uint64_t tx_bcast_bytes; 189 uint64_t tx_mcast_bytes; 190 }; 191 192 /* 193 * Software state per device. 194 */ 195 struct age_softc { 196 if_t age_ifp; 197 device_t age_dev; 198 device_t age_miibus; 199 struct resource *age_res[1]; 200 struct resource_spec *age_res_spec; 201 struct resource *age_irq[AGE_MSI_MESSAGES]; 202 struct resource_spec *age_irq_spec; 203 void *age_intrhand[AGE_MSI_MESSAGES]; 204 int age_rev; 205 int age_chip_rev; 206 int age_phyaddr; 207 uint8_t age_eaddr[ETHER_ADDR_LEN]; 208 uint32_t age_dma_rd_burst; 209 uint32_t age_dma_wr_burst; 210 int age_flags; 211 #define AGE_FLAG_PCIE 0x0001 212 #define AGE_FLAG_PCIX 0x0002 213 #define AGE_FLAG_MSI 0x0004 214 #define AGE_FLAG_MSIX 0x0008 215 #define AGE_FLAG_PMCAP 0x0010 216 #define AGE_FLAG_DETACH 0x4000 217 #define AGE_FLAG_LINK 0x8000 218 219 struct callout age_tick_ch; 220 struct age_stats age_stat; 221 struct age_chain_data age_cdata; 222 struct age_ring_data age_rdata; 223 int age_if_flags; 224 int age_watchdog_timer; 225 int age_process_limit; 226 int age_int_mod; 227 int age_max_frame_size; 228 int age_morework; 229 int age_rr_prod; 230 int age_tpd_cons; 231 232 struct task age_int_task; 233 struct task age_link_task; 234 struct taskqueue *age_tq; 235 struct mtx age_mtx; 236 }; 237 238 /* Register access macros. */ 239 #define CSR_WRITE_4(_sc, reg, val) \ 240 bus_write_4((_sc)->age_res[0], (reg), (val)) 241 #define CSR_WRITE_2(_sc, reg, val) \ 242 bus_write_2((_sc)->age_res[0], (reg), (val)) 243 #define CSR_READ_2(_sc, reg) \ 244 bus_read_2((_sc)->age_res[0], (reg)) 245 #define CSR_READ_4(_sc, reg) \ 246 bus_read_4((_sc)->age_res[0], (reg)) 247 248 #define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) 249 #define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) 250 #define AGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->age_mtx, MA_OWNED) 251 252 #define AGE_COMMIT_MBOX(_sc) \ 253 do { \ 254 CSR_WRITE_4(_sc, AGE_MBOX, \ 255 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ 256 MBOX_RD_PROD_IDX_MASK) | \ 257 (((_sc)->age_cdata.age_rr_cons << \ 258 MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ 259 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ 260 MBOX_TD_PROD_IDX_MASK)); \ 261 } while (0) 262 263 #define AGE_RXCHAIN_RESET(_sc) \ 264 do { \ 265 (_sc)->age_cdata.age_rxhead = NULL; \ 266 (_sc)->age_cdata.age_rxtail = NULL; \ 267 (_sc)->age_cdata.age_rxprev_tail = NULL; \ 268 (_sc)->age_cdata.age_rxlen = 0; \ 269 } while (0) 270 271 #define AGE_TX_TIMEOUT 5 272 #define AGE_RESET_TIMEOUT 100 273 #define AGE_TIMEOUT 1000 274 #define AGE_PHY_TIMEOUT 1000 275 276 #endif /* _IF_AGEVAR_H */ 277