1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/age/if_agereg.h> 73 #include <dev/age/if_agevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 79 80 MODULE_DEPEND(age, pci, 1, 1, 1); 81 MODULE_DEPEND(age, ether, 1, 1, 1); 82 MODULE_DEPEND(age, miibus, 1, 1, 1); 83 84 /* Tunables. */ 85 static int msi_disable = 0; 86 static int msix_disable = 0; 87 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 88 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 89 90 /* 91 * Devices supported by this driver. 92 */ 93 static struct age_dev { 94 uint16_t age_vendorid; 95 uint16_t age_deviceid; 96 const char *age_name; 97 } age_devs[] = { 98 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 99 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 100 }; 101 102 static int age_miibus_readreg(device_t, int, int); 103 static int age_miibus_writereg(device_t, int, int, int); 104 static void age_miibus_statchg(device_t); 105 static void age_mediastatus(if_t, struct ifmediareq *); 106 static int age_mediachange(if_t); 107 static int age_probe(device_t); 108 static void age_get_macaddr(struct age_softc *); 109 static void age_phy_reset(struct age_softc *); 110 static int age_attach(device_t); 111 static int age_detach(device_t); 112 static void age_sysctl_node(struct age_softc *); 113 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 114 static int age_check_boundary(struct age_softc *); 115 static int age_dma_alloc(struct age_softc *); 116 static void age_dma_free(struct age_softc *); 117 static int age_shutdown(device_t); 118 static void age_setwol(struct age_softc *); 119 static int age_suspend(device_t); 120 static int age_resume(device_t); 121 static int age_encap(struct age_softc *, struct mbuf **); 122 static void age_start(if_t); 123 static void age_start_locked(if_t); 124 static void age_watchdog(struct age_softc *); 125 static int age_ioctl(if_t, u_long, caddr_t); 126 static void age_mac_config(struct age_softc *); 127 static void age_link_task(void *, int); 128 static void age_stats_update(struct age_softc *); 129 static int age_intr(void *); 130 static void age_int_task(void *, int); 131 static void age_txintr(struct age_softc *, int); 132 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 133 static int age_rxintr(struct age_softc *, int, int); 134 static void age_tick(void *); 135 static void age_reset(struct age_softc *); 136 static void age_init(void *); 137 static void age_init_locked(struct age_softc *); 138 static void age_stop(struct age_softc *); 139 static void age_stop_txmac(struct age_softc *); 140 static void age_stop_rxmac(struct age_softc *); 141 static void age_init_tx_ring(struct age_softc *); 142 static int age_init_rx_ring(struct age_softc *); 143 static void age_init_rr_ring(struct age_softc *); 144 static void age_init_cmb_block(struct age_softc *); 145 static void age_init_smb_block(struct age_softc *); 146 #ifndef __NO_STRICT_ALIGNMENT 147 static struct mbuf *age_fixup_rx(if_t, struct mbuf *); 148 #endif 149 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 150 static void age_rxvlan(struct age_softc *); 151 static void age_rxfilter(struct age_softc *); 152 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 156 157 static device_method_t age_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, age_probe), 160 DEVMETHOD(device_attach, age_attach), 161 DEVMETHOD(device_detach, age_detach), 162 DEVMETHOD(device_shutdown, age_shutdown), 163 DEVMETHOD(device_suspend, age_suspend), 164 DEVMETHOD(device_resume, age_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, age_miibus_readreg), 168 DEVMETHOD(miibus_writereg, age_miibus_writereg), 169 DEVMETHOD(miibus_statchg, age_miibus_statchg), 170 { NULL, NULL } 171 }; 172 173 static driver_t age_driver = { 174 "age", 175 age_methods, 176 sizeof(struct age_softc) 177 }; 178 179 DRIVER_MODULE(age, pci, age_driver, 0, 0); 180 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 181 nitems(age_devs)); 182 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0); 183 184 static struct resource_spec age_res_spec_mem[] = { 185 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 186 { -1, 0, 0 } 187 }; 188 189 static struct resource_spec age_irq_spec_legacy[] = { 190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 191 { -1, 0, 0 } 192 }; 193 194 static struct resource_spec age_irq_spec_msi[] = { 195 { SYS_RES_IRQ, 1, RF_ACTIVE }, 196 { -1, 0, 0 } 197 }; 198 199 static struct resource_spec age_irq_spec_msix[] = { 200 { SYS_RES_IRQ, 1, RF_ACTIVE }, 201 { -1, 0, 0 } 202 }; 203 204 /* 205 * Read a PHY register on the MII of the L1. 206 */ 207 static int 208 age_miibus_readreg(device_t dev, int phy, int reg) 209 { 210 struct age_softc *sc; 211 uint32_t v; 212 int i; 213 214 sc = device_get_softc(dev); 215 216 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 217 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 218 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 219 DELAY(1); 220 v = CSR_READ_4(sc, AGE_MDIO); 221 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 222 break; 223 } 224 225 if (i == 0) { 226 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 227 return (0); 228 } 229 230 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 231 } 232 233 /* 234 * Write a PHY register on the MII of the L1. 235 */ 236 static int 237 age_miibus_writereg(device_t dev, int phy, int reg, int val) 238 { 239 struct age_softc *sc; 240 uint32_t v; 241 int i; 242 243 sc = device_get_softc(dev); 244 245 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 246 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 247 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 248 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 249 DELAY(1); 250 v = CSR_READ_4(sc, AGE_MDIO); 251 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 252 break; 253 } 254 255 if (i == 0) 256 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 257 258 return (0); 259 } 260 261 /* 262 * Callback from MII layer when media changes. 263 */ 264 static void 265 age_miibus_statchg(device_t dev) 266 { 267 struct age_softc *sc; 268 269 sc = device_get_softc(dev); 270 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 271 } 272 273 /* 274 * Get the current interface media status. 275 */ 276 static void 277 age_mediastatus(if_t ifp, struct ifmediareq *ifmr) 278 { 279 struct age_softc *sc; 280 struct mii_data *mii; 281 282 sc = if_getsoftc(ifp); 283 AGE_LOCK(sc); 284 mii = device_get_softc(sc->age_miibus); 285 286 mii_pollstat(mii); 287 ifmr->ifm_status = mii->mii_media_status; 288 ifmr->ifm_active = mii->mii_media_active; 289 AGE_UNLOCK(sc); 290 } 291 292 /* 293 * Set hardware to newly-selected media. 294 */ 295 static int 296 age_mediachange(if_t ifp) 297 { 298 struct age_softc *sc; 299 struct mii_data *mii; 300 struct mii_softc *miisc; 301 int error; 302 303 sc = if_getsoftc(ifp); 304 AGE_LOCK(sc); 305 mii = device_get_softc(sc->age_miibus); 306 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 307 PHY_RESET(miisc); 308 error = mii_mediachg(mii); 309 AGE_UNLOCK(sc); 310 311 return (error); 312 } 313 314 static int 315 age_probe(device_t dev) 316 { 317 struct age_dev *sp; 318 int i; 319 uint16_t vendor, devid; 320 321 vendor = pci_get_vendor(dev); 322 devid = pci_get_device(dev); 323 sp = age_devs; 324 for (i = 0; i < nitems(age_devs); i++, sp++) { 325 if (vendor == sp->age_vendorid && 326 devid == sp->age_deviceid) { 327 device_set_desc(dev, sp->age_name); 328 return (BUS_PROBE_DEFAULT); 329 } 330 } 331 332 return (ENXIO); 333 } 334 335 static void 336 age_get_macaddr(struct age_softc *sc) 337 { 338 uint32_t ea[2], reg; 339 int i, vpdc; 340 341 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 342 if ((reg & SPI_VPD_ENB) != 0) { 343 /* Get VPD stored in TWSI EEPROM. */ 344 reg &= ~SPI_VPD_ENB; 345 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 346 } 347 348 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 349 /* 350 * PCI VPD capability found, let TWSI reload EEPROM. 351 * This will set ethernet address of controller. 352 */ 353 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 354 TWSI_CTRL_SW_LD_START); 355 for (i = 100; i > 0; i--) { 356 DELAY(1000); 357 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 358 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 359 break; 360 } 361 if (i == 0) 362 device_printf(sc->age_dev, 363 "reloading EEPROM timeout!\n"); 364 } else { 365 if (bootverbose) 366 device_printf(sc->age_dev, 367 "PCI VPD capability not found!\n"); 368 } 369 370 ea[0] = CSR_READ_4(sc, AGE_PAR0); 371 ea[1] = CSR_READ_4(sc, AGE_PAR1); 372 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 373 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 374 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 375 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 376 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 377 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 378 } 379 380 static void 381 age_phy_reset(struct age_softc *sc) 382 { 383 uint16_t reg, pn; 384 int i, linkup; 385 386 /* Reset PHY. */ 387 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 388 DELAY(2000); 389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 390 DELAY(2000); 391 392 #define ATPHY_DBG_ADDR 0x1D 393 #define ATPHY_DBG_DATA 0x1E 394 #define ATPHY_CDTC 0x16 395 #define PHY_CDTC_ENB 0x0001 396 #define PHY_CDTC_POFF 8 397 #define ATPHY_CDTS 0x1C 398 #define PHY_CDTS_STAT_OK 0x0000 399 #define PHY_CDTS_STAT_SHORT 0x0100 400 #define PHY_CDTS_STAT_OPEN 0x0200 401 #define PHY_CDTS_STAT_INVAL 0x0300 402 #define PHY_CDTS_STAT_MASK 0x0300 403 404 /* Check power saving mode. Magic from Linux. */ 405 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 406 for (linkup = 0, pn = 0; pn < 4; pn++) { 407 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 408 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 409 for (i = 200; i > 0; i--) { 410 DELAY(1000); 411 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 412 ATPHY_CDTC); 413 if ((reg & PHY_CDTC_ENB) == 0) 414 break; 415 } 416 DELAY(1000); 417 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 418 ATPHY_CDTS); 419 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 420 linkup++; 421 break; 422 } 423 } 424 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 425 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 426 if (linkup == 0) { 427 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 428 ATPHY_DBG_ADDR, 0); 429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 430 ATPHY_DBG_DATA, 0x124E); 431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 432 ATPHY_DBG_ADDR, 1); 433 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 434 ATPHY_DBG_DATA); 435 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_DATA, reg | 0x03); 437 /* XXX */ 438 DELAY(1500 * 1000); 439 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 440 ATPHY_DBG_ADDR, 0); 441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_DATA, 0x024E); 443 } 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 #undef ATPHY_CDTC 448 #undef PHY_CDTC_ENB 449 #undef PHY_CDTC_POFF 450 #undef ATPHY_CDTS 451 #undef PHY_CDTS_STAT_OK 452 #undef PHY_CDTS_STAT_SHORT 453 #undef PHY_CDTS_STAT_OPEN 454 #undef PHY_CDTS_STAT_INVAL 455 #undef PHY_CDTS_STAT_MASK 456 } 457 458 static int 459 age_attach(device_t dev) 460 { 461 struct age_softc *sc; 462 if_t ifp; 463 uint16_t burst; 464 int error, i, msic, msixc, pmc; 465 466 error = 0; 467 sc = device_get_softc(dev); 468 sc->age_dev = dev; 469 470 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 471 MTX_DEF); 472 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 473 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 474 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 475 476 /* Map the device. */ 477 pci_enable_busmaster(dev); 478 sc->age_res_spec = age_res_spec_mem; 479 sc->age_irq_spec = age_irq_spec_legacy; 480 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 481 if (error != 0) { 482 device_printf(dev, "cannot allocate memory resources.\n"); 483 goto fail; 484 } 485 486 /* Set PHY address. */ 487 sc->age_phyaddr = AGE_PHY_ADDR; 488 489 /* Reset PHY. */ 490 age_phy_reset(sc); 491 492 /* Reset the ethernet controller. */ 493 age_reset(sc); 494 495 /* Get PCI and chip id/revision. */ 496 sc->age_rev = pci_get_revid(dev); 497 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 498 MASTER_CHIP_REV_SHIFT; 499 if (bootverbose) { 500 device_printf(dev, "PCI device revision : 0x%04x\n", 501 sc->age_rev); 502 device_printf(dev, "Chip id/revision : 0x%04x\n", 503 sc->age_chip_rev); 504 } 505 506 /* 507 * XXX 508 * Unintialized hardware returns an invalid chip id/revision 509 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 510 * unplugged cable results in putting hardware into automatic 511 * power down mode which in turn returns invalld chip revision. 512 */ 513 if (sc->age_chip_rev == 0xFFFF) { 514 device_printf(dev,"invalid chip revision : 0x%04x -- " 515 "not initialized?\n", sc->age_chip_rev); 516 error = ENXIO; 517 goto fail; 518 } 519 520 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 521 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 522 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 523 524 /* Allocate IRQ resources. */ 525 msixc = pci_msix_count(dev); 526 msic = pci_msi_count(dev); 527 if (bootverbose) { 528 device_printf(dev, "MSIX count : %d\n", msixc); 529 device_printf(dev, "MSI count : %d\n", msic); 530 } 531 532 /* Prefer MSIX over MSI. */ 533 if (msix_disable == 0 || msi_disable == 0) { 534 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 535 pci_alloc_msix(dev, &msixc) == 0) { 536 if (msic == AGE_MSIX_MESSAGES) { 537 device_printf(dev, "Using %d MSIX messages.\n", 538 msixc); 539 sc->age_flags |= AGE_FLAG_MSIX; 540 sc->age_irq_spec = age_irq_spec_msix; 541 } else 542 pci_release_msi(dev); 543 } 544 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 545 msic == AGE_MSI_MESSAGES && 546 pci_alloc_msi(dev, &msic) == 0) { 547 if (msic == AGE_MSI_MESSAGES) { 548 device_printf(dev, "Using %d MSI messages.\n", 549 msic); 550 sc->age_flags |= AGE_FLAG_MSI; 551 sc->age_irq_spec = age_irq_spec_msi; 552 } else 553 pci_release_msi(dev); 554 } 555 } 556 557 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 558 if (error != 0) { 559 device_printf(dev, "cannot allocate IRQ resources.\n"); 560 goto fail; 561 } 562 563 /* Get DMA parameters from PCIe device control register. */ 564 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 565 sc->age_flags |= AGE_FLAG_PCIE; 566 burst = pci_read_config(dev, i + 0x08, 2); 567 /* Max read request size. */ 568 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 569 DMA_CFG_RD_BURST_SHIFT; 570 /* Max payload size. */ 571 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 572 DMA_CFG_WR_BURST_SHIFT; 573 if (bootverbose) { 574 device_printf(dev, "Read request size : %d bytes.\n", 575 128 << ((burst >> 12) & 0x07)); 576 device_printf(dev, "TLP payload size : %d bytes.\n", 577 128 << ((burst >> 5) & 0x07)); 578 } 579 } else { 580 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 581 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 582 } 583 584 /* Create device sysctl node. */ 585 age_sysctl_node(sc); 586 587 if ((error = age_dma_alloc(sc)) != 0) 588 goto fail; 589 590 /* Load station address. */ 591 age_get_macaddr(sc); 592 593 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 594 if (ifp == NULL) { 595 device_printf(dev, "cannot allocate ifnet structure.\n"); 596 error = ENXIO; 597 goto fail; 598 } 599 600 if_setsoftc(ifp, sc); 601 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 602 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 603 if_setioctlfn(ifp, age_ioctl); 604 if_setstartfn(ifp, age_start); 605 if_setinitfn(ifp, age_init); 606 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1); 607 if_setsendqready(ifp); 608 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 609 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO); 610 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 611 sc->age_flags |= AGE_FLAG_PMCAP; 612 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 613 } 614 if_setcapenable(ifp, if_getcapabilities(ifp)); 615 616 /* Set up MII bus. */ 617 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 618 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 619 0); 620 if (error != 0) { 621 device_printf(dev, "attaching PHYs failed\n"); 622 goto fail; 623 } 624 625 ether_ifattach(ifp, sc->age_eaddr); 626 627 /* VLAN capability setup. */ 628 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 629 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 630 if_setcapenable(ifp, if_getcapabilities(ifp)); 631 632 /* Tell the upper layer(s) we support long frames. */ 633 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 634 635 /* Create local taskq. */ 636 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 637 taskqueue_thread_enqueue, &sc->age_tq); 638 if (sc->age_tq == NULL) { 639 device_printf(dev, "could not create taskqueue.\n"); 640 ether_ifdetach(ifp); 641 error = ENXIO; 642 goto fail; 643 } 644 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 645 device_get_nameunit(sc->age_dev)); 646 647 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 648 msic = AGE_MSIX_MESSAGES; 649 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 650 msic = AGE_MSI_MESSAGES; 651 else 652 msic = 1; 653 for (i = 0; i < msic; i++) { 654 error = bus_setup_intr(dev, sc->age_irq[i], 655 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 656 &sc->age_intrhand[i]); 657 if (error != 0) 658 break; 659 } 660 if (error != 0) { 661 device_printf(dev, "could not set up interrupt handler.\n"); 662 taskqueue_free(sc->age_tq); 663 sc->age_tq = NULL; 664 ether_ifdetach(ifp); 665 goto fail; 666 } 667 668 fail: 669 if (error != 0) 670 age_detach(dev); 671 672 return (error); 673 } 674 675 static int 676 age_detach(device_t dev) 677 { 678 struct age_softc *sc; 679 if_t ifp; 680 int i, msic; 681 682 sc = device_get_softc(dev); 683 684 ifp = sc->age_ifp; 685 if (device_is_attached(dev)) { 686 AGE_LOCK(sc); 687 sc->age_flags |= AGE_FLAG_DETACH; 688 age_stop(sc); 689 AGE_UNLOCK(sc); 690 callout_drain(&sc->age_tick_ch); 691 taskqueue_drain(sc->age_tq, &sc->age_int_task); 692 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 693 ether_ifdetach(ifp); 694 } 695 696 if (sc->age_tq != NULL) { 697 taskqueue_drain(sc->age_tq, &sc->age_int_task); 698 taskqueue_free(sc->age_tq); 699 sc->age_tq = NULL; 700 } 701 702 if (sc->age_miibus != NULL) { 703 device_delete_child(dev, sc->age_miibus); 704 sc->age_miibus = NULL; 705 } 706 bus_generic_detach(dev); 707 age_dma_free(sc); 708 709 if (ifp != NULL) { 710 if_free(ifp); 711 sc->age_ifp = NULL; 712 } 713 714 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 715 msic = AGE_MSIX_MESSAGES; 716 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 717 msic = AGE_MSI_MESSAGES; 718 else 719 msic = 1; 720 for (i = 0; i < msic; i++) { 721 if (sc->age_intrhand[i] != NULL) { 722 bus_teardown_intr(dev, sc->age_irq[i], 723 sc->age_intrhand[i]); 724 sc->age_intrhand[i] = NULL; 725 } 726 } 727 728 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 729 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 730 pci_release_msi(dev); 731 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 732 mtx_destroy(&sc->age_mtx); 733 734 return (0); 735 } 736 737 static void 738 age_sysctl_node(struct age_softc *sc) 739 { 740 int error; 741 742 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 743 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 744 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 745 sc, 0, sysctl_age_stats, "I", "Statistics"); 746 747 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 748 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 749 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 750 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", 751 "age interrupt moderation"); 752 753 /* Pull in device tunables. */ 754 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 755 error = resource_int_value(device_get_name(sc->age_dev), 756 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 757 if (error == 0) { 758 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 759 sc->age_int_mod > AGE_IM_TIMER_MAX) { 760 device_printf(sc->age_dev, 761 "int_mod value out of range; using default: %d\n", 762 AGE_IM_TIMER_DEFAULT); 763 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 764 } 765 } 766 767 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 768 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 769 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 770 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", 771 "max number of Rx events to process"); 772 773 /* Pull in device tunables. */ 774 sc->age_process_limit = AGE_PROC_DEFAULT; 775 error = resource_int_value(device_get_name(sc->age_dev), 776 device_get_unit(sc->age_dev), "process_limit", 777 &sc->age_process_limit); 778 if (error == 0) { 779 if (sc->age_process_limit < AGE_PROC_MIN || 780 sc->age_process_limit > AGE_PROC_MAX) { 781 device_printf(sc->age_dev, 782 "process_limit value out of range; " 783 "using default: %d\n", AGE_PROC_DEFAULT); 784 sc->age_process_limit = AGE_PROC_DEFAULT; 785 } 786 } 787 } 788 789 struct age_dmamap_arg { 790 bus_addr_t age_busaddr; 791 }; 792 793 static void 794 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 795 { 796 struct age_dmamap_arg *ctx; 797 798 if (error != 0) 799 return; 800 801 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 802 803 ctx = (struct age_dmamap_arg *)arg; 804 ctx->age_busaddr = segs[0].ds_addr; 805 } 806 807 /* 808 * Attansic L1 controller have single register to specify high 809 * address part of DMA blocks. So all descriptor structures and 810 * DMA memory blocks should have the same high address of given 811 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 812 */ 813 static int 814 age_check_boundary(struct age_softc *sc) 815 { 816 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 817 bus_addr_t cmb_block_end, smb_block_end; 818 819 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 820 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 821 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 822 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 823 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 824 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 825 826 if ((AGE_ADDR_HI(tx_ring_end) != 827 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 828 (AGE_ADDR_HI(rx_ring_end) != 829 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 830 (AGE_ADDR_HI(rr_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 832 (AGE_ADDR_HI(cmb_block_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 834 (AGE_ADDR_HI(smb_block_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 836 return (EFBIG); 837 838 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 839 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 840 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 841 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 842 return (EFBIG); 843 844 return (0); 845 } 846 847 static int 848 age_dma_alloc(struct age_softc *sc) 849 { 850 struct age_txdesc *txd; 851 struct age_rxdesc *rxd; 852 bus_addr_t lowaddr; 853 struct age_dmamap_arg ctx; 854 int error, i; 855 856 lowaddr = BUS_SPACE_MAXADDR; 857 858 again: 859 /* Create parent ring/DMA block tag. */ 860 error = bus_dma_tag_create( 861 bus_get_dma_tag(sc->age_dev), /* parent */ 862 1, 0, /* alignment, boundary */ 863 lowaddr, /* lowaddr */ 864 BUS_SPACE_MAXADDR, /* highaddr */ 865 NULL, NULL, /* filter, filterarg */ 866 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 867 0, /* nsegments */ 868 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 869 0, /* flags */ 870 NULL, NULL, /* lockfunc, lockarg */ 871 &sc->age_cdata.age_parent_tag); 872 if (error != 0) { 873 device_printf(sc->age_dev, 874 "could not create parent DMA tag.\n"); 875 goto fail; 876 } 877 878 /* Create tag for Tx ring. */ 879 error = bus_dma_tag_create( 880 sc->age_cdata.age_parent_tag, /* parent */ 881 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 882 BUS_SPACE_MAXADDR, /* lowaddr */ 883 BUS_SPACE_MAXADDR, /* highaddr */ 884 NULL, NULL, /* filter, filterarg */ 885 AGE_TX_RING_SZ, /* maxsize */ 886 1, /* nsegments */ 887 AGE_TX_RING_SZ, /* maxsegsize */ 888 0, /* flags */ 889 NULL, NULL, /* lockfunc, lockarg */ 890 &sc->age_cdata.age_tx_ring_tag); 891 if (error != 0) { 892 device_printf(sc->age_dev, 893 "could not create Tx ring DMA tag.\n"); 894 goto fail; 895 } 896 897 /* Create tag for Rx ring. */ 898 error = bus_dma_tag_create( 899 sc->age_cdata.age_parent_tag, /* parent */ 900 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 901 BUS_SPACE_MAXADDR, /* lowaddr */ 902 BUS_SPACE_MAXADDR, /* highaddr */ 903 NULL, NULL, /* filter, filterarg */ 904 AGE_RX_RING_SZ, /* maxsize */ 905 1, /* nsegments */ 906 AGE_RX_RING_SZ, /* maxsegsize */ 907 0, /* flags */ 908 NULL, NULL, /* lockfunc, lockarg */ 909 &sc->age_cdata.age_rx_ring_tag); 910 if (error != 0) { 911 device_printf(sc->age_dev, 912 "could not create Rx ring DMA tag.\n"); 913 goto fail; 914 } 915 916 /* Create tag for Rx return ring. */ 917 error = bus_dma_tag_create( 918 sc->age_cdata.age_parent_tag, /* parent */ 919 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 920 BUS_SPACE_MAXADDR, /* lowaddr */ 921 BUS_SPACE_MAXADDR, /* highaddr */ 922 NULL, NULL, /* filter, filterarg */ 923 AGE_RR_RING_SZ, /* maxsize */ 924 1, /* nsegments */ 925 AGE_RR_RING_SZ, /* maxsegsize */ 926 0, /* flags */ 927 NULL, NULL, /* lockfunc, lockarg */ 928 &sc->age_cdata.age_rr_ring_tag); 929 if (error != 0) { 930 device_printf(sc->age_dev, 931 "could not create Rx return ring DMA tag.\n"); 932 goto fail; 933 } 934 935 /* Create tag for coalesing message block. */ 936 error = bus_dma_tag_create( 937 sc->age_cdata.age_parent_tag, /* parent */ 938 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 939 BUS_SPACE_MAXADDR, /* lowaddr */ 940 BUS_SPACE_MAXADDR, /* highaddr */ 941 NULL, NULL, /* filter, filterarg */ 942 AGE_CMB_BLOCK_SZ, /* maxsize */ 943 1, /* nsegments */ 944 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 945 0, /* flags */ 946 NULL, NULL, /* lockfunc, lockarg */ 947 &sc->age_cdata.age_cmb_block_tag); 948 if (error != 0) { 949 device_printf(sc->age_dev, 950 "could not create CMB DMA tag.\n"); 951 goto fail; 952 } 953 954 /* Create tag for statistics message block. */ 955 error = bus_dma_tag_create( 956 sc->age_cdata.age_parent_tag, /* parent */ 957 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 958 BUS_SPACE_MAXADDR, /* lowaddr */ 959 BUS_SPACE_MAXADDR, /* highaddr */ 960 NULL, NULL, /* filter, filterarg */ 961 AGE_SMB_BLOCK_SZ, /* maxsize */ 962 1, /* nsegments */ 963 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 964 0, /* flags */ 965 NULL, NULL, /* lockfunc, lockarg */ 966 &sc->age_cdata.age_smb_block_tag); 967 if (error != 0) { 968 device_printf(sc->age_dev, 969 "could not create SMB DMA tag.\n"); 970 goto fail; 971 } 972 973 /* Allocate DMA'able memory and load the DMA map. */ 974 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 975 (void **)&sc->age_rdata.age_tx_ring, 976 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 977 &sc->age_cdata.age_tx_ring_map); 978 if (error != 0) { 979 device_printf(sc->age_dev, 980 "could not allocate DMA'able memory for Tx ring.\n"); 981 goto fail; 982 } 983 ctx.age_busaddr = 0; 984 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 985 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 986 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 987 if (error != 0 || ctx.age_busaddr == 0) { 988 device_printf(sc->age_dev, 989 "could not load DMA'able memory for Tx ring.\n"); 990 goto fail; 991 } 992 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 993 /* Rx ring */ 994 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 995 (void **)&sc->age_rdata.age_rx_ring, 996 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 997 &sc->age_cdata.age_rx_ring_map); 998 if (error != 0) { 999 device_printf(sc->age_dev, 1000 "could not allocate DMA'able memory for Rx ring.\n"); 1001 goto fail; 1002 } 1003 ctx.age_busaddr = 0; 1004 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1005 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1006 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1007 if (error != 0 || ctx.age_busaddr == 0) { 1008 device_printf(sc->age_dev, 1009 "could not load DMA'able memory for Rx ring.\n"); 1010 goto fail; 1011 } 1012 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1013 /* Rx return ring */ 1014 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1015 (void **)&sc->age_rdata.age_rr_ring, 1016 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1017 &sc->age_cdata.age_rr_ring_map); 1018 if (error != 0) { 1019 device_printf(sc->age_dev, 1020 "could not allocate DMA'able memory for Rx return ring.\n"); 1021 goto fail; 1022 } 1023 ctx.age_busaddr = 0; 1024 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1025 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1026 AGE_RR_RING_SZ, age_dmamap_cb, 1027 &ctx, 0); 1028 if (error != 0 || ctx.age_busaddr == 0) { 1029 device_printf(sc->age_dev, 1030 "could not load DMA'able memory for Rx return ring.\n"); 1031 goto fail; 1032 } 1033 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1034 /* CMB block */ 1035 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1036 (void **)&sc->age_rdata.age_cmb_block, 1037 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1038 &sc->age_cdata.age_cmb_block_map); 1039 if (error != 0) { 1040 device_printf(sc->age_dev, 1041 "could not allocate DMA'able memory for CMB block.\n"); 1042 goto fail; 1043 } 1044 ctx.age_busaddr = 0; 1045 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1046 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1047 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1048 if (error != 0 || ctx.age_busaddr == 0) { 1049 device_printf(sc->age_dev, 1050 "could not load DMA'able memory for CMB block.\n"); 1051 goto fail; 1052 } 1053 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1054 /* SMB block */ 1055 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1056 (void **)&sc->age_rdata.age_smb_block, 1057 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1058 &sc->age_cdata.age_smb_block_map); 1059 if (error != 0) { 1060 device_printf(sc->age_dev, 1061 "could not allocate DMA'able memory for SMB block.\n"); 1062 goto fail; 1063 } 1064 ctx.age_busaddr = 0; 1065 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1066 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1067 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1068 if (error != 0 || ctx.age_busaddr == 0) { 1069 device_printf(sc->age_dev, 1070 "could not load DMA'able memory for SMB block.\n"); 1071 goto fail; 1072 } 1073 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1074 1075 /* 1076 * All ring buffer and DMA blocks should have the same 1077 * high address part of 64bit DMA address space. 1078 */ 1079 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1080 (error = age_check_boundary(sc)) != 0) { 1081 device_printf(sc->age_dev, "4GB boundary crossed, " 1082 "switching to 32bit DMA addressing mode.\n"); 1083 age_dma_free(sc); 1084 /* Limit DMA address space to 32bit and try again. */ 1085 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1086 goto again; 1087 } 1088 1089 /* 1090 * Create Tx/Rx buffer parent tag. 1091 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1092 * so it needs separate parent DMA tag. 1093 * XXX 1094 * It seems enabling 64bit DMA causes data corruption. Limit 1095 * DMA address space to 32bit. 1096 */ 1097 error = bus_dma_tag_create( 1098 bus_get_dma_tag(sc->age_dev), /* parent */ 1099 1, 0, /* alignment, boundary */ 1100 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1101 BUS_SPACE_MAXADDR, /* highaddr */ 1102 NULL, NULL, /* filter, filterarg */ 1103 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1104 0, /* nsegments */ 1105 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1106 0, /* flags */ 1107 NULL, NULL, /* lockfunc, lockarg */ 1108 &sc->age_cdata.age_buffer_tag); 1109 if (error != 0) { 1110 device_printf(sc->age_dev, 1111 "could not create parent buffer DMA tag.\n"); 1112 goto fail; 1113 } 1114 1115 /* Create tag for Tx buffers. */ 1116 error = bus_dma_tag_create( 1117 sc->age_cdata.age_buffer_tag, /* parent */ 1118 1, 0, /* alignment, boundary */ 1119 BUS_SPACE_MAXADDR, /* lowaddr */ 1120 BUS_SPACE_MAXADDR, /* highaddr */ 1121 NULL, NULL, /* filter, filterarg */ 1122 AGE_TSO_MAXSIZE, /* maxsize */ 1123 AGE_MAXTXSEGS, /* nsegments */ 1124 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1125 0, /* flags */ 1126 NULL, NULL, /* lockfunc, lockarg */ 1127 &sc->age_cdata.age_tx_tag); 1128 if (error != 0) { 1129 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1130 goto fail; 1131 } 1132 1133 /* Create tag for Rx buffers. */ 1134 error = bus_dma_tag_create( 1135 sc->age_cdata.age_buffer_tag, /* parent */ 1136 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1137 BUS_SPACE_MAXADDR, /* lowaddr */ 1138 BUS_SPACE_MAXADDR, /* highaddr */ 1139 NULL, NULL, /* filter, filterarg */ 1140 MCLBYTES, /* maxsize */ 1141 1, /* nsegments */ 1142 MCLBYTES, /* maxsegsize */ 1143 0, /* flags */ 1144 NULL, NULL, /* lockfunc, lockarg */ 1145 &sc->age_cdata.age_rx_tag); 1146 if (error != 0) { 1147 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1148 goto fail; 1149 } 1150 1151 /* Create DMA maps for Tx buffers. */ 1152 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1153 txd = &sc->age_cdata.age_txdesc[i]; 1154 txd->tx_m = NULL; 1155 txd->tx_dmamap = NULL; 1156 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1157 &txd->tx_dmamap); 1158 if (error != 0) { 1159 device_printf(sc->age_dev, 1160 "could not create Tx dmamap.\n"); 1161 goto fail; 1162 } 1163 } 1164 /* Create DMA maps for Rx buffers. */ 1165 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1166 &sc->age_cdata.age_rx_sparemap)) != 0) { 1167 device_printf(sc->age_dev, 1168 "could not create spare Rx dmamap.\n"); 1169 goto fail; 1170 } 1171 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1172 rxd = &sc->age_cdata.age_rxdesc[i]; 1173 rxd->rx_m = NULL; 1174 rxd->rx_dmamap = NULL; 1175 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1176 &rxd->rx_dmamap); 1177 if (error != 0) { 1178 device_printf(sc->age_dev, 1179 "could not create Rx dmamap.\n"); 1180 goto fail; 1181 } 1182 } 1183 1184 fail: 1185 return (error); 1186 } 1187 1188 static void 1189 age_dma_free(struct age_softc *sc) 1190 { 1191 struct age_txdesc *txd; 1192 struct age_rxdesc *rxd; 1193 int i; 1194 1195 /* Tx buffers */ 1196 if (sc->age_cdata.age_tx_tag != NULL) { 1197 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1198 txd = &sc->age_cdata.age_txdesc[i]; 1199 if (txd->tx_dmamap != NULL) { 1200 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1201 txd->tx_dmamap); 1202 txd->tx_dmamap = NULL; 1203 } 1204 } 1205 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1206 sc->age_cdata.age_tx_tag = NULL; 1207 } 1208 /* Rx buffers */ 1209 if (sc->age_cdata.age_rx_tag != NULL) { 1210 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1211 rxd = &sc->age_cdata.age_rxdesc[i]; 1212 if (rxd->rx_dmamap != NULL) { 1213 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1214 rxd->rx_dmamap); 1215 rxd->rx_dmamap = NULL; 1216 } 1217 } 1218 if (sc->age_cdata.age_rx_sparemap != NULL) { 1219 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1220 sc->age_cdata.age_rx_sparemap); 1221 sc->age_cdata.age_rx_sparemap = NULL; 1222 } 1223 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1224 sc->age_cdata.age_rx_tag = NULL; 1225 } 1226 /* Tx ring. */ 1227 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1228 if (sc->age_rdata.age_tx_ring_paddr != 0) 1229 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1230 sc->age_cdata.age_tx_ring_map); 1231 if (sc->age_rdata.age_tx_ring != NULL) 1232 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1233 sc->age_rdata.age_tx_ring, 1234 sc->age_cdata.age_tx_ring_map); 1235 sc->age_rdata.age_tx_ring_paddr = 0; 1236 sc->age_rdata.age_tx_ring = NULL; 1237 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1238 sc->age_cdata.age_tx_ring_tag = NULL; 1239 } 1240 /* Rx ring. */ 1241 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1242 if (sc->age_rdata.age_rx_ring_paddr != 0) 1243 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1244 sc->age_cdata.age_rx_ring_map); 1245 if (sc->age_rdata.age_rx_ring != NULL) 1246 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1247 sc->age_rdata.age_rx_ring, 1248 sc->age_cdata.age_rx_ring_map); 1249 sc->age_rdata.age_rx_ring_paddr = 0; 1250 sc->age_rdata.age_rx_ring = NULL; 1251 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1252 sc->age_cdata.age_rx_ring_tag = NULL; 1253 } 1254 /* Rx return ring. */ 1255 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1256 if (sc->age_rdata.age_rr_ring_paddr != 0) 1257 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1258 sc->age_cdata.age_rr_ring_map); 1259 if (sc->age_rdata.age_rr_ring != NULL) 1260 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1261 sc->age_rdata.age_rr_ring, 1262 sc->age_cdata.age_rr_ring_map); 1263 sc->age_rdata.age_rr_ring_paddr = 0; 1264 sc->age_rdata.age_rr_ring = NULL; 1265 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1266 sc->age_cdata.age_rr_ring_tag = NULL; 1267 } 1268 /* CMB block */ 1269 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1270 if (sc->age_rdata.age_cmb_block_paddr != 0) 1271 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1272 sc->age_cdata.age_cmb_block_map); 1273 if (sc->age_rdata.age_cmb_block != NULL) 1274 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1275 sc->age_rdata.age_cmb_block, 1276 sc->age_cdata.age_cmb_block_map); 1277 sc->age_rdata.age_cmb_block_paddr = 0; 1278 sc->age_rdata.age_cmb_block = NULL; 1279 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1280 sc->age_cdata.age_cmb_block_tag = NULL; 1281 } 1282 /* SMB block */ 1283 if (sc->age_cdata.age_smb_block_tag != NULL) { 1284 if (sc->age_rdata.age_smb_block_paddr != 0) 1285 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1286 sc->age_cdata.age_smb_block_map); 1287 if (sc->age_rdata.age_smb_block != NULL) 1288 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1289 sc->age_rdata.age_smb_block, 1290 sc->age_cdata.age_smb_block_map); 1291 sc->age_rdata.age_smb_block_paddr = 0; 1292 sc->age_rdata.age_smb_block = NULL; 1293 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1294 sc->age_cdata.age_smb_block_tag = NULL; 1295 } 1296 1297 if (sc->age_cdata.age_buffer_tag != NULL) { 1298 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1299 sc->age_cdata.age_buffer_tag = NULL; 1300 } 1301 if (sc->age_cdata.age_parent_tag != NULL) { 1302 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1303 sc->age_cdata.age_parent_tag = NULL; 1304 } 1305 } 1306 1307 /* 1308 * Make sure the interface is stopped at reboot time. 1309 */ 1310 static int 1311 age_shutdown(device_t dev) 1312 { 1313 1314 return (age_suspend(dev)); 1315 } 1316 1317 static void 1318 age_setwol(struct age_softc *sc) 1319 { 1320 if_t ifp; 1321 struct mii_data *mii; 1322 uint32_t reg, pmcs; 1323 uint16_t pmstat; 1324 int aneg, i, pmc; 1325 1326 AGE_LOCK_ASSERT(sc); 1327 1328 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1329 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1330 /* 1331 * No PME capability, PHY power down. 1332 * XXX 1333 * Due to an unknown reason powering down PHY resulted 1334 * in unexpected results such as inaccessbility of 1335 * hardware of freshly rebooted system. Disable 1336 * powering down PHY until I got more information for 1337 * Attansic/Atheros PHY hardwares. 1338 */ 1339 #ifdef notyet 1340 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1341 MII_BMCR, BMCR_PDOWN); 1342 #endif 1343 return; 1344 } 1345 1346 ifp = sc->age_ifp; 1347 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1348 /* 1349 * Note, this driver resets the link speed to 10/100Mbps with 1350 * auto-negotiation but we don't know whether that operation 1351 * would succeed or not as it have no control after powering 1352 * off. If the renegotiation fail WOL may not work. Running 1353 * at 1Gbps will draw more power than 375mA at 3.3V which is 1354 * specified in PCI specification and that would result in 1355 * complete shutdowning power to ethernet controller. 1356 * 1357 * TODO 1358 * Save current negotiated media speed/duplex/flow-control 1359 * to softc and restore the same link again after resuming. 1360 * PHY handling such as power down/resetting to 100Mbps 1361 * may be better handled in suspend method in phy driver. 1362 */ 1363 mii = device_get_softc(sc->age_miibus); 1364 mii_pollstat(mii); 1365 aneg = 0; 1366 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1367 switch IFM_SUBTYPE(mii->mii_media_active) { 1368 case IFM_10_T: 1369 case IFM_100_TX: 1370 goto got_link; 1371 case IFM_1000_T: 1372 aneg++; 1373 default: 1374 break; 1375 } 1376 } 1377 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1378 MII_100T2CR, 0); 1379 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1380 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1381 ANAR_10 | ANAR_CSMA); 1382 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1383 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1384 DELAY(1000); 1385 if (aneg != 0) { 1386 /* Poll link state until age(4) get a 10/100 link. */ 1387 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1388 mii_pollstat(mii); 1389 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1390 switch (IFM_SUBTYPE( 1391 mii->mii_media_active)) { 1392 case IFM_10_T: 1393 case IFM_100_TX: 1394 age_mac_config(sc); 1395 goto got_link; 1396 default: 1397 break; 1398 } 1399 } 1400 AGE_UNLOCK(sc); 1401 pause("agelnk", hz); 1402 AGE_LOCK(sc); 1403 } 1404 if (i == MII_ANEGTICKS_GIGE) 1405 device_printf(sc->age_dev, 1406 "establishing link failed, " 1407 "WOL may not work!"); 1408 } 1409 /* 1410 * No link, force MAC to have 100Mbps, full-duplex link. 1411 * This is the last resort and may/may not work. 1412 */ 1413 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1414 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1415 age_mac_config(sc); 1416 } 1417 1418 got_link: 1419 pmcs = 0; 1420 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1421 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1422 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1423 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1424 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1425 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1426 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1427 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1428 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1429 reg |= MAC_CFG_RX_ENB; 1430 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1431 } 1432 1433 /* Request PME. */ 1434 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1435 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1436 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1437 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1438 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1439 #ifdef notyet 1440 /* See above for powering down PHY issues. */ 1441 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1442 /* No WOL, PHY power down. */ 1443 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1444 MII_BMCR, BMCR_PDOWN); 1445 } 1446 #endif 1447 } 1448 1449 static int 1450 age_suspend(device_t dev) 1451 { 1452 struct age_softc *sc; 1453 1454 sc = device_get_softc(dev); 1455 1456 AGE_LOCK(sc); 1457 age_stop(sc); 1458 age_setwol(sc); 1459 AGE_UNLOCK(sc); 1460 1461 return (0); 1462 } 1463 1464 static int 1465 age_resume(device_t dev) 1466 { 1467 struct age_softc *sc; 1468 if_t ifp; 1469 1470 sc = device_get_softc(dev); 1471 1472 AGE_LOCK(sc); 1473 age_phy_reset(sc); 1474 ifp = sc->age_ifp; 1475 if ((if_getflags(ifp) & IFF_UP) != 0) 1476 age_init_locked(sc); 1477 1478 AGE_UNLOCK(sc); 1479 1480 return (0); 1481 } 1482 1483 static int 1484 age_encap(struct age_softc *sc, struct mbuf **m_head) 1485 { 1486 struct age_txdesc *txd, *txd_last; 1487 struct tx_desc *desc; 1488 struct mbuf *m; 1489 struct ip *ip; 1490 struct tcphdr *tcp; 1491 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1492 bus_dmamap_t map; 1493 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1494 int error, i, nsegs, prod, si; 1495 1496 AGE_LOCK_ASSERT(sc); 1497 1498 M_ASSERTPKTHDR((*m_head)); 1499 1500 m = *m_head; 1501 ip = NULL; 1502 tcp = NULL; 1503 cflags = vtag = 0; 1504 ip_off = poff = 0; 1505 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1506 /* 1507 * L1 requires offset of TCP/UDP payload in its Tx 1508 * descriptor to perform hardware Tx checksum offload. 1509 * Additionally, TSO requires IP/TCP header size and 1510 * modification of IP/TCP header in order to make TSO 1511 * engine work. This kind of operation takes many CPU 1512 * cycles on FreeBSD so fast host CPU is needed to get 1513 * smooth TSO performance. 1514 */ 1515 struct ether_header *eh; 1516 1517 if (M_WRITABLE(m) == 0) { 1518 /* Get a writable copy. */ 1519 m = m_dup(*m_head, M_NOWAIT); 1520 /* Release original mbufs. */ 1521 m_freem(*m_head); 1522 if (m == NULL) { 1523 *m_head = NULL; 1524 return (ENOBUFS); 1525 } 1526 *m_head = m; 1527 } 1528 ip_off = sizeof(struct ether_header); 1529 m = m_pullup(m, ip_off); 1530 if (m == NULL) { 1531 *m_head = NULL; 1532 return (ENOBUFS); 1533 } 1534 eh = mtod(m, struct ether_header *); 1535 /* 1536 * Check if hardware VLAN insertion is off. 1537 * Additional check for LLC/SNAP frame? 1538 */ 1539 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1540 ip_off = sizeof(struct ether_vlan_header); 1541 m = m_pullup(m, ip_off); 1542 if (m == NULL) { 1543 *m_head = NULL; 1544 return (ENOBUFS); 1545 } 1546 } 1547 m = m_pullup(m, ip_off + sizeof(struct ip)); 1548 if (m == NULL) { 1549 *m_head = NULL; 1550 return (ENOBUFS); 1551 } 1552 ip = (struct ip *)(mtod(m, char *) + ip_off); 1553 poff = ip_off + (ip->ip_hl << 2); 1554 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1555 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1556 if (m == NULL) { 1557 *m_head = NULL; 1558 return (ENOBUFS); 1559 } 1560 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1561 m = m_pullup(m, poff + (tcp->th_off << 2)); 1562 if (m == NULL) { 1563 *m_head = NULL; 1564 return (ENOBUFS); 1565 } 1566 /* 1567 * L1 requires IP/TCP header size and offset as 1568 * well as TCP pseudo checksum which complicates 1569 * TSO configuration. I guess this comes from the 1570 * adherence to Microsoft NDIS Large Send 1571 * specification which requires insertion of 1572 * pseudo checksum by upper stack. The pseudo 1573 * checksum that NDIS refers to doesn't include 1574 * TCP payload length so age(4) should recompute 1575 * the pseudo checksum here. Hopefully this wouldn't 1576 * be much burden on modern CPUs. 1577 * Reset IP checksum and recompute TCP pseudo 1578 * checksum as NDIS specification said. 1579 */ 1580 ip = (struct ip *)(mtod(m, char *) + ip_off); 1581 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1582 ip->ip_sum = 0; 1583 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1584 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1585 } 1586 *m_head = m; 1587 } 1588 1589 si = prod = sc->age_cdata.age_tx_prod; 1590 txd = &sc->age_cdata.age_txdesc[prod]; 1591 txd_last = txd; 1592 map = txd->tx_dmamap; 1593 1594 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1595 *m_head, txsegs, &nsegs, 0); 1596 if (error == EFBIG) { 1597 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1598 if (m == NULL) { 1599 m_freem(*m_head); 1600 *m_head = NULL; 1601 return (ENOMEM); 1602 } 1603 *m_head = m; 1604 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1605 *m_head, txsegs, &nsegs, 0); 1606 if (error != 0) { 1607 m_freem(*m_head); 1608 *m_head = NULL; 1609 return (error); 1610 } 1611 } else if (error != 0) 1612 return (error); 1613 if (nsegs == 0) { 1614 m_freem(*m_head); 1615 *m_head = NULL; 1616 return (EIO); 1617 } 1618 1619 /* Check descriptor overrun. */ 1620 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1621 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1622 return (ENOBUFS); 1623 } 1624 1625 m = *m_head; 1626 /* Configure VLAN hardware tag insertion. */ 1627 if ((m->m_flags & M_VLANTAG) != 0) { 1628 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1629 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1630 cflags |= AGE_TD_INSERT_VLAN_TAG; 1631 } 1632 1633 desc = NULL; 1634 i = 0; 1635 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1636 /* Request TSO and set MSS. */ 1637 cflags |= AGE_TD_TSO_IPV4; 1638 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1639 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1640 AGE_TD_TSO_MSS_SHIFT); 1641 /* Set IP/TCP header size. */ 1642 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1643 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1644 /* 1645 * L1 requires the first buffer should only hold IP/TCP 1646 * header data. TCP payload should be handled in other 1647 * descriptors. 1648 */ 1649 hdrlen = poff + (tcp->th_off << 2); 1650 desc = &sc->age_rdata.age_tx_ring[prod]; 1651 desc->addr = htole64(txsegs[0].ds_addr); 1652 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1653 desc->flags = htole32(cflags); 1654 sc->age_cdata.age_tx_cnt++; 1655 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1656 if (m->m_len - hdrlen > 0) { 1657 /* Handle remaining payload of the 1st fragment. */ 1658 desc = &sc->age_rdata.age_tx_ring[prod]; 1659 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1660 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1661 vtag); 1662 desc->flags = htole32(cflags); 1663 sc->age_cdata.age_tx_cnt++; 1664 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1665 } 1666 /* Handle remaining fragments. */ 1667 i = 1; 1668 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1669 /* Configure Tx IP/TCP/UDP checksum offload. */ 1670 cflags |= AGE_TD_CSUM; 1671 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1672 cflags |= AGE_TD_TCPCSUM; 1673 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1674 cflags |= AGE_TD_UDPCSUM; 1675 /* Set checksum start offset. */ 1676 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1677 /* Set checksum insertion position of TCP/UDP. */ 1678 cflags |= ((poff + m->m_pkthdr.csum_data) << 1679 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1680 } 1681 for (; i < nsegs; i++) { 1682 desc = &sc->age_rdata.age_tx_ring[prod]; 1683 desc->addr = htole64(txsegs[i].ds_addr); 1684 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1685 desc->flags = htole32(cflags); 1686 sc->age_cdata.age_tx_cnt++; 1687 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1688 } 1689 /* Update producer index. */ 1690 sc->age_cdata.age_tx_prod = prod; 1691 1692 /* Set EOP on the last descriptor. */ 1693 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1694 desc = &sc->age_rdata.age_tx_ring[prod]; 1695 desc->flags |= htole32(AGE_TD_EOP); 1696 1697 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1698 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1699 desc = &sc->age_rdata.age_tx_ring[si]; 1700 desc->flags |= htole32(AGE_TD_TSO_HDR); 1701 } 1702 1703 /* Swap dmamap of the first and the last. */ 1704 txd = &sc->age_cdata.age_txdesc[prod]; 1705 map = txd_last->tx_dmamap; 1706 txd_last->tx_dmamap = txd->tx_dmamap; 1707 txd->tx_dmamap = map; 1708 txd->tx_m = m; 1709 1710 /* Sync descriptors. */ 1711 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1712 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1713 sc->age_cdata.age_tx_ring_map, 1714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1715 1716 return (0); 1717 } 1718 1719 static void 1720 age_start(if_t ifp) 1721 { 1722 struct age_softc *sc; 1723 1724 sc = if_getsoftc(ifp); 1725 AGE_LOCK(sc); 1726 age_start_locked(ifp); 1727 AGE_UNLOCK(sc); 1728 } 1729 1730 static void 1731 age_start_locked(if_t ifp) 1732 { 1733 struct age_softc *sc; 1734 struct mbuf *m_head; 1735 int enq; 1736 1737 sc = if_getsoftc(ifp); 1738 1739 AGE_LOCK_ASSERT(sc); 1740 1741 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1742 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1743 return; 1744 1745 for (enq = 0; !if_sendq_empty(ifp); ) { 1746 m_head = if_dequeue(ifp); 1747 if (m_head == NULL) 1748 break; 1749 /* 1750 * Pack the data into the transmit ring. If we 1751 * don't have room, set the OACTIVE flag and wait 1752 * for the NIC to drain the ring. 1753 */ 1754 if (age_encap(sc, &m_head)) { 1755 if (m_head == NULL) 1756 break; 1757 if_sendq_prepend(ifp, m_head); 1758 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1759 break; 1760 } 1761 1762 enq++; 1763 /* 1764 * If there's a BPF listener, bounce a copy of this frame 1765 * to him. 1766 */ 1767 ETHER_BPF_MTAP(ifp, m_head); 1768 } 1769 1770 if (enq > 0) { 1771 /* Update mbox. */ 1772 AGE_COMMIT_MBOX(sc); 1773 /* Set a timeout in case the chip goes out to lunch. */ 1774 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1775 } 1776 } 1777 1778 static void 1779 age_watchdog(struct age_softc *sc) 1780 { 1781 if_t ifp; 1782 1783 AGE_LOCK_ASSERT(sc); 1784 1785 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1786 return; 1787 1788 ifp = sc->age_ifp; 1789 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1790 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1791 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1792 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1793 age_init_locked(sc); 1794 return; 1795 } 1796 if (sc->age_cdata.age_tx_cnt == 0) { 1797 if_printf(sc->age_ifp, 1798 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1799 if (!if_sendq_empty(ifp)) 1800 age_start_locked(ifp); 1801 return; 1802 } 1803 if_printf(sc->age_ifp, "watchdog timeout\n"); 1804 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1805 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1806 age_init_locked(sc); 1807 if (!if_sendq_empty(ifp)) 1808 age_start_locked(ifp); 1809 } 1810 1811 static int 1812 age_ioctl(if_t ifp, u_long cmd, caddr_t data) 1813 { 1814 struct age_softc *sc; 1815 struct ifreq *ifr; 1816 struct mii_data *mii; 1817 uint32_t reg; 1818 int error, mask; 1819 1820 sc = if_getsoftc(ifp); 1821 ifr = (struct ifreq *)data; 1822 error = 0; 1823 switch (cmd) { 1824 case SIOCSIFMTU: 1825 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1826 error = EINVAL; 1827 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1828 AGE_LOCK(sc); 1829 if_setmtu(ifp, ifr->ifr_mtu); 1830 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1831 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1832 age_init_locked(sc); 1833 } 1834 AGE_UNLOCK(sc); 1835 } 1836 break; 1837 case SIOCSIFFLAGS: 1838 AGE_LOCK(sc); 1839 if ((if_getflags(ifp) & IFF_UP) != 0) { 1840 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1841 if (((if_getflags(ifp) ^ sc->age_if_flags) 1842 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1843 age_rxfilter(sc); 1844 } else { 1845 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1846 age_init_locked(sc); 1847 } 1848 } else { 1849 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1850 age_stop(sc); 1851 } 1852 sc->age_if_flags = if_getflags(ifp); 1853 AGE_UNLOCK(sc); 1854 break; 1855 case SIOCADDMULTI: 1856 case SIOCDELMULTI: 1857 AGE_LOCK(sc); 1858 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1859 age_rxfilter(sc); 1860 AGE_UNLOCK(sc); 1861 break; 1862 case SIOCSIFMEDIA: 1863 case SIOCGIFMEDIA: 1864 mii = device_get_softc(sc->age_miibus); 1865 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1866 break; 1867 case SIOCSIFCAP: 1868 AGE_LOCK(sc); 1869 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1870 if ((mask & IFCAP_TXCSUM) != 0 && 1871 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1872 if_togglecapenable(ifp, IFCAP_TXCSUM); 1873 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1874 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0); 1875 else 1876 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES); 1877 } 1878 if ((mask & IFCAP_RXCSUM) != 0 && 1879 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1880 if_togglecapenable(ifp, IFCAP_RXCSUM); 1881 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1882 reg &= ~MAC_CFG_RXCSUM_ENB; 1883 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1884 reg |= MAC_CFG_RXCSUM_ENB; 1885 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1886 } 1887 if ((mask & IFCAP_TSO4) != 0 && 1888 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1889 if_togglecapenable(ifp, IFCAP_TSO4); 1890 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 1891 if_sethwassistbits(ifp, CSUM_TSO, 0); 1892 else 1893 if_sethwassistbits(ifp, 0, CSUM_TSO); 1894 } 1895 1896 if ((mask & IFCAP_WOL_MCAST) != 0 && 1897 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 1898 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 1899 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1900 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1901 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1902 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1903 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 1904 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1905 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1906 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1907 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1908 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1909 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1910 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1911 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1912 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1913 age_rxvlan(sc); 1914 } 1915 AGE_UNLOCK(sc); 1916 VLAN_CAPABILITIES(ifp); 1917 break; 1918 default: 1919 error = ether_ioctl(ifp, cmd, data); 1920 break; 1921 } 1922 1923 return (error); 1924 } 1925 1926 static void 1927 age_mac_config(struct age_softc *sc) 1928 { 1929 struct mii_data *mii; 1930 uint32_t reg; 1931 1932 AGE_LOCK_ASSERT(sc); 1933 1934 mii = device_get_softc(sc->age_miibus); 1935 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1936 reg &= ~MAC_CFG_FULL_DUPLEX; 1937 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1938 reg &= ~MAC_CFG_SPEED_MASK; 1939 /* Reprogram MAC with resolved speed/duplex. */ 1940 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1941 case IFM_10_T: 1942 case IFM_100_TX: 1943 reg |= MAC_CFG_SPEED_10_100; 1944 break; 1945 case IFM_1000_T: 1946 reg |= MAC_CFG_SPEED_1000; 1947 break; 1948 } 1949 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1950 reg |= MAC_CFG_FULL_DUPLEX; 1951 #ifdef notyet 1952 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1953 reg |= MAC_CFG_TX_FC; 1954 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1955 reg |= MAC_CFG_RX_FC; 1956 #endif 1957 } 1958 1959 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1960 } 1961 1962 static void 1963 age_link_task(void *arg, int pending) 1964 { 1965 struct age_softc *sc; 1966 struct mii_data *mii; 1967 if_t ifp; 1968 uint32_t reg; 1969 1970 sc = (struct age_softc *)arg; 1971 1972 AGE_LOCK(sc); 1973 mii = device_get_softc(sc->age_miibus); 1974 ifp = sc->age_ifp; 1975 if (mii == NULL || ifp == NULL || 1976 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1977 AGE_UNLOCK(sc); 1978 return; 1979 } 1980 1981 sc->age_flags &= ~AGE_FLAG_LINK; 1982 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1983 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1984 case IFM_10_T: 1985 case IFM_100_TX: 1986 case IFM_1000_T: 1987 sc->age_flags |= AGE_FLAG_LINK; 1988 break; 1989 default: 1990 break; 1991 } 1992 } 1993 1994 /* Stop Rx/Tx MACs. */ 1995 age_stop_rxmac(sc); 1996 age_stop_txmac(sc); 1997 1998 /* Program MACs with resolved speed/duplex/flow-control. */ 1999 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2000 age_mac_config(sc); 2001 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2002 /* Restart DMA engine and Tx/Rx MAC. */ 2003 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2004 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2005 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2006 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2007 } 2008 2009 AGE_UNLOCK(sc); 2010 } 2011 2012 static void 2013 age_stats_update(struct age_softc *sc) 2014 { 2015 struct age_stats *stat; 2016 struct smb *smb; 2017 if_t ifp; 2018 2019 AGE_LOCK_ASSERT(sc); 2020 2021 stat = &sc->age_stat; 2022 2023 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2024 sc->age_cdata.age_smb_block_map, 2025 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2026 2027 smb = sc->age_rdata.age_smb_block; 2028 if (smb->updated == 0) 2029 return; 2030 2031 ifp = sc->age_ifp; 2032 /* Rx stats. */ 2033 stat->rx_frames += smb->rx_frames; 2034 stat->rx_bcast_frames += smb->rx_bcast_frames; 2035 stat->rx_mcast_frames += smb->rx_mcast_frames; 2036 stat->rx_pause_frames += smb->rx_pause_frames; 2037 stat->rx_control_frames += smb->rx_control_frames; 2038 stat->rx_crcerrs += smb->rx_crcerrs; 2039 stat->rx_lenerrs += smb->rx_lenerrs; 2040 stat->rx_bytes += smb->rx_bytes; 2041 stat->rx_runts += smb->rx_runts; 2042 stat->rx_fragments += smb->rx_fragments; 2043 stat->rx_pkts_64 += smb->rx_pkts_64; 2044 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2045 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2046 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2047 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2048 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2049 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2050 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2051 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2052 stat->rx_desc_oflows += smb->rx_desc_oflows; 2053 stat->rx_alignerrs += smb->rx_alignerrs; 2054 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2055 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2056 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2057 2058 /* Tx stats. */ 2059 stat->tx_frames += smb->tx_frames; 2060 stat->tx_bcast_frames += smb->tx_bcast_frames; 2061 stat->tx_mcast_frames += smb->tx_mcast_frames; 2062 stat->tx_pause_frames += smb->tx_pause_frames; 2063 stat->tx_excess_defer += smb->tx_excess_defer; 2064 stat->tx_control_frames += smb->tx_control_frames; 2065 stat->tx_deferred += smb->tx_deferred; 2066 stat->tx_bytes += smb->tx_bytes; 2067 stat->tx_pkts_64 += smb->tx_pkts_64; 2068 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2069 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2070 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2071 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2072 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2073 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2074 stat->tx_single_colls += smb->tx_single_colls; 2075 stat->tx_multi_colls += smb->tx_multi_colls; 2076 stat->tx_late_colls += smb->tx_late_colls; 2077 stat->tx_excess_colls += smb->tx_excess_colls; 2078 stat->tx_underrun += smb->tx_underrun; 2079 stat->tx_desc_underrun += smb->tx_desc_underrun; 2080 stat->tx_lenerrs += smb->tx_lenerrs; 2081 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2082 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2083 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2084 2085 /* Update counters in ifnet. */ 2086 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2087 2088 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2089 smb->tx_multi_colls + smb->tx_late_colls + 2090 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2091 2092 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2093 smb->tx_late_colls + smb->tx_underrun + 2094 smb->tx_pkts_truncated); 2095 2096 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2097 2098 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2099 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2100 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2101 smb->rx_alignerrs); 2102 2103 /* Update done, clear. */ 2104 smb->updated = 0; 2105 2106 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2107 sc->age_cdata.age_smb_block_map, 2108 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2109 } 2110 2111 static int 2112 age_intr(void *arg) 2113 { 2114 struct age_softc *sc; 2115 uint32_t status; 2116 2117 sc = (struct age_softc *)arg; 2118 2119 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2120 if (status == 0 || (status & AGE_INTRS) == 0) 2121 return (FILTER_STRAY); 2122 /* Disable interrupts. */ 2123 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2124 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2125 2126 return (FILTER_HANDLED); 2127 } 2128 2129 static void 2130 age_int_task(void *arg, int pending) 2131 { 2132 struct age_softc *sc; 2133 if_t ifp; 2134 struct cmb *cmb; 2135 uint32_t status; 2136 2137 sc = (struct age_softc *)arg; 2138 2139 AGE_LOCK(sc); 2140 2141 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2142 sc->age_cdata.age_cmb_block_map, 2143 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2144 cmb = sc->age_rdata.age_cmb_block; 2145 status = le32toh(cmb->intr_status); 2146 if (sc->age_morework != 0) 2147 status |= INTR_CMB_RX; 2148 if ((status & AGE_INTRS) == 0) 2149 goto done; 2150 2151 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2152 TPD_CONS_SHIFT; 2153 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2154 RRD_PROD_SHIFT; 2155 /* Let hardware know CMB was served. */ 2156 cmb->intr_status = 0; 2157 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2158 sc->age_cdata.age_cmb_block_map, 2159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2160 2161 ifp = sc->age_ifp; 2162 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2163 if ((status & INTR_CMB_RX) != 0) 2164 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2165 sc->age_process_limit); 2166 if ((status & INTR_CMB_TX) != 0) 2167 age_txintr(sc, sc->age_tpd_cons); 2168 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2169 if ((status & INTR_DMA_RD_TO_RST) != 0) 2170 device_printf(sc->age_dev, 2171 "DMA read error! -- resetting\n"); 2172 if ((status & INTR_DMA_WR_TO_RST) != 0) 2173 device_printf(sc->age_dev, 2174 "DMA write error! -- resetting\n"); 2175 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2176 age_init_locked(sc); 2177 } 2178 if (!if_sendq_empty(ifp)) 2179 age_start_locked(ifp); 2180 if ((status & INTR_SMB) != 0) 2181 age_stats_update(sc); 2182 } 2183 2184 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2185 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2186 sc->age_cdata.age_cmb_block_map, 2187 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2188 status = le32toh(cmb->intr_status); 2189 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2190 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2191 AGE_UNLOCK(sc); 2192 return; 2193 } 2194 2195 done: 2196 /* Re-enable interrupts. */ 2197 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2198 AGE_UNLOCK(sc); 2199 } 2200 2201 static void 2202 age_txintr(struct age_softc *sc, int tpd_cons) 2203 { 2204 if_t ifp; 2205 struct age_txdesc *txd; 2206 int cons, prog; 2207 2208 AGE_LOCK_ASSERT(sc); 2209 2210 ifp = sc->age_ifp; 2211 2212 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2213 sc->age_cdata.age_tx_ring_map, 2214 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2215 2216 /* 2217 * Go through our Tx list and free mbufs for those 2218 * frames which have been transmitted. 2219 */ 2220 cons = sc->age_cdata.age_tx_cons; 2221 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2222 if (sc->age_cdata.age_tx_cnt <= 0) 2223 break; 2224 prog++; 2225 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2226 sc->age_cdata.age_tx_cnt--; 2227 txd = &sc->age_cdata.age_txdesc[cons]; 2228 /* 2229 * Clear Tx descriptors, it's not required but would 2230 * help debugging in case of Tx issues. 2231 */ 2232 txd->tx_desc->addr = 0; 2233 txd->tx_desc->len = 0; 2234 txd->tx_desc->flags = 0; 2235 2236 if (txd->tx_m == NULL) 2237 continue; 2238 /* Reclaim transmitted mbufs. */ 2239 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2240 BUS_DMASYNC_POSTWRITE); 2241 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2242 m_freem(txd->tx_m); 2243 txd->tx_m = NULL; 2244 } 2245 2246 if (prog > 0) { 2247 sc->age_cdata.age_tx_cons = cons; 2248 2249 /* 2250 * Unarm watchdog timer only when there are no pending 2251 * Tx descriptors in queue. 2252 */ 2253 if (sc->age_cdata.age_tx_cnt == 0) 2254 sc->age_watchdog_timer = 0; 2255 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2256 sc->age_cdata.age_tx_ring_map, 2257 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2258 } 2259 } 2260 2261 #ifndef __NO_STRICT_ALIGNMENT 2262 static struct mbuf * 2263 age_fixup_rx(if_t ifp, struct mbuf *m) 2264 { 2265 struct mbuf *n; 2266 int i; 2267 uint16_t *src, *dst; 2268 2269 src = mtod(m, uint16_t *); 2270 dst = src - 3; 2271 2272 if (m->m_next == NULL) { 2273 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2274 *dst++ = *src++; 2275 m->m_data -= 6; 2276 return (m); 2277 } 2278 /* 2279 * Append a new mbuf to received mbuf chain and copy ethernet 2280 * header from the mbuf chain. This can save lots of CPU 2281 * cycles for jumbo frame. 2282 */ 2283 MGETHDR(n, M_NOWAIT, MT_DATA); 2284 if (n == NULL) { 2285 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2286 m_freem(m); 2287 return (NULL); 2288 } 2289 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2290 m->m_data += ETHER_HDR_LEN; 2291 m->m_len -= ETHER_HDR_LEN; 2292 n->m_len = ETHER_HDR_LEN; 2293 M_MOVE_PKTHDR(n, m); 2294 n->m_next = m; 2295 return (n); 2296 } 2297 #endif 2298 2299 /* Receive a frame. */ 2300 static void 2301 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2302 { 2303 struct age_rxdesc *rxd; 2304 if_t ifp; 2305 struct mbuf *mp, *m; 2306 uint32_t status, index, vtag; 2307 int count, nsegs; 2308 int rx_cons; 2309 2310 AGE_LOCK_ASSERT(sc); 2311 2312 ifp = sc->age_ifp; 2313 status = le32toh(rxrd->flags); 2314 index = le32toh(rxrd->index); 2315 rx_cons = AGE_RX_CONS(index); 2316 nsegs = AGE_RX_NSEGS(index); 2317 2318 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2319 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2320 /* 2321 * We want to pass the following frames to upper 2322 * layer regardless of error status of Rx return 2323 * ring. 2324 * 2325 * o IP/TCP/UDP checksum is bad. 2326 * o frame length and protocol specific length 2327 * does not match. 2328 */ 2329 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2330 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2331 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2332 return; 2333 } 2334 2335 for (count = 0; count < nsegs; count++, 2336 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2337 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2338 mp = rxd->rx_m; 2339 /* Add a new receive buffer to the ring. */ 2340 if (age_newbuf(sc, rxd) != 0) { 2341 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2342 /* Reuse Rx buffers. */ 2343 if (sc->age_cdata.age_rxhead != NULL) 2344 m_freem(sc->age_cdata.age_rxhead); 2345 break; 2346 } 2347 2348 /* 2349 * Assume we've received a full sized frame. 2350 * Actual size is fixed when we encounter the end of 2351 * multi-segmented frame. 2352 */ 2353 mp->m_len = AGE_RX_BUF_SIZE; 2354 2355 /* Chain received mbufs. */ 2356 if (sc->age_cdata.age_rxhead == NULL) { 2357 sc->age_cdata.age_rxhead = mp; 2358 sc->age_cdata.age_rxtail = mp; 2359 } else { 2360 mp->m_flags &= ~M_PKTHDR; 2361 sc->age_cdata.age_rxprev_tail = 2362 sc->age_cdata.age_rxtail; 2363 sc->age_cdata.age_rxtail->m_next = mp; 2364 sc->age_cdata.age_rxtail = mp; 2365 } 2366 2367 if (count == nsegs - 1) { 2368 /* Last desc. for this frame. */ 2369 m = sc->age_cdata.age_rxhead; 2370 m->m_flags |= M_PKTHDR; 2371 /* 2372 * It seems that L1 controller has no way 2373 * to tell hardware to strip CRC bytes. 2374 */ 2375 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2376 ETHER_CRC_LEN; 2377 if (nsegs > 1) { 2378 /* Set last mbuf size. */ 2379 mp->m_len = sc->age_cdata.age_rxlen - 2380 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2381 /* Remove the CRC bytes in chained mbufs. */ 2382 if (mp->m_len <= ETHER_CRC_LEN) { 2383 sc->age_cdata.age_rxtail = 2384 sc->age_cdata.age_rxprev_tail; 2385 sc->age_cdata.age_rxtail->m_len -= 2386 (ETHER_CRC_LEN - mp->m_len); 2387 sc->age_cdata.age_rxtail->m_next = NULL; 2388 m_freem(mp); 2389 } else { 2390 mp->m_len -= ETHER_CRC_LEN; 2391 } 2392 } else 2393 m->m_len = m->m_pkthdr.len; 2394 m->m_pkthdr.rcvif = ifp; 2395 /* 2396 * Set checksum information. 2397 * It seems that L1 controller can compute partial 2398 * checksum. The partial checksum value can be used 2399 * to accelerate checksum computation for fragmented 2400 * TCP/UDP packets. Upper network stack already 2401 * takes advantage of the partial checksum value in 2402 * IP reassembly stage. But I'm not sure the 2403 * correctness of the partial hardware checksum 2404 * assistance due to lack of data sheet. If it is 2405 * proven to work on L1 I'll enable it. 2406 */ 2407 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2408 (status & AGE_RRD_IPV4) != 0) { 2409 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2410 m->m_pkthdr.csum_flags |= 2411 CSUM_IP_CHECKED | CSUM_IP_VALID; 2412 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2413 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2414 m->m_pkthdr.csum_flags |= 2415 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2416 m->m_pkthdr.csum_data = 0xffff; 2417 } 2418 /* 2419 * Don't mark bad checksum for TCP/UDP frames 2420 * as fragmented frames may always have set 2421 * bad checksummed bit of descriptor status. 2422 */ 2423 } 2424 2425 /* Check for VLAN tagged frames. */ 2426 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2427 (status & AGE_RRD_VLAN) != 0) { 2428 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2429 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2430 m->m_flags |= M_VLANTAG; 2431 } 2432 #ifndef __NO_STRICT_ALIGNMENT 2433 m = age_fixup_rx(ifp, m); 2434 if (m != NULL) 2435 #endif 2436 { 2437 /* Pass it on. */ 2438 AGE_UNLOCK(sc); 2439 if_input(ifp, m); 2440 AGE_LOCK(sc); 2441 } 2442 } 2443 } 2444 2445 /* Reset mbuf chains. */ 2446 AGE_RXCHAIN_RESET(sc); 2447 } 2448 2449 static int 2450 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2451 { 2452 struct rx_rdesc *rxrd; 2453 int rr_cons, nsegs, pktlen, prog; 2454 2455 AGE_LOCK_ASSERT(sc); 2456 2457 rr_cons = sc->age_cdata.age_rr_cons; 2458 if (rr_cons == rr_prod) 2459 return (0); 2460 2461 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2462 sc->age_cdata.age_rr_ring_map, 2463 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2464 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2465 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2466 2467 for (prog = 0; rr_cons != rr_prod; prog++) { 2468 if (count-- <= 0) 2469 break; 2470 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2471 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2472 if (nsegs == 0) 2473 break; 2474 /* 2475 * Check number of segments against received bytes. 2476 * Non-matching value would indicate that hardware 2477 * is still trying to update Rx return descriptors. 2478 * I'm not sure whether this check is really needed. 2479 */ 2480 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2481 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2482 break; 2483 2484 /* Received a frame. */ 2485 age_rxeof(sc, rxrd); 2486 /* Clear return ring. */ 2487 rxrd->index = 0; 2488 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2489 sc->age_cdata.age_rx_cons += nsegs; 2490 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2491 } 2492 2493 if (prog > 0) { 2494 /* Update the consumer index. */ 2495 sc->age_cdata.age_rr_cons = rr_cons; 2496 2497 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2498 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2499 /* Sync descriptors. */ 2500 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2501 sc->age_cdata.age_rr_ring_map, 2502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2503 2504 /* Notify hardware availability of new Rx buffers. */ 2505 AGE_COMMIT_MBOX(sc); 2506 } 2507 2508 return (count > 0 ? 0 : EAGAIN); 2509 } 2510 2511 static void 2512 age_tick(void *arg) 2513 { 2514 struct age_softc *sc; 2515 struct mii_data *mii; 2516 2517 sc = (struct age_softc *)arg; 2518 2519 AGE_LOCK_ASSERT(sc); 2520 2521 mii = device_get_softc(sc->age_miibus); 2522 mii_tick(mii); 2523 age_watchdog(sc); 2524 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2525 } 2526 2527 static void 2528 age_reset(struct age_softc *sc) 2529 { 2530 uint32_t reg; 2531 int i; 2532 2533 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2534 CSR_READ_4(sc, AGE_MASTER_CFG); 2535 DELAY(1000); 2536 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2537 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2538 break; 2539 DELAY(10); 2540 } 2541 2542 if (i == 0) 2543 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2544 /* Initialize PCIe module. From Linux. */ 2545 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2546 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2547 } 2548 2549 static void 2550 age_init(void *xsc) 2551 { 2552 struct age_softc *sc; 2553 2554 sc = (struct age_softc *)xsc; 2555 AGE_LOCK(sc); 2556 age_init_locked(sc); 2557 AGE_UNLOCK(sc); 2558 } 2559 2560 static void 2561 age_init_locked(struct age_softc *sc) 2562 { 2563 if_t ifp; 2564 struct mii_data *mii; 2565 uint8_t eaddr[ETHER_ADDR_LEN]; 2566 bus_addr_t paddr; 2567 uint32_t reg, fsize; 2568 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2569 int error; 2570 2571 AGE_LOCK_ASSERT(sc); 2572 2573 ifp = sc->age_ifp; 2574 mii = device_get_softc(sc->age_miibus); 2575 2576 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2577 return; 2578 2579 /* 2580 * Cancel any pending I/O. 2581 */ 2582 age_stop(sc); 2583 2584 /* 2585 * Reset the chip to a known state. 2586 */ 2587 age_reset(sc); 2588 2589 /* Initialize descriptors. */ 2590 error = age_init_rx_ring(sc); 2591 if (error != 0) { 2592 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2593 age_stop(sc); 2594 return; 2595 } 2596 age_init_rr_ring(sc); 2597 age_init_tx_ring(sc); 2598 age_init_cmb_block(sc); 2599 age_init_smb_block(sc); 2600 2601 /* Reprogram the station address. */ 2602 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2603 CSR_WRITE_4(sc, AGE_PAR0, 2604 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2605 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2606 2607 /* Set descriptor base addresses. */ 2608 paddr = sc->age_rdata.age_tx_ring_paddr; 2609 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2610 paddr = sc->age_rdata.age_rx_ring_paddr; 2611 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2612 paddr = sc->age_rdata.age_rr_ring_paddr; 2613 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2614 paddr = sc->age_rdata.age_tx_ring_paddr; 2615 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2616 paddr = sc->age_rdata.age_cmb_block_paddr; 2617 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2618 paddr = sc->age_rdata.age_smb_block_paddr; 2619 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2620 /* Set Rx/Rx return descriptor counter. */ 2621 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2622 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2623 DESC_RRD_CNT_MASK) | 2624 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2625 /* Set Tx descriptor counter. */ 2626 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2627 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2628 2629 /* Tell hardware that we're ready to load descriptors. */ 2630 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2631 2632 /* 2633 * Initialize mailbox register. 2634 * Updated producer/consumer index information is exchanged 2635 * through this mailbox register. However Tx producer and 2636 * Rx return consumer/Rx producer are all shared such that 2637 * it's hard to separate code path between Tx and Rx without 2638 * locking. If L1 hardware have a separate mail box register 2639 * for Tx and Rx consumer/producer management we could have 2640 * independent Tx/Rx handler which in turn Rx handler could have 2641 * been run without any locking. 2642 */ 2643 AGE_COMMIT_MBOX(sc); 2644 2645 /* Configure IPG/IFG parameters. */ 2646 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2647 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2648 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2649 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2650 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2651 2652 /* Set parameters for half-duplex media. */ 2653 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2654 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2655 HDPX_CFG_LCOL_MASK) | 2656 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2657 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2658 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2659 HDPX_CFG_ABEBT_MASK) | 2660 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2661 HDPX_CFG_JAMIPG_MASK)); 2662 2663 /* Configure interrupt moderation timer. */ 2664 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2665 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2666 reg &= ~MASTER_MTIMER_ENB; 2667 if (AGE_USECS(sc->age_int_mod) == 0) 2668 reg &= ~MASTER_ITIMER_ENB; 2669 else 2670 reg |= MASTER_ITIMER_ENB; 2671 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2672 if (bootverbose) 2673 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2674 sc->age_int_mod); 2675 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2676 2677 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2678 if (if_getmtu(ifp) < ETHERMTU) 2679 sc->age_max_frame_size = ETHERMTU; 2680 else 2681 sc->age_max_frame_size = if_getmtu(ifp); 2682 sc->age_max_frame_size += ETHER_HDR_LEN + 2683 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2684 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2685 /* Configure jumbo frame. */ 2686 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2687 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2688 (((fsize / sizeof(uint64_t)) << 2689 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2690 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2691 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2692 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2693 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2694 2695 /* Configure flow-control parameters. From Linux. */ 2696 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2697 /* 2698 * Magic workaround for old-L1. 2699 * Don't know which hw revision requires this magic. 2700 */ 2701 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2702 /* 2703 * Another magic workaround for flow-control mode 2704 * change. From Linux. 2705 */ 2706 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2707 } 2708 /* 2709 * TODO 2710 * Should understand pause parameter relationships between FIFO 2711 * size and number of Rx descriptors and Rx return descriptors. 2712 * 2713 * Magic parameters came from Linux. 2714 */ 2715 switch (sc->age_chip_rev) { 2716 case 0x8001: 2717 case 0x9001: 2718 case 0x9002: 2719 case 0x9003: 2720 rxf_hi = AGE_RX_RING_CNT / 16; 2721 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2722 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2723 rrd_lo = AGE_RR_RING_CNT / 16; 2724 break; 2725 default: 2726 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2727 rxf_lo = reg / 16; 2728 if (rxf_lo < 192) 2729 rxf_lo = 192; 2730 rxf_hi = (reg * 7) / 8; 2731 if (rxf_hi < rxf_lo) 2732 rxf_hi = rxf_lo + 16; 2733 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2734 rrd_lo = reg / 8; 2735 rrd_hi = (reg * 7) / 8; 2736 if (rrd_lo < 2) 2737 rrd_lo = 2; 2738 if (rrd_hi < rrd_lo) 2739 rrd_hi = rrd_lo + 3; 2740 break; 2741 } 2742 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2743 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2744 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2745 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2746 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2747 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2748 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2749 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2750 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2751 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2752 2753 /* Configure RxQ. */ 2754 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2755 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2756 RXQ_CFG_RD_BURST_MASK) | 2757 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2758 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2759 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2760 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2761 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2762 2763 /* Configure TxQ. */ 2764 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2765 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2766 TXQ_CFG_TPD_BURST_MASK) | 2767 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2768 TXQ_CFG_TX_FIFO_BURST_MASK) | 2769 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2770 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2771 TXQ_CFG_ENB); 2772 2773 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2774 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2775 TX_JUMBO_TPD_TH_MASK) | 2776 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2777 TX_JUMBO_TPD_IPG_MASK)); 2778 /* Configure DMA parameters. */ 2779 CSR_WRITE_4(sc, AGE_DMA_CFG, 2780 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2781 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2782 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2783 2784 /* Configure CMB DMA write threshold. */ 2785 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2786 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2787 CMB_WR_THRESH_RRD_MASK) | 2788 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2789 CMB_WR_THRESH_TPD_MASK)); 2790 2791 /* Set CMB/SMB timer and enable them. */ 2792 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2793 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2794 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2795 /* Request SMB updates for every seconds. */ 2796 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2797 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2798 2799 /* 2800 * Disable all WOL bits as WOL can interfere normal Rx 2801 * operation. 2802 */ 2803 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2804 2805 /* 2806 * Configure Tx/Rx MACs. 2807 * - Auto-padding for short frames. 2808 * - Enable CRC generation. 2809 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2810 * of MAC is followed after link establishment. 2811 */ 2812 CSR_WRITE_4(sc, AGE_MAC_CFG, 2813 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2814 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2815 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2816 MAC_CFG_PREAMBLE_MASK)); 2817 /* Set up the receive filter. */ 2818 age_rxfilter(sc); 2819 age_rxvlan(sc); 2820 2821 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2822 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2823 reg |= MAC_CFG_RXCSUM_ENB; 2824 2825 /* Ack all pending interrupts and clear it. */ 2826 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2827 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2828 2829 /* Finally enable Tx/Rx MAC. */ 2830 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2831 2832 sc->age_flags &= ~AGE_FLAG_LINK; 2833 /* Switch to the current media. */ 2834 mii_mediachg(mii); 2835 2836 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2837 2838 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2839 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2840 } 2841 2842 static void 2843 age_stop(struct age_softc *sc) 2844 { 2845 if_t ifp; 2846 struct age_txdesc *txd; 2847 struct age_rxdesc *rxd; 2848 uint32_t reg; 2849 int i; 2850 2851 AGE_LOCK_ASSERT(sc); 2852 /* 2853 * Mark the interface down and cancel the watchdog timer. 2854 */ 2855 ifp = sc->age_ifp; 2856 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2857 sc->age_flags &= ~AGE_FLAG_LINK; 2858 callout_stop(&sc->age_tick_ch); 2859 sc->age_watchdog_timer = 0; 2860 2861 /* 2862 * Disable interrupts. 2863 */ 2864 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2865 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2866 /* Stop CMB/SMB updates. */ 2867 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2868 /* Stop Rx/Tx MAC. */ 2869 age_stop_rxmac(sc); 2870 age_stop_txmac(sc); 2871 /* Stop DMA. */ 2872 CSR_WRITE_4(sc, AGE_DMA_CFG, 2873 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2874 /* Stop TxQ/RxQ. */ 2875 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2876 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2877 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2878 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2879 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2880 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2881 break; 2882 DELAY(10); 2883 } 2884 if (i == 0) 2885 device_printf(sc->age_dev, 2886 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2887 2888 /* Reclaim Rx buffers that have been processed. */ 2889 if (sc->age_cdata.age_rxhead != NULL) 2890 m_freem(sc->age_cdata.age_rxhead); 2891 AGE_RXCHAIN_RESET(sc); 2892 /* 2893 * Free RX and TX mbufs still in the queues. 2894 */ 2895 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2896 rxd = &sc->age_cdata.age_rxdesc[i]; 2897 if (rxd->rx_m != NULL) { 2898 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2899 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2900 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2901 rxd->rx_dmamap); 2902 m_freem(rxd->rx_m); 2903 rxd->rx_m = NULL; 2904 } 2905 } 2906 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2907 txd = &sc->age_cdata.age_txdesc[i]; 2908 if (txd->tx_m != NULL) { 2909 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2910 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2911 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2912 txd->tx_dmamap); 2913 m_freem(txd->tx_m); 2914 txd->tx_m = NULL; 2915 } 2916 } 2917 } 2918 2919 static void 2920 age_stop_txmac(struct age_softc *sc) 2921 { 2922 uint32_t reg; 2923 int i; 2924 2925 AGE_LOCK_ASSERT(sc); 2926 2927 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2928 if ((reg & MAC_CFG_TX_ENB) != 0) { 2929 reg &= ~MAC_CFG_TX_ENB; 2930 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2931 } 2932 /* Stop Tx DMA engine. */ 2933 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2934 if ((reg & DMA_CFG_RD_ENB) != 0) { 2935 reg &= ~DMA_CFG_RD_ENB; 2936 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2937 } 2938 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2939 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2940 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2941 break; 2942 DELAY(10); 2943 } 2944 if (i == 0) 2945 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2946 } 2947 2948 static void 2949 age_stop_rxmac(struct age_softc *sc) 2950 { 2951 uint32_t reg; 2952 int i; 2953 2954 AGE_LOCK_ASSERT(sc); 2955 2956 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2957 if ((reg & MAC_CFG_RX_ENB) != 0) { 2958 reg &= ~MAC_CFG_RX_ENB; 2959 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2960 } 2961 /* Stop Rx DMA engine. */ 2962 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2963 if ((reg & DMA_CFG_WR_ENB) != 0) { 2964 reg &= ~DMA_CFG_WR_ENB; 2965 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2966 } 2967 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2968 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2969 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2970 break; 2971 DELAY(10); 2972 } 2973 if (i == 0) 2974 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2975 } 2976 2977 static void 2978 age_init_tx_ring(struct age_softc *sc) 2979 { 2980 struct age_ring_data *rd; 2981 struct age_txdesc *txd; 2982 int i; 2983 2984 AGE_LOCK_ASSERT(sc); 2985 2986 sc->age_cdata.age_tx_prod = 0; 2987 sc->age_cdata.age_tx_cons = 0; 2988 sc->age_cdata.age_tx_cnt = 0; 2989 2990 rd = &sc->age_rdata; 2991 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2992 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2993 txd = &sc->age_cdata.age_txdesc[i]; 2994 txd->tx_desc = &rd->age_tx_ring[i]; 2995 txd->tx_m = NULL; 2996 } 2997 2998 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2999 sc->age_cdata.age_tx_ring_map, 3000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3001 } 3002 3003 static int 3004 age_init_rx_ring(struct age_softc *sc) 3005 { 3006 struct age_ring_data *rd; 3007 struct age_rxdesc *rxd; 3008 int i; 3009 3010 AGE_LOCK_ASSERT(sc); 3011 3012 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3013 sc->age_morework = 0; 3014 rd = &sc->age_rdata; 3015 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3016 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3017 rxd = &sc->age_cdata.age_rxdesc[i]; 3018 rxd->rx_m = NULL; 3019 rxd->rx_desc = &rd->age_rx_ring[i]; 3020 if (age_newbuf(sc, rxd) != 0) 3021 return (ENOBUFS); 3022 } 3023 3024 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3025 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3026 3027 return (0); 3028 } 3029 3030 static void 3031 age_init_rr_ring(struct age_softc *sc) 3032 { 3033 struct age_ring_data *rd; 3034 3035 AGE_LOCK_ASSERT(sc); 3036 3037 sc->age_cdata.age_rr_cons = 0; 3038 AGE_RXCHAIN_RESET(sc); 3039 3040 rd = &sc->age_rdata; 3041 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3042 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3043 sc->age_cdata.age_rr_ring_map, 3044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3045 } 3046 3047 static void 3048 age_init_cmb_block(struct age_softc *sc) 3049 { 3050 struct age_ring_data *rd; 3051 3052 AGE_LOCK_ASSERT(sc); 3053 3054 rd = &sc->age_rdata; 3055 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3056 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3057 sc->age_cdata.age_cmb_block_map, 3058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3059 } 3060 3061 static void 3062 age_init_smb_block(struct age_softc *sc) 3063 { 3064 struct age_ring_data *rd; 3065 3066 AGE_LOCK_ASSERT(sc); 3067 3068 rd = &sc->age_rdata; 3069 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3070 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3071 sc->age_cdata.age_smb_block_map, 3072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3073 } 3074 3075 static int 3076 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3077 { 3078 struct rx_desc *desc; 3079 struct mbuf *m; 3080 bus_dma_segment_t segs[1]; 3081 bus_dmamap_t map; 3082 int nsegs; 3083 3084 AGE_LOCK_ASSERT(sc); 3085 3086 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3087 if (m == NULL) 3088 return (ENOBUFS); 3089 m->m_len = m->m_pkthdr.len = MCLBYTES; 3090 #ifndef __NO_STRICT_ALIGNMENT 3091 m_adj(m, AGE_RX_BUF_ALIGN); 3092 #endif 3093 3094 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3095 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3096 m_freem(m); 3097 return (ENOBUFS); 3098 } 3099 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3100 3101 if (rxd->rx_m != NULL) { 3102 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3103 BUS_DMASYNC_POSTREAD); 3104 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3105 } 3106 map = rxd->rx_dmamap; 3107 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3108 sc->age_cdata.age_rx_sparemap = map; 3109 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3110 BUS_DMASYNC_PREREAD); 3111 rxd->rx_m = m; 3112 3113 desc = rxd->rx_desc; 3114 desc->addr = htole64(segs[0].ds_addr); 3115 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3116 AGE_RD_LEN_SHIFT); 3117 return (0); 3118 } 3119 3120 static void 3121 age_rxvlan(struct age_softc *sc) 3122 { 3123 if_t ifp; 3124 uint32_t reg; 3125 3126 AGE_LOCK_ASSERT(sc); 3127 3128 ifp = sc->age_ifp; 3129 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3130 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3131 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3132 reg |= MAC_CFG_VLAN_TAG_STRIP; 3133 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3134 } 3135 3136 static u_int 3137 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3138 { 3139 uint32_t *mchash = arg; 3140 uint32_t crc; 3141 3142 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3143 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3144 3145 return (1); 3146 } 3147 3148 static void 3149 age_rxfilter(struct age_softc *sc) 3150 { 3151 if_t ifp; 3152 uint32_t mchash[2]; 3153 uint32_t rxcfg; 3154 3155 AGE_LOCK_ASSERT(sc); 3156 3157 ifp = sc->age_ifp; 3158 3159 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3160 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3161 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3162 rxcfg |= MAC_CFG_BCAST; 3163 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3164 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3165 rxcfg |= MAC_CFG_PROMISC; 3166 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3167 rxcfg |= MAC_CFG_ALLMULTI; 3168 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3169 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3170 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3171 return; 3172 } 3173 3174 /* Program new filter. */ 3175 bzero(mchash, sizeof(mchash)); 3176 if_foreach_llmaddr(ifp, age_hash_maddr, mchash); 3177 3178 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3179 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3180 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3181 } 3182 3183 static int 3184 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3185 { 3186 struct age_softc *sc; 3187 struct age_stats *stats; 3188 int error, result; 3189 3190 result = -1; 3191 error = sysctl_handle_int(oidp, &result, 0, req); 3192 3193 if (error != 0 || req->newptr == NULL) 3194 return (error); 3195 3196 if (result != 1) 3197 return (error); 3198 3199 sc = (struct age_softc *)arg1; 3200 stats = &sc->age_stat; 3201 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3202 printf("Transmit good frames : %ju\n", 3203 (uintmax_t)stats->tx_frames); 3204 printf("Transmit good broadcast frames : %ju\n", 3205 (uintmax_t)stats->tx_bcast_frames); 3206 printf("Transmit good multicast frames : %ju\n", 3207 (uintmax_t)stats->tx_mcast_frames); 3208 printf("Transmit pause control frames : %u\n", 3209 stats->tx_pause_frames); 3210 printf("Transmit control frames : %u\n", 3211 stats->tx_control_frames); 3212 printf("Transmit frames with excessive deferrals : %u\n", 3213 stats->tx_excess_defer); 3214 printf("Transmit deferrals : %u\n", 3215 stats->tx_deferred); 3216 printf("Transmit good octets : %ju\n", 3217 (uintmax_t)stats->tx_bytes); 3218 printf("Transmit good broadcast octets : %ju\n", 3219 (uintmax_t)stats->tx_bcast_bytes); 3220 printf("Transmit good multicast octets : %ju\n", 3221 (uintmax_t)stats->tx_mcast_bytes); 3222 printf("Transmit frames 64 bytes : %ju\n", 3223 (uintmax_t)stats->tx_pkts_64); 3224 printf("Transmit frames 65 to 127 bytes : %ju\n", 3225 (uintmax_t)stats->tx_pkts_65_127); 3226 printf("Transmit frames 128 to 255 bytes : %ju\n", 3227 (uintmax_t)stats->tx_pkts_128_255); 3228 printf("Transmit frames 256 to 511 bytes : %ju\n", 3229 (uintmax_t)stats->tx_pkts_256_511); 3230 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3231 (uintmax_t)stats->tx_pkts_512_1023); 3232 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3233 (uintmax_t)stats->tx_pkts_1024_1518); 3234 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3235 (uintmax_t)stats->tx_pkts_1519_max); 3236 printf("Transmit single collisions : %u\n", 3237 stats->tx_single_colls); 3238 printf("Transmit multiple collisions : %u\n", 3239 stats->tx_multi_colls); 3240 printf("Transmit late collisions : %u\n", 3241 stats->tx_late_colls); 3242 printf("Transmit abort due to excessive collisions : %u\n", 3243 stats->tx_excess_colls); 3244 printf("Transmit underruns due to FIFO underruns : %u\n", 3245 stats->tx_underrun); 3246 printf("Transmit descriptor write-back errors : %u\n", 3247 stats->tx_desc_underrun); 3248 printf("Transmit frames with length mismatched frame size : %u\n", 3249 stats->tx_lenerrs); 3250 printf("Transmit frames with truncated due to MTU size : %u\n", 3251 stats->tx_lenerrs); 3252 3253 printf("Receive good frames : %ju\n", 3254 (uintmax_t)stats->rx_frames); 3255 printf("Receive good broadcast frames : %ju\n", 3256 (uintmax_t)stats->rx_bcast_frames); 3257 printf("Receive good multicast frames : %ju\n", 3258 (uintmax_t)stats->rx_mcast_frames); 3259 printf("Receive pause control frames : %u\n", 3260 stats->rx_pause_frames); 3261 printf("Receive control frames : %u\n", 3262 stats->rx_control_frames); 3263 printf("Receive CRC errors : %u\n", 3264 stats->rx_crcerrs); 3265 printf("Receive frames with length errors : %u\n", 3266 stats->rx_lenerrs); 3267 printf("Receive good octets : %ju\n", 3268 (uintmax_t)stats->rx_bytes); 3269 printf("Receive good broadcast octets : %ju\n", 3270 (uintmax_t)stats->rx_bcast_bytes); 3271 printf("Receive good multicast octets : %ju\n", 3272 (uintmax_t)stats->rx_mcast_bytes); 3273 printf("Receive frames too short : %u\n", 3274 stats->rx_runts); 3275 printf("Receive fragmented frames : %ju\n", 3276 (uintmax_t)stats->rx_fragments); 3277 printf("Receive frames 64 bytes : %ju\n", 3278 (uintmax_t)stats->rx_pkts_64); 3279 printf("Receive frames 65 to 127 bytes : %ju\n", 3280 (uintmax_t)stats->rx_pkts_65_127); 3281 printf("Receive frames 128 to 255 bytes : %ju\n", 3282 (uintmax_t)stats->rx_pkts_128_255); 3283 printf("Receive frames 256 to 511 bytes : %ju\n", 3284 (uintmax_t)stats->rx_pkts_256_511); 3285 printf("Receive frames 512 to 1024 bytes : %ju\n", 3286 (uintmax_t)stats->rx_pkts_512_1023); 3287 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3288 (uintmax_t)stats->rx_pkts_1024_1518); 3289 printf("Receive frames 1519 to MTU bytes : %ju\n", 3290 (uintmax_t)stats->rx_pkts_1519_max); 3291 printf("Receive frames too long : %ju\n", 3292 (uint64_t)stats->rx_pkts_truncated); 3293 printf("Receive frames with FIFO overflow : %u\n", 3294 stats->rx_fifo_oflows); 3295 printf("Receive frames with return descriptor overflow : %u\n", 3296 stats->rx_desc_oflows); 3297 printf("Receive frames with alignment errors : %u\n", 3298 stats->rx_alignerrs); 3299 printf("Receive frames dropped due to address filtering : %ju\n", 3300 (uint64_t)stats->rx_pkts_filtered); 3301 3302 return (error); 3303 } 3304 3305 static int 3306 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3307 { 3308 int error, value; 3309 3310 if (arg1 == NULL) 3311 return (EINVAL); 3312 value = *(int *)arg1; 3313 error = sysctl_handle_int(oidp, &value, 0, req); 3314 if (error || req->newptr == NULL) 3315 return (error); 3316 if (value < low || value > high) 3317 return (EINVAL); 3318 *(int *)arg1 = value; 3319 3320 return (0); 3321 } 3322 3323 static int 3324 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3325 { 3326 return (sysctl_int_range(oidp, arg1, arg2, req, 3327 AGE_PROC_MIN, AGE_PROC_MAX)); 3328 } 3329 3330 static int 3331 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3332 { 3333 3334 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3335 AGE_IM_TIMER_MAX)); 3336 } 3337