1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/mbuf.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/bus.h> 72 #include <machine/in_cksum.h> 73 74 #include <dev/age/if_agereg.h> 75 #include <dev/age/if_agevar.h> 76 77 /* "device miibus" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(age, pci, 1, 1, 1); 83 MODULE_DEPEND(age, ether, 1, 1, 1); 84 MODULE_DEPEND(age, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct age_dev { 96 uint16_t age_vendorid; 97 uint16_t age_deviceid; 98 const char *age_name; 99 } age_devs[] = { 100 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102 }; 103 104 static int age_miibus_readreg(device_t, int, int); 105 static int age_miibus_writereg(device_t, int, int, int); 106 static void age_miibus_statchg(device_t); 107 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 108 static int age_mediachange(struct ifnet *); 109 static int age_probe(device_t); 110 static void age_get_macaddr(struct age_softc *); 111 static void age_phy_reset(struct age_softc *); 112 static int age_attach(device_t); 113 static int age_detach(device_t); 114 static void age_sysctl_node(struct age_softc *); 115 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 116 static int age_check_boundary(struct age_softc *); 117 static int age_dma_alloc(struct age_softc *); 118 static void age_dma_free(struct age_softc *); 119 static int age_shutdown(device_t); 120 static void age_setwol(struct age_softc *); 121 static int age_suspend(device_t); 122 static int age_resume(device_t); 123 static int age_encap(struct age_softc *, struct mbuf **); 124 static void age_start(struct ifnet *); 125 static void age_start_locked(struct ifnet *); 126 static void age_watchdog(struct age_softc *); 127 static int age_ioctl(struct ifnet *, u_long, caddr_t); 128 static void age_mac_config(struct age_softc *); 129 static void age_link_task(void *, int); 130 static void age_stats_update(struct age_softc *); 131 static int age_intr(void *); 132 static void age_int_task(void *, int); 133 static void age_txintr(struct age_softc *, int); 134 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 135 static int age_rxintr(struct age_softc *, int, int); 136 static void age_tick(void *); 137 static void age_reset(struct age_softc *); 138 static void age_init(void *); 139 static void age_init_locked(struct age_softc *); 140 static void age_stop(struct age_softc *); 141 static void age_stop_txmac(struct age_softc *); 142 static void age_stop_rxmac(struct age_softc *); 143 static void age_init_tx_ring(struct age_softc *); 144 static int age_init_rx_ring(struct age_softc *); 145 static void age_init_rr_ring(struct age_softc *); 146 static void age_init_cmb_block(struct age_softc *); 147 static void age_init_smb_block(struct age_softc *); 148 #ifndef __NO_STRICT_ALIGNMENT 149 static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *); 150 #endif 151 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 152 static void age_rxvlan(struct age_softc *); 153 static void age_rxfilter(struct age_softc *); 154 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 155 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 156 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 157 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 158 159 160 static device_method_t age_methods[] = { 161 /* Device interface. */ 162 DEVMETHOD(device_probe, age_probe), 163 DEVMETHOD(device_attach, age_attach), 164 DEVMETHOD(device_detach, age_detach), 165 DEVMETHOD(device_shutdown, age_shutdown), 166 DEVMETHOD(device_suspend, age_suspend), 167 DEVMETHOD(device_resume, age_resume), 168 169 /* MII interface. */ 170 DEVMETHOD(miibus_readreg, age_miibus_readreg), 171 DEVMETHOD(miibus_writereg, age_miibus_writereg), 172 DEVMETHOD(miibus_statchg, age_miibus_statchg), 173 174 { NULL, NULL } 175 }; 176 177 static driver_t age_driver = { 178 "age", 179 age_methods, 180 sizeof(struct age_softc) 181 }; 182 183 static devclass_t age_devclass; 184 185 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 186 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 187 nitems(age_devs)); 188 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 189 190 static struct resource_spec age_res_spec_mem[] = { 191 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec age_irq_spec_legacy[] = { 196 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 197 { -1, 0, 0 } 198 }; 199 200 static struct resource_spec age_irq_spec_msi[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203 }; 204 205 static struct resource_spec age_irq_spec_msix[] = { 206 { SYS_RES_IRQ, 1, RF_ACTIVE }, 207 { -1, 0, 0 } 208 }; 209 210 /* 211 * Read a PHY register on the MII of the L1. 212 */ 213 static int 214 age_miibus_readreg(device_t dev, int phy, int reg) 215 { 216 struct age_softc *sc; 217 uint32_t v; 218 int i; 219 220 sc = device_get_softc(dev); 221 222 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 223 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 224 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 225 DELAY(1); 226 v = CSR_READ_4(sc, AGE_MDIO); 227 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 228 break; 229 } 230 231 if (i == 0) { 232 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 233 return (0); 234 } 235 236 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 237 } 238 239 /* 240 * Write a PHY register on the MII of the L1. 241 */ 242 static int 243 age_miibus_writereg(device_t dev, int phy, int reg, int val) 244 { 245 struct age_softc *sc; 246 uint32_t v; 247 int i; 248 249 sc = device_get_softc(dev); 250 251 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 252 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 253 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 254 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 255 DELAY(1); 256 v = CSR_READ_4(sc, AGE_MDIO); 257 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 258 break; 259 } 260 261 if (i == 0) 262 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 263 264 return (0); 265 } 266 267 /* 268 * Callback from MII layer when media changes. 269 */ 270 static void 271 age_miibus_statchg(device_t dev) 272 { 273 struct age_softc *sc; 274 275 sc = device_get_softc(dev); 276 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 277 } 278 279 /* 280 * Get the current interface media status. 281 */ 282 static void 283 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 284 { 285 struct age_softc *sc; 286 struct mii_data *mii; 287 288 sc = ifp->if_softc; 289 AGE_LOCK(sc); 290 mii = device_get_softc(sc->age_miibus); 291 292 mii_pollstat(mii); 293 ifmr->ifm_status = mii->mii_media_status; 294 ifmr->ifm_active = mii->mii_media_active; 295 AGE_UNLOCK(sc); 296 } 297 298 /* 299 * Set hardware to newly-selected media. 300 */ 301 static int 302 age_mediachange(struct ifnet *ifp) 303 { 304 struct age_softc *sc; 305 struct mii_data *mii; 306 struct mii_softc *miisc; 307 int error; 308 309 sc = ifp->if_softc; 310 AGE_LOCK(sc); 311 mii = device_get_softc(sc->age_miibus); 312 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 313 PHY_RESET(miisc); 314 error = mii_mediachg(mii); 315 AGE_UNLOCK(sc); 316 317 return (error); 318 } 319 320 static int 321 age_probe(device_t dev) 322 { 323 struct age_dev *sp; 324 int i; 325 uint16_t vendor, devid; 326 327 vendor = pci_get_vendor(dev); 328 devid = pci_get_device(dev); 329 sp = age_devs; 330 for (i = 0; i < nitems(age_devs); i++, sp++) { 331 if (vendor == sp->age_vendorid && 332 devid == sp->age_deviceid) { 333 device_set_desc(dev, sp->age_name); 334 return (BUS_PROBE_DEFAULT); 335 } 336 } 337 338 return (ENXIO); 339 } 340 341 static void 342 age_get_macaddr(struct age_softc *sc) 343 { 344 uint32_t ea[2], reg; 345 int i, vpdc; 346 347 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 348 if ((reg & SPI_VPD_ENB) != 0) { 349 /* Get VPD stored in TWSI EEPROM. */ 350 reg &= ~SPI_VPD_ENB; 351 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 352 } 353 354 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 355 /* 356 * PCI VPD capability found, let TWSI reload EEPROM. 357 * This will set ethernet address of controller. 358 */ 359 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 360 TWSI_CTRL_SW_LD_START); 361 for (i = 100; i > 0; i--) { 362 DELAY(1000); 363 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 364 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 365 break; 366 } 367 if (i == 0) 368 device_printf(sc->age_dev, 369 "reloading EEPROM timeout!\n"); 370 } else { 371 if (bootverbose) 372 device_printf(sc->age_dev, 373 "PCI VPD capability not found!\n"); 374 } 375 376 ea[0] = CSR_READ_4(sc, AGE_PAR0); 377 ea[1] = CSR_READ_4(sc, AGE_PAR1); 378 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 379 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 380 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 381 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 382 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 383 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 384 } 385 386 static void 387 age_phy_reset(struct age_softc *sc) 388 { 389 uint16_t reg, pn; 390 int i, linkup; 391 392 /* Reset PHY. */ 393 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 394 DELAY(2000); 395 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 396 DELAY(2000); 397 398 #define ATPHY_DBG_ADDR 0x1D 399 #define ATPHY_DBG_DATA 0x1E 400 #define ATPHY_CDTC 0x16 401 #define PHY_CDTC_ENB 0x0001 402 #define PHY_CDTC_POFF 8 403 #define ATPHY_CDTS 0x1C 404 #define PHY_CDTS_STAT_OK 0x0000 405 #define PHY_CDTS_STAT_SHORT 0x0100 406 #define PHY_CDTS_STAT_OPEN 0x0200 407 #define PHY_CDTS_STAT_INVAL 0x0300 408 #define PHY_CDTS_STAT_MASK 0x0300 409 410 /* Check power saving mode. Magic from Linux. */ 411 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 412 for (linkup = 0, pn = 0; pn < 4; pn++) { 413 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 414 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 415 for (i = 200; i > 0; i--) { 416 DELAY(1000); 417 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 418 ATPHY_CDTC); 419 if ((reg & PHY_CDTC_ENB) == 0) 420 break; 421 } 422 DELAY(1000); 423 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 424 ATPHY_CDTS); 425 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 426 linkup++; 427 break; 428 } 429 } 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 431 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 432 if (linkup == 0) { 433 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 434 ATPHY_DBG_ADDR, 0); 435 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_DATA, 0x124E); 437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 438 ATPHY_DBG_ADDR, 1); 439 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 440 ATPHY_DBG_DATA); 441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_DATA, reg | 0x03); 443 /* XXX */ 444 DELAY(1500 * 1000); 445 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 446 ATPHY_DBG_ADDR, 0); 447 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 448 ATPHY_DBG_DATA, 0x024E); 449 } 450 451 #undef ATPHY_DBG_ADDR 452 #undef ATPHY_DBG_DATA 453 #undef ATPHY_CDTC 454 #undef PHY_CDTC_ENB 455 #undef PHY_CDTC_POFF 456 #undef ATPHY_CDTS 457 #undef PHY_CDTS_STAT_OK 458 #undef PHY_CDTS_STAT_SHORT 459 #undef PHY_CDTS_STAT_OPEN 460 #undef PHY_CDTS_STAT_INVAL 461 #undef PHY_CDTS_STAT_MASK 462 } 463 464 static int 465 age_attach(device_t dev) 466 { 467 struct age_softc *sc; 468 struct ifnet *ifp; 469 uint16_t burst; 470 int error, i, msic, msixc, pmc; 471 472 error = 0; 473 sc = device_get_softc(dev); 474 sc->age_dev = dev; 475 476 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 477 MTX_DEF); 478 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 479 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 480 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 481 482 /* Map the device. */ 483 pci_enable_busmaster(dev); 484 sc->age_res_spec = age_res_spec_mem; 485 sc->age_irq_spec = age_irq_spec_legacy; 486 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 487 if (error != 0) { 488 device_printf(dev, "cannot allocate memory resources.\n"); 489 goto fail; 490 } 491 492 /* Set PHY address. */ 493 sc->age_phyaddr = AGE_PHY_ADDR; 494 495 /* Reset PHY. */ 496 age_phy_reset(sc); 497 498 /* Reset the ethernet controller. */ 499 age_reset(sc); 500 501 /* Get PCI and chip id/revision. */ 502 sc->age_rev = pci_get_revid(dev); 503 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 504 MASTER_CHIP_REV_SHIFT; 505 if (bootverbose) { 506 device_printf(dev, "PCI device revision : 0x%04x\n", 507 sc->age_rev); 508 device_printf(dev, "Chip id/revision : 0x%04x\n", 509 sc->age_chip_rev); 510 } 511 512 /* 513 * XXX 514 * Unintialized hardware returns an invalid chip id/revision 515 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 516 * unplugged cable results in putting hardware into automatic 517 * power down mode which in turn returns invalld chip revision. 518 */ 519 if (sc->age_chip_rev == 0xFFFF) { 520 device_printf(dev,"invalid chip revision : 0x%04x -- " 521 "not initialized?\n", sc->age_chip_rev); 522 error = ENXIO; 523 goto fail; 524 } 525 526 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 527 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 528 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 529 530 /* Allocate IRQ resources. */ 531 msixc = pci_msix_count(dev); 532 msic = pci_msi_count(dev); 533 if (bootverbose) { 534 device_printf(dev, "MSIX count : %d\n", msixc); 535 device_printf(dev, "MSI count : %d\n", msic); 536 } 537 538 /* Prefer MSIX over MSI. */ 539 if (msix_disable == 0 || msi_disable == 0) { 540 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 541 pci_alloc_msix(dev, &msixc) == 0) { 542 if (msic == AGE_MSIX_MESSAGES) { 543 device_printf(dev, "Using %d MSIX messages.\n", 544 msixc); 545 sc->age_flags |= AGE_FLAG_MSIX; 546 sc->age_irq_spec = age_irq_spec_msix; 547 } else 548 pci_release_msi(dev); 549 } 550 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 551 msic == AGE_MSI_MESSAGES && 552 pci_alloc_msi(dev, &msic) == 0) { 553 if (msic == AGE_MSI_MESSAGES) { 554 device_printf(dev, "Using %d MSI messages.\n", 555 msic); 556 sc->age_flags |= AGE_FLAG_MSI; 557 sc->age_irq_spec = age_irq_spec_msi; 558 } else 559 pci_release_msi(dev); 560 } 561 } 562 563 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 564 if (error != 0) { 565 device_printf(dev, "cannot allocate IRQ resources.\n"); 566 goto fail; 567 } 568 569 570 /* Get DMA parameters from PCIe device control register. */ 571 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 572 sc->age_flags |= AGE_FLAG_PCIE; 573 burst = pci_read_config(dev, i + 0x08, 2); 574 /* Max read request size. */ 575 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 576 DMA_CFG_RD_BURST_SHIFT; 577 /* Max payload size. */ 578 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 579 DMA_CFG_WR_BURST_SHIFT; 580 if (bootverbose) { 581 device_printf(dev, "Read request size : %d bytes.\n", 582 128 << ((burst >> 12) & 0x07)); 583 device_printf(dev, "TLP payload size : %d bytes.\n", 584 128 << ((burst >> 5) & 0x07)); 585 } 586 } else { 587 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 588 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 589 } 590 591 /* Create device sysctl node. */ 592 age_sysctl_node(sc); 593 594 if ((error = age_dma_alloc(sc)) != 0) 595 goto fail; 596 597 /* Load station address. */ 598 age_get_macaddr(sc); 599 600 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 601 if (ifp == NULL) { 602 device_printf(dev, "cannot allocate ifnet structure.\n"); 603 error = ENXIO; 604 goto fail; 605 } 606 607 ifp->if_softc = sc; 608 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 610 ifp->if_ioctl = age_ioctl; 611 ifp->if_start = age_start; 612 ifp->if_init = age_init; 613 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 614 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 615 IFQ_SET_READY(&ifp->if_snd); 616 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 617 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 618 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 619 sc->age_flags |= AGE_FLAG_PMCAP; 620 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 621 } 622 ifp->if_capenable = ifp->if_capabilities; 623 624 /* Set up MII bus. */ 625 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 626 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 627 0); 628 if (error != 0) { 629 device_printf(dev, "attaching PHYs failed\n"); 630 goto fail; 631 } 632 633 ether_ifattach(ifp, sc->age_eaddr); 634 635 /* VLAN capability setup. */ 636 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 637 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 638 ifp->if_capenable = ifp->if_capabilities; 639 640 /* Tell the upper layer(s) we support long frames. */ 641 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 642 643 /* Create local taskq. */ 644 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 645 taskqueue_thread_enqueue, &sc->age_tq); 646 if (sc->age_tq == NULL) { 647 device_printf(dev, "could not create taskqueue.\n"); 648 ether_ifdetach(ifp); 649 error = ENXIO; 650 goto fail; 651 } 652 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 653 device_get_nameunit(sc->age_dev)); 654 655 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 656 msic = AGE_MSIX_MESSAGES; 657 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 658 msic = AGE_MSI_MESSAGES; 659 else 660 msic = 1; 661 for (i = 0; i < msic; i++) { 662 error = bus_setup_intr(dev, sc->age_irq[i], 663 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 664 &sc->age_intrhand[i]); 665 if (error != 0) 666 break; 667 } 668 if (error != 0) { 669 device_printf(dev, "could not set up interrupt handler.\n"); 670 taskqueue_free(sc->age_tq); 671 sc->age_tq = NULL; 672 ether_ifdetach(ifp); 673 goto fail; 674 } 675 676 fail: 677 if (error != 0) 678 age_detach(dev); 679 680 return (error); 681 } 682 683 static int 684 age_detach(device_t dev) 685 { 686 struct age_softc *sc; 687 struct ifnet *ifp; 688 int i, msic; 689 690 sc = device_get_softc(dev); 691 692 ifp = sc->age_ifp; 693 if (device_is_attached(dev)) { 694 AGE_LOCK(sc); 695 sc->age_flags |= AGE_FLAG_DETACH; 696 age_stop(sc); 697 AGE_UNLOCK(sc); 698 callout_drain(&sc->age_tick_ch); 699 taskqueue_drain(sc->age_tq, &sc->age_int_task); 700 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 701 ether_ifdetach(ifp); 702 } 703 704 if (sc->age_tq != NULL) { 705 taskqueue_drain(sc->age_tq, &sc->age_int_task); 706 taskqueue_free(sc->age_tq); 707 sc->age_tq = NULL; 708 } 709 710 if (sc->age_miibus != NULL) { 711 device_delete_child(dev, sc->age_miibus); 712 sc->age_miibus = NULL; 713 } 714 bus_generic_detach(dev); 715 age_dma_free(sc); 716 717 if (ifp != NULL) { 718 if_free(ifp); 719 sc->age_ifp = NULL; 720 } 721 722 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 723 msic = AGE_MSIX_MESSAGES; 724 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 725 msic = AGE_MSI_MESSAGES; 726 else 727 msic = 1; 728 for (i = 0; i < msic; i++) { 729 if (sc->age_intrhand[i] != NULL) { 730 bus_teardown_intr(dev, sc->age_irq[i], 731 sc->age_intrhand[i]); 732 sc->age_intrhand[i] = NULL; 733 } 734 } 735 736 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 737 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 738 pci_release_msi(dev); 739 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 740 mtx_destroy(&sc->age_mtx); 741 742 return (0); 743 } 744 745 static void 746 age_sysctl_node(struct age_softc *sc) 747 { 748 int error; 749 750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 752 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 753 sc, 0, sysctl_age_stats, "I", "Statistics"); 754 755 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 756 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 757 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 758 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", 759 "age interrupt moderation"); 760 761 /* Pull in device tunables. */ 762 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 763 error = resource_int_value(device_get_name(sc->age_dev), 764 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 765 if (error == 0) { 766 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 767 sc->age_int_mod > AGE_IM_TIMER_MAX) { 768 device_printf(sc->age_dev, 769 "int_mod value out of range; using default: %d\n", 770 AGE_IM_TIMER_DEFAULT); 771 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 772 } 773 } 774 775 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 776 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 777 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 778 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", 779 "max number of Rx events to process"); 780 781 /* Pull in device tunables. */ 782 sc->age_process_limit = AGE_PROC_DEFAULT; 783 error = resource_int_value(device_get_name(sc->age_dev), 784 device_get_unit(sc->age_dev), "process_limit", 785 &sc->age_process_limit); 786 if (error == 0) { 787 if (sc->age_process_limit < AGE_PROC_MIN || 788 sc->age_process_limit > AGE_PROC_MAX) { 789 device_printf(sc->age_dev, 790 "process_limit value out of range; " 791 "using default: %d\n", AGE_PROC_DEFAULT); 792 sc->age_process_limit = AGE_PROC_DEFAULT; 793 } 794 } 795 } 796 797 struct age_dmamap_arg { 798 bus_addr_t age_busaddr; 799 }; 800 801 static void 802 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 803 { 804 struct age_dmamap_arg *ctx; 805 806 if (error != 0) 807 return; 808 809 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 810 811 ctx = (struct age_dmamap_arg *)arg; 812 ctx->age_busaddr = segs[0].ds_addr; 813 } 814 815 /* 816 * Attansic L1 controller have single register to specify high 817 * address part of DMA blocks. So all descriptor structures and 818 * DMA memory blocks should have the same high address of given 819 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 820 */ 821 static int 822 age_check_boundary(struct age_softc *sc) 823 { 824 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 825 bus_addr_t cmb_block_end, smb_block_end; 826 827 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 828 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 829 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 830 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 831 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 832 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 833 834 if ((AGE_ADDR_HI(tx_ring_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 836 (AGE_ADDR_HI(rx_ring_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 838 (AGE_ADDR_HI(rr_ring_end) != 839 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 840 (AGE_ADDR_HI(cmb_block_end) != 841 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 842 (AGE_ADDR_HI(smb_block_end) != 843 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 844 return (EFBIG); 845 846 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 847 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 848 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 849 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 850 return (EFBIG); 851 852 return (0); 853 } 854 855 static int 856 age_dma_alloc(struct age_softc *sc) 857 { 858 struct age_txdesc *txd; 859 struct age_rxdesc *rxd; 860 bus_addr_t lowaddr; 861 struct age_dmamap_arg ctx; 862 int error, i; 863 864 lowaddr = BUS_SPACE_MAXADDR; 865 866 again: 867 /* Create parent ring/DMA block tag. */ 868 error = bus_dma_tag_create( 869 bus_get_dma_tag(sc->age_dev), /* parent */ 870 1, 0, /* alignment, boundary */ 871 lowaddr, /* lowaddr */ 872 BUS_SPACE_MAXADDR, /* highaddr */ 873 NULL, NULL, /* filter, filterarg */ 874 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 875 0, /* nsegments */ 876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 877 0, /* flags */ 878 NULL, NULL, /* lockfunc, lockarg */ 879 &sc->age_cdata.age_parent_tag); 880 if (error != 0) { 881 device_printf(sc->age_dev, 882 "could not create parent DMA tag.\n"); 883 goto fail; 884 } 885 886 /* Create tag for Tx ring. */ 887 error = bus_dma_tag_create( 888 sc->age_cdata.age_parent_tag, /* parent */ 889 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 890 BUS_SPACE_MAXADDR, /* lowaddr */ 891 BUS_SPACE_MAXADDR, /* highaddr */ 892 NULL, NULL, /* filter, filterarg */ 893 AGE_TX_RING_SZ, /* maxsize */ 894 1, /* nsegments */ 895 AGE_TX_RING_SZ, /* maxsegsize */ 896 0, /* flags */ 897 NULL, NULL, /* lockfunc, lockarg */ 898 &sc->age_cdata.age_tx_ring_tag); 899 if (error != 0) { 900 device_printf(sc->age_dev, 901 "could not create Tx ring DMA tag.\n"); 902 goto fail; 903 } 904 905 /* Create tag for Rx ring. */ 906 error = bus_dma_tag_create( 907 sc->age_cdata.age_parent_tag, /* parent */ 908 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 909 BUS_SPACE_MAXADDR, /* lowaddr */ 910 BUS_SPACE_MAXADDR, /* highaddr */ 911 NULL, NULL, /* filter, filterarg */ 912 AGE_RX_RING_SZ, /* maxsize */ 913 1, /* nsegments */ 914 AGE_RX_RING_SZ, /* maxsegsize */ 915 0, /* flags */ 916 NULL, NULL, /* lockfunc, lockarg */ 917 &sc->age_cdata.age_rx_ring_tag); 918 if (error != 0) { 919 device_printf(sc->age_dev, 920 "could not create Rx ring DMA tag.\n"); 921 goto fail; 922 } 923 924 /* Create tag for Rx return ring. */ 925 error = bus_dma_tag_create( 926 sc->age_cdata.age_parent_tag, /* parent */ 927 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 928 BUS_SPACE_MAXADDR, /* lowaddr */ 929 BUS_SPACE_MAXADDR, /* highaddr */ 930 NULL, NULL, /* filter, filterarg */ 931 AGE_RR_RING_SZ, /* maxsize */ 932 1, /* nsegments */ 933 AGE_RR_RING_SZ, /* maxsegsize */ 934 0, /* flags */ 935 NULL, NULL, /* lockfunc, lockarg */ 936 &sc->age_cdata.age_rr_ring_tag); 937 if (error != 0) { 938 device_printf(sc->age_dev, 939 "could not create Rx return ring DMA tag.\n"); 940 goto fail; 941 } 942 943 /* Create tag for coalesing message block. */ 944 error = bus_dma_tag_create( 945 sc->age_cdata.age_parent_tag, /* parent */ 946 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 947 BUS_SPACE_MAXADDR, /* lowaddr */ 948 BUS_SPACE_MAXADDR, /* highaddr */ 949 NULL, NULL, /* filter, filterarg */ 950 AGE_CMB_BLOCK_SZ, /* maxsize */ 951 1, /* nsegments */ 952 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 953 0, /* flags */ 954 NULL, NULL, /* lockfunc, lockarg */ 955 &sc->age_cdata.age_cmb_block_tag); 956 if (error != 0) { 957 device_printf(sc->age_dev, 958 "could not create CMB DMA tag.\n"); 959 goto fail; 960 } 961 962 /* Create tag for statistics message block. */ 963 error = bus_dma_tag_create( 964 sc->age_cdata.age_parent_tag, /* parent */ 965 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 966 BUS_SPACE_MAXADDR, /* lowaddr */ 967 BUS_SPACE_MAXADDR, /* highaddr */ 968 NULL, NULL, /* filter, filterarg */ 969 AGE_SMB_BLOCK_SZ, /* maxsize */ 970 1, /* nsegments */ 971 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 972 0, /* flags */ 973 NULL, NULL, /* lockfunc, lockarg */ 974 &sc->age_cdata.age_smb_block_tag); 975 if (error != 0) { 976 device_printf(sc->age_dev, 977 "could not create SMB DMA tag.\n"); 978 goto fail; 979 } 980 981 /* Allocate DMA'able memory and load the DMA map. */ 982 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 983 (void **)&sc->age_rdata.age_tx_ring, 984 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 985 &sc->age_cdata.age_tx_ring_map); 986 if (error != 0) { 987 device_printf(sc->age_dev, 988 "could not allocate DMA'able memory for Tx ring.\n"); 989 goto fail; 990 } 991 ctx.age_busaddr = 0; 992 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 993 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 994 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 995 if (error != 0 || ctx.age_busaddr == 0) { 996 device_printf(sc->age_dev, 997 "could not load DMA'able memory for Tx ring.\n"); 998 goto fail; 999 } 1000 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 1001 /* Rx ring */ 1002 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1003 (void **)&sc->age_rdata.age_rx_ring, 1004 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1005 &sc->age_cdata.age_rx_ring_map); 1006 if (error != 0) { 1007 device_printf(sc->age_dev, 1008 "could not allocate DMA'able memory for Rx ring.\n"); 1009 goto fail; 1010 } 1011 ctx.age_busaddr = 0; 1012 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1013 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1014 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1015 if (error != 0 || ctx.age_busaddr == 0) { 1016 device_printf(sc->age_dev, 1017 "could not load DMA'able memory for Rx ring.\n"); 1018 goto fail; 1019 } 1020 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1021 /* Rx return ring */ 1022 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1023 (void **)&sc->age_rdata.age_rr_ring, 1024 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1025 &sc->age_cdata.age_rr_ring_map); 1026 if (error != 0) { 1027 device_printf(sc->age_dev, 1028 "could not allocate DMA'able memory for Rx return ring.\n"); 1029 goto fail; 1030 } 1031 ctx.age_busaddr = 0; 1032 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1033 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1034 AGE_RR_RING_SZ, age_dmamap_cb, 1035 &ctx, 0); 1036 if (error != 0 || ctx.age_busaddr == 0) { 1037 device_printf(sc->age_dev, 1038 "could not load DMA'able memory for Rx return ring.\n"); 1039 goto fail; 1040 } 1041 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1042 /* CMB block */ 1043 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1044 (void **)&sc->age_rdata.age_cmb_block, 1045 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1046 &sc->age_cdata.age_cmb_block_map); 1047 if (error != 0) { 1048 device_printf(sc->age_dev, 1049 "could not allocate DMA'able memory for CMB block.\n"); 1050 goto fail; 1051 } 1052 ctx.age_busaddr = 0; 1053 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1054 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1055 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1056 if (error != 0 || ctx.age_busaddr == 0) { 1057 device_printf(sc->age_dev, 1058 "could not load DMA'able memory for CMB block.\n"); 1059 goto fail; 1060 } 1061 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1062 /* SMB block */ 1063 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1064 (void **)&sc->age_rdata.age_smb_block, 1065 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1066 &sc->age_cdata.age_smb_block_map); 1067 if (error != 0) { 1068 device_printf(sc->age_dev, 1069 "could not allocate DMA'able memory for SMB block.\n"); 1070 goto fail; 1071 } 1072 ctx.age_busaddr = 0; 1073 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1074 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1075 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1076 if (error != 0 || ctx.age_busaddr == 0) { 1077 device_printf(sc->age_dev, 1078 "could not load DMA'able memory for SMB block.\n"); 1079 goto fail; 1080 } 1081 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1082 1083 /* 1084 * All ring buffer and DMA blocks should have the same 1085 * high address part of 64bit DMA address space. 1086 */ 1087 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1088 (error = age_check_boundary(sc)) != 0) { 1089 device_printf(sc->age_dev, "4GB boundary crossed, " 1090 "switching to 32bit DMA addressing mode.\n"); 1091 age_dma_free(sc); 1092 /* Limit DMA address space to 32bit and try again. */ 1093 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1094 goto again; 1095 } 1096 1097 /* 1098 * Create Tx/Rx buffer parent tag. 1099 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1100 * so it needs separate parent DMA tag. 1101 * XXX 1102 * It seems enabling 64bit DMA causes data corruption. Limit 1103 * DMA address space to 32bit. 1104 */ 1105 error = bus_dma_tag_create( 1106 bus_get_dma_tag(sc->age_dev), /* parent */ 1107 1, 0, /* alignment, boundary */ 1108 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, NULL, /* filter, filterarg */ 1111 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1112 0, /* nsegments */ 1113 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1114 0, /* flags */ 1115 NULL, NULL, /* lockfunc, lockarg */ 1116 &sc->age_cdata.age_buffer_tag); 1117 if (error != 0) { 1118 device_printf(sc->age_dev, 1119 "could not create parent buffer DMA tag.\n"); 1120 goto fail; 1121 } 1122 1123 /* Create tag for Tx buffers. */ 1124 error = bus_dma_tag_create( 1125 sc->age_cdata.age_buffer_tag, /* parent */ 1126 1, 0, /* alignment, boundary */ 1127 BUS_SPACE_MAXADDR, /* lowaddr */ 1128 BUS_SPACE_MAXADDR, /* highaddr */ 1129 NULL, NULL, /* filter, filterarg */ 1130 AGE_TSO_MAXSIZE, /* maxsize */ 1131 AGE_MAXTXSEGS, /* nsegments */ 1132 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1133 0, /* flags */ 1134 NULL, NULL, /* lockfunc, lockarg */ 1135 &sc->age_cdata.age_tx_tag); 1136 if (error != 0) { 1137 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1138 goto fail; 1139 } 1140 1141 /* Create tag for Rx buffers. */ 1142 error = bus_dma_tag_create( 1143 sc->age_cdata.age_buffer_tag, /* parent */ 1144 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1145 BUS_SPACE_MAXADDR, /* lowaddr */ 1146 BUS_SPACE_MAXADDR, /* highaddr */ 1147 NULL, NULL, /* filter, filterarg */ 1148 MCLBYTES, /* maxsize */ 1149 1, /* nsegments */ 1150 MCLBYTES, /* maxsegsize */ 1151 0, /* flags */ 1152 NULL, NULL, /* lockfunc, lockarg */ 1153 &sc->age_cdata.age_rx_tag); 1154 if (error != 0) { 1155 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1156 goto fail; 1157 } 1158 1159 /* Create DMA maps for Tx buffers. */ 1160 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1161 txd = &sc->age_cdata.age_txdesc[i]; 1162 txd->tx_m = NULL; 1163 txd->tx_dmamap = NULL; 1164 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1165 &txd->tx_dmamap); 1166 if (error != 0) { 1167 device_printf(sc->age_dev, 1168 "could not create Tx dmamap.\n"); 1169 goto fail; 1170 } 1171 } 1172 /* Create DMA maps for Rx buffers. */ 1173 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1174 &sc->age_cdata.age_rx_sparemap)) != 0) { 1175 device_printf(sc->age_dev, 1176 "could not create spare Rx dmamap.\n"); 1177 goto fail; 1178 } 1179 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1180 rxd = &sc->age_cdata.age_rxdesc[i]; 1181 rxd->rx_m = NULL; 1182 rxd->rx_dmamap = NULL; 1183 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1184 &rxd->rx_dmamap); 1185 if (error != 0) { 1186 device_printf(sc->age_dev, 1187 "could not create Rx dmamap.\n"); 1188 goto fail; 1189 } 1190 } 1191 1192 fail: 1193 return (error); 1194 } 1195 1196 static void 1197 age_dma_free(struct age_softc *sc) 1198 { 1199 struct age_txdesc *txd; 1200 struct age_rxdesc *rxd; 1201 int i; 1202 1203 /* Tx buffers */ 1204 if (sc->age_cdata.age_tx_tag != NULL) { 1205 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1206 txd = &sc->age_cdata.age_txdesc[i]; 1207 if (txd->tx_dmamap != NULL) { 1208 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1209 txd->tx_dmamap); 1210 txd->tx_dmamap = NULL; 1211 } 1212 } 1213 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1214 sc->age_cdata.age_tx_tag = NULL; 1215 } 1216 /* Rx buffers */ 1217 if (sc->age_cdata.age_rx_tag != NULL) { 1218 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1219 rxd = &sc->age_cdata.age_rxdesc[i]; 1220 if (rxd->rx_dmamap != NULL) { 1221 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1222 rxd->rx_dmamap); 1223 rxd->rx_dmamap = NULL; 1224 } 1225 } 1226 if (sc->age_cdata.age_rx_sparemap != NULL) { 1227 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1228 sc->age_cdata.age_rx_sparemap); 1229 sc->age_cdata.age_rx_sparemap = NULL; 1230 } 1231 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1232 sc->age_cdata.age_rx_tag = NULL; 1233 } 1234 /* Tx ring. */ 1235 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1236 if (sc->age_rdata.age_tx_ring_paddr != 0) 1237 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1238 sc->age_cdata.age_tx_ring_map); 1239 if (sc->age_rdata.age_tx_ring != NULL) 1240 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1241 sc->age_rdata.age_tx_ring, 1242 sc->age_cdata.age_tx_ring_map); 1243 sc->age_rdata.age_tx_ring_paddr = 0; 1244 sc->age_rdata.age_tx_ring = NULL; 1245 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1246 sc->age_cdata.age_tx_ring_tag = NULL; 1247 } 1248 /* Rx ring. */ 1249 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1250 if (sc->age_rdata.age_rx_ring_paddr != 0) 1251 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1252 sc->age_cdata.age_rx_ring_map); 1253 if (sc->age_rdata.age_rx_ring != NULL) 1254 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1255 sc->age_rdata.age_rx_ring, 1256 sc->age_cdata.age_rx_ring_map); 1257 sc->age_rdata.age_rx_ring_paddr = 0; 1258 sc->age_rdata.age_rx_ring = NULL; 1259 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1260 sc->age_cdata.age_rx_ring_tag = NULL; 1261 } 1262 /* Rx return ring. */ 1263 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1264 if (sc->age_rdata.age_rr_ring_paddr != 0) 1265 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1266 sc->age_cdata.age_rr_ring_map); 1267 if (sc->age_rdata.age_rr_ring != NULL) 1268 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1269 sc->age_rdata.age_rr_ring, 1270 sc->age_cdata.age_rr_ring_map); 1271 sc->age_rdata.age_rr_ring_paddr = 0; 1272 sc->age_rdata.age_rr_ring = NULL; 1273 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1274 sc->age_cdata.age_rr_ring_tag = NULL; 1275 } 1276 /* CMB block */ 1277 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1278 if (sc->age_rdata.age_cmb_block_paddr != 0) 1279 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1280 sc->age_cdata.age_cmb_block_map); 1281 if (sc->age_rdata.age_cmb_block != NULL) 1282 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1283 sc->age_rdata.age_cmb_block, 1284 sc->age_cdata.age_cmb_block_map); 1285 sc->age_rdata.age_cmb_block_paddr = 0; 1286 sc->age_rdata.age_cmb_block = NULL; 1287 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1288 sc->age_cdata.age_cmb_block_tag = NULL; 1289 } 1290 /* SMB block */ 1291 if (sc->age_cdata.age_smb_block_tag != NULL) { 1292 if (sc->age_rdata.age_smb_block_paddr != 0) 1293 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1294 sc->age_cdata.age_smb_block_map); 1295 if (sc->age_rdata.age_smb_block != NULL) 1296 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1297 sc->age_rdata.age_smb_block, 1298 sc->age_cdata.age_smb_block_map); 1299 sc->age_rdata.age_smb_block_paddr = 0; 1300 sc->age_rdata.age_smb_block = NULL; 1301 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1302 sc->age_cdata.age_smb_block_tag = NULL; 1303 } 1304 1305 if (sc->age_cdata.age_buffer_tag != NULL) { 1306 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1307 sc->age_cdata.age_buffer_tag = NULL; 1308 } 1309 if (sc->age_cdata.age_parent_tag != NULL) { 1310 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1311 sc->age_cdata.age_parent_tag = NULL; 1312 } 1313 } 1314 1315 /* 1316 * Make sure the interface is stopped at reboot time. 1317 */ 1318 static int 1319 age_shutdown(device_t dev) 1320 { 1321 1322 return (age_suspend(dev)); 1323 } 1324 1325 static void 1326 age_setwol(struct age_softc *sc) 1327 { 1328 struct ifnet *ifp; 1329 struct mii_data *mii; 1330 uint32_t reg, pmcs; 1331 uint16_t pmstat; 1332 int aneg, i, pmc; 1333 1334 AGE_LOCK_ASSERT(sc); 1335 1336 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1337 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1338 /* 1339 * No PME capability, PHY power down. 1340 * XXX 1341 * Due to an unknown reason powering down PHY resulted 1342 * in unexpected results such as inaccessbility of 1343 * hardware of freshly rebooted system. Disable 1344 * powering down PHY until I got more information for 1345 * Attansic/Atheros PHY hardwares. 1346 */ 1347 #ifdef notyet 1348 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1349 MII_BMCR, BMCR_PDOWN); 1350 #endif 1351 return; 1352 } 1353 1354 ifp = sc->age_ifp; 1355 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1356 /* 1357 * Note, this driver resets the link speed to 10/100Mbps with 1358 * auto-negotiation but we don't know whether that operation 1359 * would succeed or not as it have no control after powering 1360 * off. If the renegotiation fail WOL may not work. Running 1361 * at 1Gbps will draw more power than 375mA at 3.3V which is 1362 * specified in PCI specification and that would result in 1363 * complete shutdowning power to ethernet controller. 1364 * 1365 * TODO 1366 * Save current negotiated media speed/duplex/flow-control 1367 * to softc and restore the same link again after resuming. 1368 * PHY handling such as power down/resetting to 100Mbps 1369 * may be better handled in suspend method in phy driver. 1370 */ 1371 mii = device_get_softc(sc->age_miibus); 1372 mii_pollstat(mii); 1373 aneg = 0; 1374 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1375 switch IFM_SUBTYPE(mii->mii_media_active) { 1376 case IFM_10_T: 1377 case IFM_100_TX: 1378 goto got_link; 1379 case IFM_1000_T: 1380 aneg++; 1381 default: 1382 break; 1383 } 1384 } 1385 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1386 MII_100T2CR, 0); 1387 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1388 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1389 ANAR_10 | ANAR_CSMA); 1390 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1391 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1392 DELAY(1000); 1393 if (aneg != 0) { 1394 /* Poll link state until age(4) get a 10/100 link. */ 1395 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1396 mii_pollstat(mii); 1397 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1398 switch (IFM_SUBTYPE( 1399 mii->mii_media_active)) { 1400 case IFM_10_T: 1401 case IFM_100_TX: 1402 age_mac_config(sc); 1403 goto got_link; 1404 default: 1405 break; 1406 } 1407 } 1408 AGE_UNLOCK(sc); 1409 pause("agelnk", hz); 1410 AGE_LOCK(sc); 1411 } 1412 if (i == MII_ANEGTICKS_GIGE) 1413 device_printf(sc->age_dev, 1414 "establishing link failed, " 1415 "WOL may not work!"); 1416 } 1417 /* 1418 * No link, force MAC to have 100Mbps, full-duplex link. 1419 * This is the last resort and may/may not work. 1420 */ 1421 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1422 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1423 age_mac_config(sc); 1424 } 1425 1426 got_link: 1427 pmcs = 0; 1428 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1429 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1430 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1431 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1432 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1433 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1434 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1435 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1436 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1437 reg |= MAC_CFG_RX_ENB; 1438 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1439 } 1440 1441 /* Request PME. */ 1442 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1443 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1444 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1445 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1446 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1447 #ifdef notyet 1448 /* See above for powering down PHY issues. */ 1449 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1450 /* No WOL, PHY power down. */ 1451 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1452 MII_BMCR, BMCR_PDOWN); 1453 } 1454 #endif 1455 } 1456 1457 static int 1458 age_suspend(device_t dev) 1459 { 1460 struct age_softc *sc; 1461 1462 sc = device_get_softc(dev); 1463 1464 AGE_LOCK(sc); 1465 age_stop(sc); 1466 age_setwol(sc); 1467 AGE_UNLOCK(sc); 1468 1469 return (0); 1470 } 1471 1472 static int 1473 age_resume(device_t dev) 1474 { 1475 struct age_softc *sc; 1476 struct ifnet *ifp; 1477 1478 sc = device_get_softc(dev); 1479 1480 AGE_LOCK(sc); 1481 age_phy_reset(sc); 1482 ifp = sc->age_ifp; 1483 if ((ifp->if_flags & IFF_UP) != 0) 1484 age_init_locked(sc); 1485 1486 AGE_UNLOCK(sc); 1487 1488 return (0); 1489 } 1490 1491 static int 1492 age_encap(struct age_softc *sc, struct mbuf **m_head) 1493 { 1494 struct age_txdesc *txd, *txd_last; 1495 struct tx_desc *desc; 1496 struct mbuf *m; 1497 struct ip *ip; 1498 struct tcphdr *tcp; 1499 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1500 bus_dmamap_t map; 1501 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1502 int error, i, nsegs, prod, si; 1503 1504 AGE_LOCK_ASSERT(sc); 1505 1506 M_ASSERTPKTHDR((*m_head)); 1507 1508 m = *m_head; 1509 ip = NULL; 1510 tcp = NULL; 1511 cflags = vtag = 0; 1512 ip_off = poff = 0; 1513 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1514 /* 1515 * L1 requires offset of TCP/UDP payload in its Tx 1516 * descriptor to perform hardware Tx checksum offload. 1517 * Additionally, TSO requires IP/TCP header size and 1518 * modification of IP/TCP header in order to make TSO 1519 * engine work. This kind of operation takes many CPU 1520 * cycles on FreeBSD so fast host CPU is needed to get 1521 * smooth TSO performance. 1522 */ 1523 struct ether_header *eh; 1524 1525 if (M_WRITABLE(m) == 0) { 1526 /* Get a writable copy. */ 1527 m = m_dup(*m_head, M_NOWAIT); 1528 /* Release original mbufs. */ 1529 m_freem(*m_head); 1530 if (m == NULL) { 1531 *m_head = NULL; 1532 return (ENOBUFS); 1533 } 1534 *m_head = m; 1535 } 1536 ip_off = sizeof(struct ether_header); 1537 m = m_pullup(m, ip_off); 1538 if (m == NULL) { 1539 *m_head = NULL; 1540 return (ENOBUFS); 1541 } 1542 eh = mtod(m, struct ether_header *); 1543 /* 1544 * Check if hardware VLAN insertion is off. 1545 * Additional check for LLC/SNAP frame? 1546 */ 1547 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1548 ip_off = sizeof(struct ether_vlan_header); 1549 m = m_pullup(m, ip_off); 1550 if (m == NULL) { 1551 *m_head = NULL; 1552 return (ENOBUFS); 1553 } 1554 } 1555 m = m_pullup(m, ip_off + sizeof(struct ip)); 1556 if (m == NULL) { 1557 *m_head = NULL; 1558 return (ENOBUFS); 1559 } 1560 ip = (struct ip *)(mtod(m, char *) + ip_off); 1561 poff = ip_off + (ip->ip_hl << 2); 1562 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1563 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1564 if (m == NULL) { 1565 *m_head = NULL; 1566 return (ENOBUFS); 1567 } 1568 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1569 m = m_pullup(m, poff + (tcp->th_off << 2)); 1570 if (m == NULL) { 1571 *m_head = NULL; 1572 return (ENOBUFS); 1573 } 1574 /* 1575 * L1 requires IP/TCP header size and offset as 1576 * well as TCP pseudo checksum which complicates 1577 * TSO configuration. I guess this comes from the 1578 * adherence to Microsoft NDIS Large Send 1579 * specification which requires insertion of 1580 * pseudo checksum by upper stack. The pseudo 1581 * checksum that NDIS refers to doesn't include 1582 * TCP payload length so age(4) should recompute 1583 * the pseudo checksum here. Hopefully this wouldn't 1584 * be much burden on modern CPUs. 1585 * Reset IP checksum and recompute TCP pseudo 1586 * checksum as NDIS specification said. 1587 */ 1588 ip = (struct ip *)(mtod(m, char *) + ip_off); 1589 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1590 ip->ip_sum = 0; 1591 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1592 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1593 } 1594 *m_head = m; 1595 } 1596 1597 si = prod = sc->age_cdata.age_tx_prod; 1598 txd = &sc->age_cdata.age_txdesc[prod]; 1599 txd_last = txd; 1600 map = txd->tx_dmamap; 1601 1602 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1603 *m_head, txsegs, &nsegs, 0); 1604 if (error == EFBIG) { 1605 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1606 if (m == NULL) { 1607 m_freem(*m_head); 1608 *m_head = NULL; 1609 return (ENOMEM); 1610 } 1611 *m_head = m; 1612 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1613 *m_head, txsegs, &nsegs, 0); 1614 if (error != 0) { 1615 m_freem(*m_head); 1616 *m_head = NULL; 1617 return (error); 1618 } 1619 } else if (error != 0) 1620 return (error); 1621 if (nsegs == 0) { 1622 m_freem(*m_head); 1623 *m_head = NULL; 1624 return (EIO); 1625 } 1626 1627 /* Check descriptor overrun. */ 1628 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1629 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1630 return (ENOBUFS); 1631 } 1632 1633 m = *m_head; 1634 /* Configure VLAN hardware tag insertion. */ 1635 if ((m->m_flags & M_VLANTAG) != 0) { 1636 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1637 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1638 cflags |= AGE_TD_INSERT_VLAN_TAG; 1639 } 1640 1641 desc = NULL; 1642 i = 0; 1643 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1644 /* Request TSO and set MSS. */ 1645 cflags |= AGE_TD_TSO_IPV4; 1646 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1647 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1648 AGE_TD_TSO_MSS_SHIFT); 1649 /* Set IP/TCP header size. */ 1650 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1651 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1652 /* 1653 * L1 requires the first buffer should only hold IP/TCP 1654 * header data. TCP payload should be handled in other 1655 * descriptors. 1656 */ 1657 hdrlen = poff + (tcp->th_off << 2); 1658 desc = &sc->age_rdata.age_tx_ring[prod]; 1659 desc->addr = htole64(txsegs[0].ds_addr); 1660 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1661 desc->flags = htole32(cflags); 1662 sc->age_cdata.age_tx_cnt++; 1663 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1664 if (m->m_len - hdrlen > 0) { 1665 /* Handle remaining payload of the 1st fragment. */ 1666 desc = &sc->age_rdata.age_tx_ring[prod]; 1667 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1668 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1669 vtag); 1670 desc->flags = htole32(cflags); 1671 sc->age_cdata.age_tx_cnt++; 1672 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1673 } 1674 /* Handle remaining fragments. */ 1675 i = 1; 1676 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1677 /* Configure Tx IP/TCP/UDP checksum offload. */ 1678 cflags |= AGE_TD_CSUM; 1679 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1680 cflags |= AGE_TD_TCPCSUM; 1681 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1682 cflags |= AGE_TD_UDPCSUM; 1683 /* Set checksum start offset. */ 1684 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1685 /* Set checksum insertion position of TCP/UDP. */ 1686 cflags |= ((poff + m->m_pkthdr.csum_data) << 1687 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1688 } 1689 for (; i < nsegs; i++) { 1690 desc = &sc->age_rdata.age_tx_ring[prod]; 1691 desc->addr = htole64(txsegs[i].ds_addr); 1692 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1693 desc->flags = htole32(cflags); 1694 sc->age_cdata.age_tx_cnt++; 1695 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1696 } 1697 /* Update producer index. */ 1698 sc->age_cdata.age_tx_prod = prod; 1699 1700 /* Set EOP on the last descriptor. */ 1701 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1702 desc = &sc->age_rdata.age_tx_ring[prod]; 1703 desc->flags |= htole32(AGE_TD_EOP); 1704 1705 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1706 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1707 desc = &sc->age_rdata.age_tx_ring[si]; 1708 desc->flags |= htole32(AGE_TD_TSO_HDR); 1709 } 1710 1711 /* Swap dmamap of the first and the last. */ 1712 txd = &sc->age_cdata.age_txdesc[prod]; 1713 map = txd_last->tx_dmamap; 1714 txd_last->tx_dmamap = txd->tx_dmamap; 1715 txd->tx_dmamap = map; 1716 txd->tx_m = m; 1717 1718 /* Sync descriptors. */ 1719 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1720 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1721 sc->age_cdata.age_tx_ring_map, 1722 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1723 1724 return (0); 1725 } 1726 1727 static void 1728 age_start(struct ifnet *ifp) 1729 { 1730 struct age_softc *sc; 1731 1732 sc = ifp->if_softc; 1733 AGE_LOCK(sc); 1734 age_start_locked(ifp); 1735 AGE_UNLOCK(sc); 1736 } 1737 1738 static void 1739 age_start_locked(struct ifnet *ifp) 1740 { 1741 struct age_softc *sc; 1742 struct mbuf *m_head; 1743 int enq; 1744 1745 sc = ifp->if_softc; 1746 1747 AGE_LOCK_ASSERT(sc); 1748 1749 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1750 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1751 return; 1752 1753 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1754 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1755 if (m_head == NULL) 1756 break; 1757 /* 1758 * Pack the data into the transmit ring. If we 1759 * don't have room, set the OACTIVE flag and wait 1760 * for the NIC to drain the ring. 1761 */ 1762 if (age_encap(sc, &m_head)) { 1763 if (m_head == NULL) 1764 break; 1765 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1766 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1767 break; 1768 } 1769 1770 enq++; 1771 /* 1772 * If there's a BPF listener, bounce a copy of this frame 1773 * to him. 1774 */ 1775 ETHER_BPF_MTAP(ifp, m_head); 1776 } 1777 1778 if (enq > 0) { 1779 /* Update mbox. */ 1780 AGE_COMMIT_MBOX(sc); 1781 /* Set a timeout in case the chip goes out to lunch. */ 1782 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1783 } 1784 } 1785 1786 static void 1787 age_watchdog(struct age_softc *sc) 1788 { 1789 struct ifnet *ifp; 1790 1791 AGE_LOCK_ASSERT(sc); 1792 1793 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1794 return; 1795 1796 ifp = sc->age_ifp; 1797 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1798 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1799 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1800 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1801 age_init_locked(sc); 1802 return; 1803 } 1804 if (sc->age_cdata.age_tx_cnt == 0) { 1805 if_printf(sc->age_ifp, 1806 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1807 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1808 age_start_locked(ifp); 1809 return; 1810 } 1811 if_printf(sc->age_ifp, "watchdog timeout\n"); 1812 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1813 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1814 age_init_locked(sc); 1815 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1816 age_start_locked(ifp); 1817 } 1818 1819 static int 1820 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1821 { 1822 struct age_softc *sc; 1823 struct ifreq *ifr; 1824 struct mii_data *mii; 1825 uint32_t reg; 1826 int error, mask; 1827 1828 sc = ifp->if_softc; 1829 ifr = (struct ifreq *)data; 1830 error = 0; 1831 switch (cmd) { 1832 case SIOCSIFMTU: 1833 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1834 error = EINVAL; 1835 else if (ifp->if_mtu != ifr->ifr_mtu) { 1836 AGE_LOCK(sc); 1837 ifp->if_mtu = ifr->ifr_mtu; 1838 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1839 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1840 age_init_locked(sc); 1841 } 1842 AGE_UNLOCK(sc); 1843 } 1844 break; 1845 case SIOCSIFFLAGS: 1846 AGE_LOCK(sc); 1847 if ((ifp->if_flags & IFF_UP) != 0) { 1848 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1849 if (((ifp->if_flags ^ sc->age_if_flags) 1850 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1851 age_rxfilter(sc); 1852 } else { 1853 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1854 age_init_locked(sc); 1855 } 1856 } else { 1857 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1858 age_stop(sc); 1859 } 1860 sc->age_if_flags = ifp->if_flags; 1861 AGE_UNLOCK(sc); 1862 break; 1863 case SIOCADDMULTI: 1864 case SIOCDELMULTI: 1865 AGE_LOCK(sc); 1866 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1867 age_rxfilter(sc); 1868 AGE_UNLOCK(sc); 1869 break; 1870 case SIOCSIFMEDIA: 1871 case SIOCGIFMEDIA: 1872 mii = device_get_softc(sc->age_miibus); 1873 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1874 break; 1875 case SIOCSIFCAP: 1876 AGE_LOCK(sc); 1877 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1878 if ((mask & IFCAP_TXCSUM) != 0 && 1879 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1880 ifp->if_capenable ^= IFCAP_TXCSUM; 1881 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1882 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1883 else 1884 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1885 } 1886 if ((mask & IFCAP_RXCSUM) != 0 && 1887 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1888 ifp->if_capenable ^= IFCAP_RXCSUM; 1889 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1890 reg &= ~MAC_CFG_RXCSUM_ENB; 1891 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1892 reg |= MAC_CFG_RXCSUM_ENB; 1893 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1894 } 1895 if ((mask & IFCAP_TSO4) != 0 && 1896 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1897 ifp->if_capenable ^= IFCAP_TSO4; 1898 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1899 ifp->if_hwassist |= CSUM_TSO; 1900 else 1901 ifp->if_hwassist &= ~CSUM_TSO; 1902 } 1903 1904 if ((mask & IFCAP_WOL_MCAST) != 0 && 1905 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1906 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1907 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1908 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1909 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1910 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1911 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1912 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1913 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1914 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1915 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1916 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1917 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1918 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1919 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1920 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1921 age_rxvlan(sc); 1922 } 1923 AGE_UNLOCK(sc); 1924 VLAN_CAPABILITIES(ifp); 1925 break; 1926 default: 1927 error = ether_ioctl(ifp, cmd, data); 1928 break; 1929 } 1930 1931 return (error); 1932 } 1933 1934 static void 1935 age_mac_config(struct age_softc *sc) 1936 { 1937 struct mii_data *mii; 1938 uint32_t reg; 1939 1940 AGE_LOCK_ASSERT(sc); 1941 1942 mii = device_get_softc(sc->age_miibus); 1943 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1944 reg &= ~MAC_CFG_FULL_DUPLEX; 1945 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1946 reg &= ~MAC_CFG_SPEED_MASK; 1947 /* Reprogram MAC with resolved speed/duplex. */ 1948 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1949 case IFM_10_T: 1950 case IFM_100_TX: 1951 reg |= MAC_CFG_SPEED_10_100; 1952 break; 1953 case IFM_1000_T: 1954 reg |= MAC_CFG_SPEED_1000; 1955 break; 1956 } 1957 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1958 reg |= MAC_CFG_FULL_DUPLEX; 1959 #ifdef notyet 1960 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1961 reg |= MAC_CFG_TX_FC; 1962 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1963 reg |= MAC_CFG_RX_FC; 1964 #endif 1965 } 1966 1967 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1968 } 1969 1970 static void 1971 age_link_task(void *arg, int pending) 1972 { 1973 struct age_softc *sc; 1974 struct mii_data *mii; 1975 struct ifnet *ifp; 1976 uint32_t reg; 1977 1978 sc = (struct age_softc *)arg; 1979 1980 AGE_LOCK(sc); 1981 mii = device_get_softc(sc->age_miibus); 1982 ifp = sc->age_ifp; 1983 if (mii == NULL || ifp == NULL || 1984 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1985 AGE_UNLOCK(sc); 1986 return; 1987 } 1988 1989 sc->age_flags &= ~AGE_FLAG_LINK; 1990 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1991 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1992 case IFM_10_T: 1993 case IFM_100_TX: 1994 case IFM_1000_T: 1995 sc->age_flags |= AGE_FLAG_LINK; 1996 break; 1997 default: 1998 break; 1999 } 2000 } 2001 2002 /* Stop Rx/Tx MACs. */ 2003 age_stop_rxmac(sc); 2004 age_stop_txmac(sc); 2005 2006 /* Program MACs with resolved speed/duplex/flow-control. */ 2007 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2008 age_mac_config(sc); 2009 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2010 /* Restart DMA engine and Tx/Rx MAC. */ 2011 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2012 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2013 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2014 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2015 } 2016 2017 AGE_UNLOCK(sc); 2018 } 2019 2020 static void 2021 age_stats_update(struct age_softc *sc) 2022 { 2023 struct age_stats *stat; 2024 struct smb *smb; 2025 struct ifnet *ifp; 2026 2027 AGE_LOCK_ASSERT(sc); 2028 2029 stat = &sc->age_stat; 2030 2031 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2032 sc->age_cdata.age_smb_block_map, 2033 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2034 2035 smb = sc->age_rdata.age_smb_block; 2036 if (smb->updated == 0) 2037 return; 2038 2039 ifp = sc->age_ifp; 2040 /* Rx stats. */ 2041 stat->rx_frames += smb->rx_frames; 2042 stat->rx_bcast_frames += smb->rx_bcast_frames; 2043 stat->rx_mcast_frames += smb->rx_mcast_frames; 2044 stat->rx_pause_frames += smb->rx_pause_frames; 2045 stat->rx_control_frames += smb->rx_control_frames; 2046 stat->rx_crcerrs += smb->rx_crcerrs; 2047 stat->rx_lenerrs += smb->rx_lenerrs; 2048 stat->rx_bytes += smb->rx_bytes; 2049 stat->rx_runts += smb->rx_runts; 2050 stat->rx_fragments += smb->rx_fragments; 2051 stat->rx_pkts_64 += smb->rx_pkts_64; 2052 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2053 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2054 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2055 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2056 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2057 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2058 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2059 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2060 stat->rx_desc_oflows += smb->rx_desc_oflows; 2061 stat->rx_alignerrs += smb->rx_alignerrs; 2062 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2063 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2064 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2065 2066 /* Tx stats. */ 2067 stat->tx_frames += smb->tx_frames; 2068 stat->tx_bcast_frames += smb->tx_bcast_frames; 2069 stat->tx_mcast_frames += smb->tx_mcast_frames; 2070 stat->tx_pause_frames += smb->tx_pause_frames; 2071 stat->tx_excess_defer += smb->tx_excess_defer; 2072 stat->tx_control_frames += smb->tx_control_frames; 2073 stat->tx_deferred += smb->tx_deferred; 2074 stat->tx_bytes += smb->tx_bytes; 2075 stat->tx_pkts_64 += smb->tx_pkts_64; 2076 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2077 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2078 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2079 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2080 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2081 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2082 stat->tx_single_colls += smb->tx_single_colls; 2083 stat->tx_multi_colls += smb->tx_multi_colls; 2084 stat->tx_late_colls += smb->tx_late_colls; 2085 stat->tx_excess_colls += smb->tx_excess_colls; 2086 stat->tx_underrun += smb->tx_underrun; 2087 stat->tx_desc_underrun += smb->tx_desc_underrun; 2088 stat->tx_lenerrs += smb->tx_lenerrs; 2089 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2090 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2091 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2092 2093 /* Update counters in ifnet. */ 2094 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2095 2096 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2097 smb->tx_multi_colls + smb->tx_late_colls + 2098 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2099 2100 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2101 smb->tx_late_colls + smb->tx_underrun + 2102 smb->tx_pkts_truncated); 2103 2104 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2105 2106 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2107 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2108 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2109 smb->rx_alignerrs); 2110 2111 /* Update done, clear. */ 2112 smb->updated = 0; 2113 2114 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2115 sc->age_cdata.age_smb_block_map, 2116 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2117 } 2118 2119 static int 2120 age_intr(void *arg) 2121 { 2122 struct age_softc *sc; 2123 uint32_t status; 2124 2125 sc = (struct age_softc *)arg; 2126 2127 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2128 if (status == 0 || (status & AGE_INTRS) == 0) 2129 return (FILTER_STRAY); 2130 /* Disable interrupts. */ 2131 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2132 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2133 2134 return (FILTER_HANDLED); 2135 } 2136 2137 static void 2138 age_int_task(void *arg, int pending) 2139 { 2140 struct age_softc *sc; 2141 struct ifnet *ifp; 2142 struct cmb *cmb; 2143 uint32_t status; 2144 2145 sc = (struct age_softc *)arg; 2146 2147 AGE_LOCK(sc); 2148 2149 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2150 sc->age_cdata.age_cmb_block_map, 2151 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2152 cmb = sc->age_rdata.age_cmb_block; 2153 status = le32toh(cmb->intr_status); 2154 if (sc->age_morework != 0) 2155 status |= INTR_CMB_RX; 2156 if ((status & AGE_INTRS) == 0) 2157 goto done; 2158 2159 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2160 TPD_CONS_SHIFT; 2161 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2162 RRD_PROD_SHIFT; 2163 /* Let hardware know CMB was served. */ 2164 cmb->intr_status = 0; 2165 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2166 sc->age_cdata.age_cmb_block_map, 2167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2168 2169 ifp = sc->age_ifp; 2170 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2171 if ((status & INTR_CMB_RX) != 0) 2172 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2173 sc->age_process_limit); 2174 if ((status & INTR_CMB_TX) != 0) 2175 age_txintr(sc, sc->age_tpd_cons); 2176 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2177 if ((status & INTR_DMA_RD_TO_RST) != 0) 2178 device_printf(sc->age_dev, 2179 "DMA read error! -- resetting\n"); 2180 if ((status & INTR_DMA_WR_TO_RST) != 0) 2181 device_printf(sc->age_dev, 2182 "DMA write error! -- resetting\n"); 2183 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2184 age_init_locked(sc); 2185 } 2186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2187 age_start_locked(ifp); 2188 if ((status & INTR_SMB) != 0) 2189 age_stats_update(sc); 2190 } 2191 2192 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2193 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2194 sc->age_cdata.age_cmb_block_map, 2195 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2196 status = le32toh(cmb->intr_status); 2197 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2198 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2199 AGE_UNLOCK(sc); 2200 return; 2201 } 2202 2203 done: 2204 /* Re-enable interrupts. */ 2205 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2206 AGE_UNLOCK(sc); 2207 } 2208 2209 static void 2210 age_txintr(struct age_softc *sc, int tpd_cons) 2211 { 2212 struct ifnet *ifp; 2213 struct age_txdesc *txd; 2214 int cons, prog; 2215 2216 AGE_LOCK_ASSERT(sc); 2217 2218 ifp = sc->age_ifp; 2219 2220 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2221 sc->age_cdata.age_tx_ring_map, 2222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2223 2224 /* 2225 * Go through our Tx list and free mbufs for those 2226 * frames which have been transmitted. 2227 */ 2228 cons = sc->age_cdata.age_tx_cons; 2229 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2230 if (sc->age_cdata.age_tx_cnt <= 0) 2231 break; 2232 prog++; 2233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2234 sc->age_cdata.age_tx_cnt--; 2235 txd = &sc->age_cdata.age_txdesc[cons]; 2236 /* 2237 * Clear Tx descriptors, it's not required but would 2238 * help debugging in case of Tx issues. 2239 */ 2240 txd->tx_desc->addr = 0; 2241 txd->tx_desc->len = 0; 2242 txd->tx_desc->flags = 0; 2243 2244 if (txd->tx_m == NULL) 2245 continue; 2246 /* Reclaim transmitted mbufs. */ 2247 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2248 BUS_DMASYNC_POSTWRITE); 2249 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2250 m_freem(txd->tx_m); 2251 txd->tx_m = NULL; 2252 } 2253 2254 if (prog > 0) { 2255 sc->age_cdata.age_tx_cons = cons; 2256 2257 /* 2258 * Unarm watchdog timer only when there are no pending 2259 * Tx descriptors in queue. 2260 */ 2261 if (sc->age_cdata.age_tx_cnt == 0) 2262 sc->age_watchdog_timer = 0; 2263 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2264 sc->age_cdata.age_tx_ring_map, 2265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2266 } 2267 } 2268 2269 #ifndef __NO_STRICT_ALIGNMENT 2270 static struct mbuf * 2271 age_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2272 { 2273 struct mbuf *n; 2274 int i; 2275 uint16_t *src, *dst; 2276 2277 src = mtod(m, uint16_t *); 2278 dst = src - 3; 2279 2280 if (m->m_next == NULL) { 2281 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2282 *dst++ = *src++; 2283 m->m_data -= 6; 2284 return (m); 2285 } 2286 /* 2287 * Append a new mbuf to received mbuf chain and copy ethernet 2288 * header from the mbuf chain. This can save lots of CPU 2289 * cycles for jumbo frame. 2290 */ 2291 MGETHDR(n, M_NOWAIT, MT_DATA); 2292 if (n == NULL) { 2293 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2294 m_freem(m); 2295 return (NULL); 2296 } 2297 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2298 m->m_data += ETHER_HDR_LEN; 2299 m->m_len -= ETHER_HDR_LEN; 2300 n->m_len = ETHER_HDR_LEN; 2301 M_MOVE_PKTHDR(n, m); 2302 n->m_next = m; 2303 return (n); 2304 } 2305 #endif 2306 2307 /* Receive a frame. */ 2308 static void 2309 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2310 { 2311 struct age_rxdesc *rxd; 2312 struct ifnet *ifp; 2313 struct mbuf *mp, *m; 2314 uint32_t status, index, vtag; 2315 int count, nsegs; 2316 int rx_cons; 2317 2318 AGE_LOCK_ASSERT(sc); 2319 2320 ifp = sc->age_ifp; 2321 status = le32toh(rxrd->flags); 2322 index = le32toh(rxrd->index); 2323 rx_cons = AGE_RX_CONS(index); 2324 nsegs = AGE_RX_NSEGS(index); 2325 2326 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2327 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2328 /* 2329 * We want to pass the following frames to upper 2330 * layer regardless of error status of Rx return 2331 * ring. 2332 * 2333 * o IP/TCP/UDP checksum is bad. 2334 * o frame length and protocol specific length 2335 * does not match. 2336 */ 2337 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2338 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2339 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2340 return; 2341 } 2342 2343 for (count = 0; count < nsegs; count++, 2344 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2345 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2346 mp = rxd->rx_m; 2347 /* Add a new receive buffer to the ring. */ 2348 if (age_newbuf(sc, rxd) != 0) { 2349 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2350 /* Reuse Rx buffers. */ 2351 if (sc->age_cdata.age_rxhead != NULL) 2352 m_freem(sc->age_cdata.age_rxhead); 2353 break; 2354 } 2355 2356 /* 2357 * Assume we've received a full sized frame. 2358 * Actual size is fixed when we encounter the end of 2359 * multi-segmented frame. 2360 */ 2361 mp->m_len = AGE_RX_BUF_SIZE; 2362 2363 /* Chain received mbufs. */ 2364 if (sc->age_cdata.age_rxhead == NULL) { 2365 sc->age_cdata.age_rxhead = mp; 2366 sc->age_cdata.age_rxtail = mp; 2367 } else { 2368 mp->m_flags &= ~M_PKTHDR; 2369 sc->age_cdata.age_rxprev_tail = 2370 sc->age_cdata.age_rxtail; 2371 sc->age_cdata.age_rxtail->m_next = mp; 2372 sc->age_cdata.age_rxtail = mp; 2373 } 2374 2375 if (count == nsegs - 1) { 2376 /* Last desc. for this frame. */ 2377 m = sc->age_cdata.age_rxhead; 2378 m->m_flags |= M_PKTHDR; 2379 /* 2380 * It seems that L1 controller has no way 2381 * to tell hardware to strip CRC bytes. 2382 */ 2383 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2384 ETHER_CRC_LEN; 2385 if (nsegs > 1) { 2386 /* Set last mbuf size. */ 2387 mp->m_len = sc->age_cdata.age_rxlen - 2388 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2389 /* Remove the CRC bytes in chained mbufs. */ 2390 if (mp->m_len <= ETHER_CRC_LEN) { 2391 sc->age_cdata.age_rxtail = 2392 sc->age_cdata.age_rxprev_tail; 2393 sc->age_cdata.age_rxtail->m_len -= 2394 (ETHER_CRC_LEN - mp->m_len); 2395 sc->age_cdata.age_rxtail->m_next = NULL; 2396 m_freem(mp); 2397 } else { 2398 mp->m_len -= ETHER_CRC_LEN; 2399 } 2400 } else 2401 m->m_len = m->m_pkthdr.len; 2402 m->m_pkthdr.rcvif = ifp; 2403 /* 2404 * Set checksum information. 2405 * It seems that L1 controller can compute partial 2406 * checksum. The partial checksum value can be used 2407 * to accelerate checksum computation for fragmented 2408 * TCP/UDP packets. Upper network stack already 2409 * takes advantage of the partial checksum value in 2410 * IP reassembly stage. But I'm not sure the 2411 * correctness of the partial hardware checksum 2412 * assistance due to lack of data sheet. If it is 2413 * proven to work on L1 I'll enable it. 2414 */ 2415 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2416 (status & AGE_RRD_IPV4) != 0) { 2417 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2418 m->m_pkthdr.csum_flags |= 2419 CSUM_IP_CHECKED | CSUM_IP_VALID; 2420 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2421 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2422 m->m_pkthdr.csum_flags |= 2423 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2424 m->m_pkthdr.csum_data = 0xffff; 2425 } 2426 /* 2427 * Don't mark bad checksum for TCP/UDP frames 2428 * as fragmented frames may always have set 2429 * bad checksummed bit of descriptor status. 2430 */ 2431 } 2432 2433 /* Check for VLAN tagged frames. */ 2434 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2435 (status & AGE_RRD_VLAN) != 0) { 2436 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2437 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2438 m->m_flags |= M_VLANTAG; 2439 } 2440 #ifndef __NO_STRICT_ALIGNMENT 2441 m = age_fixup_rx(ifp, m); 2442 if (m != NULL) 2443 #endif 2444 { 2445 /* Pass it on. */ 2446 AGE_UNLOCK(sc); 2447 (*ifp->if_input)(ifp, m); 2448 AGE_LOCK(sc); 2449 } 2450 } 2451 } 2452 2453 /* Reset mbuf chains. */ 2454 AGE_RXCHAIN_RESET(sc); 2455 } 2456 2457 static int 2458 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2459 { 2460 struct rx_rdesc *rxrd; 2461 int rr_cons, nsegs, pktlen, prog; 2462 2463 AGE_LOCK_ASSERT(sc); 2464 2465 rr_cons = sc->age_cdata.age_rr_cons; 2466 if (rr_cons == rr_prod) 2467 return (0); 2468 2469 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2470 sc->age_cdata.age_rr_ring_map, 2471 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2472 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2473 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2474 2475 for (prog = 0; rr_cons != rr_prod; prog++) { 2476 if (count-- <= 0) 2477 break; 2478 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2479 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2480 if (nsegs == 0) 2481 break; 2482 /* 2483 * Check number of segments against received bytes. 2484 * Non-matching value would indicate that hardware 2485 * is still trying to update Rx return descriptors. 2486 * I'm not sure whether this check is really needed. 2487 */ 2488 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2489 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2490 break; 2491 2492 /* Received a frame. */ 2493 age_rxeof(sc, rxrd); 2494 /* Clear return ring. */ 2495 rxrd->index = 0; 2496 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2497 sc->age_cdata.age_rx_cons += nsegs; 2498 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2499 } 2500 2501 if (prog > 0) { 2502 /* Update the consumer index. */ 2503 sc->age_cdata.age_rr_cons = rr_cons; 2504 2505 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2506 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2507 /* Sync descriptors. */ 2508 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2509 sc->age_cdata.age_rr_ring_map, 2510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2511 2512 /* Notify hardware availability of new Rx buffers. */ 2513 AGE_COMMIT_MBOX(sc); 2514 } 2515 2516 return (count > 0 ? 0 : EAGAIN); 2517 } 2518 2519 static void 2520 age_tick(void *arg) 2521 { 2522 struct age_softc *sc; 2523 struct mii_data *mii; 2524 2525 sc = (struct age_softc *)arg; 2526 2527 AGE_LOCK_ASSERT(sc); 2528 2529 mii = device_get_softc(sc->age_miibus); 2530 mii_tick(mii); 2531 age_watchdog(sc); 2532 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2533 } 2534 2535 static void 2536 age_reset(struct age_softc *sc) 2537 { 2538 uint32_t reg; 2539 int i; 2540 2541 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2542 CSR_READ_4(sc, AGE_MASTER_CFG); 2543 DELAY(1000); 2544 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2545 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2546 break; 2547 DELAY(10); 2548 } 2549 2550 if (i == 0) 2551 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2552 /* Initialize PCIe module. From Linux. */ 2553 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2554 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2555 } 2556 2557 static void 2558 age_init(void *xsc) 2559 { 2560 struct age_softc *sc; 2561 2562 sc = (struct age_softc *)xsc; 2563 AGE_LOCK(sc); 2564 age_init_locked(sc); 2565 AGE_UNLOCK(sc); 2566 } 2567 2568 static void 2569 age_init_locked(struct age_softc *sc) 2570 { 2571 struct ifnet *ifp; 2572 struct mii_data *mii; 2573 uint8_t eaddr[ETHER_ADDR_LEN]; 2574 bus_addr_t paddr; 2575 uint32_t reg, fsize; 2576 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2577 int error; 2578 2579 AGE_LOCK_ASSERT(sc); 2580 2581 ifp = sc->age_ifp; 2582 mii = device_get_softc(sc->age_miibus); 2583 2584 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2585 return; 2586 2587 /* 2588 * Cancel any pending I/O. 2589 */ 2590 age_stop(sc); 2591 2592 /* 2593 * Reset the chip to a known state. 2594 */ 2595 age_reset(sc); 2596 2597 /* Initialize descriptors. */ 2598 error = age_init_rx_ring(sc); 2599 if (error != 0) { 2600 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2601 age_stop(sc); 2602 return; 2603 } 2604 age_init_rr_ring(sc); 2605 age_init_tx_ring(sc); 2606 age_init_cmb_block(sc); 2607 age_init_smb_block(sc); 2608 2609 /* Reprogram the station address. */ 2610 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2611 CSR_WRITE_4(sc, AGE_PAR0, 2612 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2613 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2614 2615 /* Set descriptor base addresses. */ 2616 paddr = sc->age_rdata.age_tx_ring_paddr; 2617 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2618 paddr = sc->age_rdata.age_rx_ring_paddr; 2619 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2620 paddr = sc->age_rdata.age_rr_ring_paddr; 2621 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2622 paddr = sc->age_rdata.age_tx_ring_paddr; 2623 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2624 paddr = sc->age_rdata.age_cmb_block_paddr; 2625 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2626 paddr = sc->age_rdata.age_smb_block_paddr; 2627 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2628 /* Set Rx/Rx return descriptor counter. */ 2629 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2630 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2631 DESC_RRD_CNT_MASK) | 2632 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2633 /* Set Tx descriptor counter. */ 2634 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2635 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2636 2637 /* Tell hardware that we're ready to load descriptors. */ 2638 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2639 2640 /* 2641 * Initialize mailbox register. 2642 * Updated producer/consumer index information is exchanged 2643 * through this mailbox register. However Tx producer and 2644 * Rx return consumer/Rx producer are all shared such that 2645 * it's hard to separate code path between Tx and Rx without 2646 * locking. If L1 hardware have a separate mail box register 2647 * for Tx and Rx consumer/producer management we could have 2648 * indepent Tx/Rx handler which in turn Rx handler could have 2649 * been run without any locking. 2650 */ 2651 AGE_COMMIT_MBOX(sc); 2652 2653 /* Configure IPG/IFG parameters. */ 2654 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2655 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2656 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2657 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2658 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2659 2660 /* Set parameters for half-duplex media. */ 2661 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2662 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2663 HDPX_CFG_LCOL_MASK) | 2664 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2665 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2666 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2667 HDPX_CFG_ABEBT_MASK) | 2668 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2669 HDPX_CFG_JAMIPG_MASK)); 2670 2671 /* Configure interrupt moderation timer. */ 2672 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2673 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2674 reg &= ~MASTER_MTIMER_ENB; 2675 if (AGE_USECS(sc->age_int_mod) == 0) 2676 reg &= ~MASTER_ITIMER_ENB; 2677 else 2678 reg |= MASTER_ITIMER_ENB; 2679 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2680 if (bootverbose) 2681 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2682 sc->age_int_mod); 2683 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2684 2685 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2686 if (ifp->if_mtu < ETHERMTU) 2687 sc->age_max_frame_size = ETHERMTU; 2688 else 2689 sc->age_max_frame_size = ifp->if_mtu; 2690 sc->age_max_frame_size += ETHER_HDR_LEN + 2691 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2692 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2693 /* Configure jumbo frame. */ 2694 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2695 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2696 (((fsize / sizeof(uint64_t)) << 2697 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2698 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2699 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2700 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2701 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2702 2703 /* Configure flow-control parameters. From Linux. */ 2704 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2705 /* 2706 * Magic workaround for old-L1. 2707 * Don't know which hw revision requires this magic. 2708 */ 2709 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2710 /* 2711 * Another magic workaround for flow-control mode 2712 * change. From Linux. 2713 */ 2714 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2715 } 2716 /* 2717 * TODO 2718 * Should understand pause parameter relationships between FIFO 2719 * size and number of Rx descriptors and Rx return descriptors. 2720 * 2721 * Magic parameters came from Linux. 2722 */ 2723 switch (sc->age_chip_rev) { 2724 case 0x8001: 2725 case 0x9001: 2726 case 0x9002: 2727 case 0x9003: 2728 rxf_hi = AGE_RX_RING_CNT / 16; 2729 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2730 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2731 rrd_lo = AGE_RR_RING_CNT / 16; 2732 break; 2733 default: 2734 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2735 rxf_lo = reg / 16; 2736 if (rxf_lo < 192) 2737 rxf_lo = 192; 2738 rxf_hi = (reg * 7) / 8; 2739 if (rxf_hi < rxf_lo) 2740 rxf_hi = rxf_lo + 16; 2741 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2742 rrd_lo = reg / 8; 2743 rrd_hi = (reg * 7) / 8; 2744 if (rrd_lo < 2) 2745 rrd_lo = 2; 2746 if (rrd_hi < rrd_lo) 2747 rrd_hi = rrd_lo + 3; 2748 break; 2749 } 2750 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2751 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2752 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2753 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2754 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2755 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2756 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2757 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2758 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2759 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2760 2761 /* Configure RxQ. */ 2762 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2763 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2764 RXQ_CFG_RD_BURST_MASK) | 2765 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2766 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2767 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2768 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2769 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2770 2771 /* Configure TxQ. */ 2772 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2773 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2774 TXQ_CFG_TPD_BURST_MASK) | 2775 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2776 TXQ_CFG_TX_FIFO_BURST_MASK) | 2777 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2778 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2779 TXQ_CFG_ENB); 2780 2781 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2782 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2783 TX_JUMBO_TPD_TH_MASK) | 2784 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2785 TX_JUMBO_TPD_IPG_MASK)); 2786 /* Configure DMA parameters. */ 2787 CSR_WRITE_4(sc, AGE_DMA_CFG, 2788 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2789 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2790 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2791 2792 /* Configure CMB DMA write threshold. */ 2793 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2794 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2795 CMB_WR_THRESH_RRD_MASK) | 2796 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2797 CMB_WR_THRESH_TPD_MASK)); 2798 2799 /* Set CMB/SMB timer and enable them. */ 2800 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2801 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2802 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2803 /* Request SMB updates for every seconds. */ 2804 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2805 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2806 2807 /* 2808 * Disable all WOL bits as WOL can interfere normal Rx 2809 * operation. 2810 */ 2811 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2812 2813 /* 2814 * Configure Tx/Rx MACs. 2815 * - Auto-padding for short frames. 2816 * - Enable CRC generation. 2817 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2818 * of MAC is followed after link establishment. 2819 */ 2820 CSR_WRITE_4(sc, AGE_MAC_CFG, 2821 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2822 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2823 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2824 MAC_CFG_PREAMBLE_MASK)); 2825 /* Set up the receive filter. */ 2826 age_rxfilter(sc); 2827 age_rxvlan(sc); 2828 2829 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2830 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2831 reg |= MAC_CFG_RXCSUM_ENB; 2832 2833 /* Ack all pending interrupts and clear it. */ 2834 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2835 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2836 2837 /* Finally enable Tx/Rx MAC. */ 2838 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2839 2840 sc->age_flags &= ~AGE_FLAG_LINK; 2841 /* Switch to the current media. */ 2842 mii_mediachg(mii); 2843 2844 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2845 2846 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2847 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2848 } 2849 2850 static void 2851 age_stop(struct age_softc *sc) 2852 { 2853 struct ifnet *ifp; 2854 struct age_txdesc *txd; 2855 struct age_rxdesc *rxd; 2856 uint32_t reg; 2857 int i; 2858 2859 AGE_LOCK_ASSERT(sc); 2860 /* 2861 * Mark the interface down and cancel the watchdog timer. 2862 */ 2863 ifp = sc->age_ifp; 2864 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2865 sc->age_flags &= ~AGE_FLAG_LINK; 2866 callout_stop(&sc->age_tick_ch); 2867 sc->age_watchdog_timer = 0; 2868 2869 /* 2870 * Disable interrupts. 2871 */ 2872 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2873 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2874 /* Stop CMB/SMB updates. */ 2875 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2876 /* Stop Rx/Tx MAC. */ 2877 age_stop_rxmac(sc); 2878 age_stop_txmac(sc); 2879 /* Stop DMA. */ 2880 CSR_WRITE_4(sc, AGE_DMA_CFG, 2881 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2882 /* Stop TxQ/RxQ. */ 2883 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2884 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2885 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2886 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2887 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2888 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2889 break; 2890 DELAY(10); 2891 } 2892 if (i == 0) 2893 device_printf(sc->age_dev, 2894 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2895 2896 /* Reclaim Rx buffers that have been processed. */ 2897 if (sc->age_cdata.age_rxhead != NULL) 2898 m_freem(sc->age_cdata.age_rxhead); 2899 AGE_RXCHAIN_RESET(sc); 2900 /* 2901 * Free RX and TX mbufs still in the queues. 2902 */ 2903 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2904 rxd = &sc->age_cdata.age_rxdesc[i]; 2905 if (rxd->rx_m != NULL) { 2906 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2907 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2908 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2909 rxd->rx_dmamap); 2910 m_freem(rxd->rx_m); 2911 rxd->rx_m = NULL; 2912 } 2913 } 2914 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2915 txd = &sc->age_cdata.age_txdesc[i]; 2916 if (txd->tx_m != NULL) { 2917 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2918 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2919 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2920 txd->tx_dmamap); 2921 m_freem(txd->tx_m); 2922 txd->tx_m = NULL; 2923 } 2924 } 2925 } 2926 2927 static void 2928 age_stop_txmac(struct age_softc *sc) 2929 { 2930 uint32_t reg; 2931 int i; 2932 2933 AGE_LOCK_ASSERT(sc); 2934 2935 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2936 if ((reg & MAC_CFG_TX_ENB) != 0) { 2937 reg &= ~MAC_CFG_TX_ENB; 2938 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2939 } 2940 /* Stop Tx DMA engine. */ 2941 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2942 if ((reg & DMA_CFG_RD_ENB) != 0) { 2943 reg &= ~DMA_CFG_RD_ENB; 2944 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2945 } 2946 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2947 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2948 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2949 break; 2950 DELAY(10); 2951 } 2952 if (i == 0) 2953 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2954 } 2955 2956 static void 2957 age_stop_rxmac(struct age_softc *sc) 2958 { 2959 uint32_t reg; 2960 int i; 2961 2962 AGE_LOCK_ASSERT(sc); 2963 2964 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2965 if ((reg & MAC_CFG_RX_ENB) != 0) { 2966 reg &= ~MAC_CFG_RX_ENB; 2967 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2968 } 2969 /* Stop Rx DMA engine. */ 2970 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2971 if ((reg & DMA_CFG_WR_ENB) != 0) { 2972 reg &= ~DMA_CFG_WR_ENB; 2973 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2974 } 2975 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2976 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2977 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2978 break; 2979 DELAY(10); 2980 } 2981 if (i == 0) 2982 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2983 } 2984 2985 static void 2986 age_init_tx_ring(struct age_softc *sc) 2987 { 2988 struct age_ring_data *rd; 2989 struct age_txdesc *txd; 2990 int i; 2991 2992 AGE_LOCK_ASSERT(sc); 2993 2994 sc->age_cdata.age_tx_prod = 0; 2995 sc->age_cdata.age_tx_cons = 0; 2996 sc->age_cdata.age_tx_cnt = 0; 2997 2998 rd = &sc->age_rdata; 2999 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 3000 for (i = 0; i < AGE_TX_RING_CNT; i++) { 3001 txd = &sc->age_cdata.age_txdesc[i]; 3002 txd->tx_desc = &rd->age_tx_ring[i]; 3003 txd->tx_m = NULL; 3004 } 3005 3006 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3007 sc->age_cdata.age_tx_ring_map, 3008 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3009 } 3010 3011 static int 3012 age_init_rx_ring(struct age_softc *sc) 3013 { 3014 struct age_ring_data *rd; 3015 struct age_rxdesc *rxd; 3016 int i; 3017 3018 AGE_LOCK_ASSERT(sc); 3019 3020 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3021 sc->age_morework = 0; 3022 rd = &sc->age_rdata; 3023 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3024 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3025 rxd = &sc->age_cdata.age_rxdesc[i]; 3026 rxd->rx_m = NULL; 3027 rxd->rx_desc = &rd->age_rx_ring[i]; 3028 if (age_newbuf(sc, rxd) != 0) 3029 return (ENOBUFS); 3030 } 3031 3032 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3033 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3034 3035 return (0); 3036 } 3037 3038 static void 3039 age_init_rr_ring(struct age_softc *sc) 3040 { 3041 struct age_ring_data *rd; 3042 3043 AGE_LOCK_ASSERT(sc); 3044 3045 sc->age_cdata.age_rr_cons = 0; 3046 AGE_RXCHAIN_RESET(sc); 3047 3048 rd = &sc->age_rdata; 3049 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3050 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3051 sc->age_cdata.age_rr_ring_map, 3052 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3053 } 3054 3055 static void 3056 age_init_cmb_block(struct age_softc *sc) 3057 { 3058 struct age_ring_data *rd; 3059 3060 AGE_LOCK_ASSERT(sc); 3061 3062 rd = &sc->age_rdata; 3063 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3064 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3065 sc->age_cdata.age_cmb_block_map, 3066 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3067 } 3068 3069 static void 3070 age_init_smb_block(struct age_softc *sc) 3071 { 3072 struct age_ring_data *rd; 3073 3074 AGE_LOCK_ASSERT(sc); 3075 3076 rd = &sc->age_rdata; 3077 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3078 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3079 sc->age_cdata.age_smb_block_map, 3080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3081 } 3082 3083 static int 3084 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3085 { 3086 struct rx_desc *desc; 3087 struct mbuf *m; 3088 bus_dma_segment_t segs[1]; 3089 bus_dmamap_t map; 3090 int nsegs; 3091 3092 AGE_LOCK_ASSERT(sc); 3093 3094 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3095 if (m == NULL) 3096 return (ENOBUFS); 3097 m->m_len = m->m_pkthdr.len = MCLBYTES; 3098 #ifndef __NO_STRICT_ALIGNMENT 3099 m_adj(m, AGE_RX_BUF_ALIGN); 3100 #endif 3101 3102 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3103 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3104 m_freem(m); 3105 return (ENOBUFS); 3106 } 3107 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3108 3109 if (rxd->rx_m != NULL) { 3110 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3111 BUS_DMASYNC_POSTREAD); 3112 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3113 } 3114 map = rxd->rx_dmamap; 3115 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3116 sc->age_cdata.age_rx_sparemap = map; 3117 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3118 BUS_DMASYNC_PREREAD); 3119 rxd->rx_m = m; 3120 3121 desc = rxd->rx_desc; 3122 desc->addr = htole64(segs[0].ds_addr); 3123 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3124 AGE_RD_LEN_SHIFT); 3125 return (0); 3126 } 3127 3128 static void 3129 age_rxvlan(struct age_softc *sc) 3130 { 3131 struct ifnet *ifp; 3132 uint32_t reg; 3133 3134 AGE_LOCK_ASSERT(sc); 3135 3136 ifp = sc->age_ifp; 3137 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3138 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3139 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3140 reg |= MAC_CFG_VLAN_TAG_STRIP; 3141 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3142 } 3143 3144 static u_int 3145 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3146 { 3147 uint32_t *mchash = arg; 3148 uint32_t crc; 3149 3150 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3151 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3152 3153 return (1); 3154 } 3155 3156 static void 3157 age_rxfilter(struct age_softc *sc) 3158 { 3159 struct ifnet *ifp; 3160 uint32_t mchash[2]; 3161 uint32_t rxcfg; 3162 3163 AGE_LOCK_ASSERT(sc); 3164 3165 ifp = sc->age_ifp; 3166 3167 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3168 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3169 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3170 rxcfg |= MAC_CFG_BCAST; 3171 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3172 if ((ifp->if_flags & IFF_PROMISC) != 0) 3173 rxcfg |= MAC_CFG_PROMISC; 3174 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3175 rxcfg |= MAC_CFG_ALLMULTI; 3176 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3177 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3178 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3179 return; 3180 } 3181 3182 /* Program new filter. */ 3183 bzero(mchash, sizeof(mchash)); 3184 if_foreach_llmaddr(ifp, age_hash_maddr, mchash); 3185 3186 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3187 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3188 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3189 } 3190 3191 static int 3192 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3193 { 3194 struct age_softc *sc; 3195 struct age_stats *stats; 3196 int error, result; 3197 3198 result = -1; 3199 error = sysctl_handle_int(oidp, &result, 0, req); 3200 3201 if (error != 0 || req->newptr == NULL) 3202 return (error); 3203 3204 if (result != 1) 3205 return (error); 3206 3207 sc = (struct age_softc *)arg1; 3208 stats = &sc->age_stat; 3209 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3210 printf("Transmit good frames : %ju\n", 3211 (uintmax_t)stats->tx_frames); 3212 printf("Transmit good broadcast frames : %ju\n", 3213 (uintmax_t)stats->tx_bcast_frames); 3214 printf("Transmit good multicast frames : %ju\n", 3215 (uintmax_t)stats->tx_mcast_frames); 3216 printf("Transmit pause control frames : %u\n", 3217 stats->tx_pause_frames); 3218 printf("Transmit control frames : %u\n", 3219 stats->tx_control_frames); 3220 printf("Transmit frames with excessive deferrals : %u\n", 3221 stats->tx_excess_defer); 3222 printf("Transmit deferrals : %u\n", 3223 stats->tx_deferred); 3224 printf("Transmit good octets : %ju\n", 3225 (uintmax_t)stats->tx_bytes); 3226 printf("Transmit good broadcast octets : %ju\n", 3227 (uintmax_t)stats->tx_bcast_bytes); 3228 printf("Transmit good multicast octets : %ju\n", 3229 (uintmax_t)stats->tx_mcast_bytes); 3230 printf("Transmit frames 64 bytes : %ju\n", 3231 (uintmax_t)stats->tx_pkts_64); 3232 printf("Transmit frames 65 to 127 bytes : %ju\n", 3233 (uintmax_t)stats->tx_pkts_65_127); 3234 printf("Transmit frames 128 to 255 bytes : %ju\n", 3235 (uintmax_t)stats->tx_pkts_128_255); 3236 printf("Transmit frames 256 to 511 bytes : %ju\n", 3237 (uintmax_t)stats->tx_pkts_256_511); 3238 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3239 (uintmax_t)stats->tx_pkts_512_1023); 3240 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3241 (uintmax_t)stats->tx_pkts_1024_1518); 3242 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3243 (uintmax_t)stats->tx_pkts_1519_max); 3244 printf("Transmit single collisions : %u\n", 3245 stats->tx_single_colls); 3246 printf("Transmit multiple collisions : %u\n", 3247 stats->tx_multi_colls); 3248 printf("Transmit late collisions : %u\n", 3249 stats->tx_late_colls); 3250 printf("Transmit abort due to excessive collisions : %u\n", 3251 stats->tx_excess_colls); 3252 printf("Transmit underruns due to FIFO underruns : %u\n", 3253 stats->tx_underrun); 3254 printf("Transmit descriptor write-back errors : %u\n", 3255 stats->tx_desc_underrun); 3256 printf("Transmit frames with length mismatched frame size : %u\n", 3257 stats->tx_lenerrs); 3258 printf("Transmit frames with truncated due to MTU size : %u\n", 3259 stats->tx_lenerrs); 3260 3261 printf("Receive good frames : %ju\n", 3262 (uintmax_t)stats->rx_frames); 3263 printf("Receive good broadcast frames : %ju\n", 3264 (uintmax_t)stats->rx_bcast_frames); 3265 printf("Receive good multicast frames : %ju\n", 3266 (uintmax_t)stats->rx_mcast_frames); 3267 printf("Receive pause control frames : %u\n", 3268 stats->rx_pause_frames); 3269 printf("Receive control frames : %u\n", 3270 stats->rx_control_frames); 3271 printf("Receive CRC errors : %u\n", 3272 stats->rx_crcerrs); 3273 printf("Receive frames with length errors : %u\n", 3274 stats->rx_lenerrs); 3275 printf("Receive good octets : %ju\n", 3276 (uintmax_t)stats->rx_bytes); 3277 printf("Receive good broadcast octets : %ju\n", 3278 (uintmax_t)stats->rx_bcast_bytes); 3279 printf("Receive good multicast octets : %ju\n", 3280 (uintmax_t)stats->rx_mcast_bytes); 3281 printf("Receive frames too short : %u\n", 3282 stats->rx_runts); 3283 printf("Receive fragmented frames : %ju\n", 3284 (uintmax_t)stats->rx_fragments); 3285 printf("Receive frames 64 bytes : %ju\n", 3286 (uintmax_t)stats->rx_pkts_64); 3287 printf("Receive frames 65 to 127 bytes : %ju\n", 3288 (uintmax_t)stats->rx_pkts_65_127); 3289 printf("Receive frames 128 to 255 bytes : %ju\n", 3290 (uintmax_t)stats->rx_pkts_128_255); 3291 printf("Receive frames 256 to 511 bytes : %ju\n", 3292 (uintmax_t)stats->rx_pkts_256_511); 3293 printf("Receive frames 512 to 1024 bytes : %ju\n", 3294 (uintmax_t)stats->rx_pkts_512_1023); 3295 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3296 (uintmax_t)stats->rx_pkts_1024_1518); 3297 printf("Receive frames 1519 to MTU bytes : %ju\n", 3298 (uintmax_t)stats->rx_pkts_1519_max); 3299 printf("Receive frames too long : %ju\n", 3300 (uint64_t)stats->rx_pkts_truncated); 3301 printf("Receive frames with FIFO overflow : %u\n", 3302 stats->rx_fifo_oflows); 3303 printf("Receive frames with return descriptor overflow : %u\n", 3304 stats->rx_desc_oflows); 3305 printf("Receive frames with alignment errors : %u\n", 3306 stats->rx_alignerrs); 3307 printf("Receive frames dropped due to address filtering : %ju\n", 3308 (uint64_t)stats->rx_pkts_filtered); 3309 3310 return (error); 3311 } 3312 3313 static int 3314 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3315 { 3316 int error, value; 3317 3318 if (arg1 == NULL) 3319 return (EINVAL); 3320 value = *(int *)arg1; 3321 error = sysctl_handle_int(oidp, &value, 0, req); 3322 if (error || req->newptr == NULL) 3323 return (error); 3324 if (value < low || value > high) 3325 return (EINVAL); 3326 *(int *)arg1 = value; 3327 3328 return (0); 3329 } 3330 3331 static int 3332 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3333 { 3334 return (sysctl_int_range(oidp, arg1, arg2, req, 3335 AGE_PROC_MIN, AGE_PROC_MAX)); 3336 } 3337 3338 static int 3339 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3340 { 3341 3342 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3343 AGE_IM_TIMER_MAX)); 3344 } 3345