1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/age/if_agereg.h> 72 #include <dev/age/if_agevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #ifndef IFCAP_VLAN_HWTSO 78 #define IFCAP_VLAN_HWTSO 0 79 #endif 80 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(age, pci, 1, 1, 1); 83 MODULE_DEPEND(age, ether, 1, 1, 1); 84 MODULE_DEPEND(age, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct age_dev { 96 uint16_t age_vendorid; 97 uint16_t age_deviceid; 98 const char *age_name; 99 } age_devs[] = { 100 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102 }; 103 104 static int age_miibus_readreg(device_t, int, int); 105 static int age_miibus_writereg(device_t, int, int, int); 106 static void age_miibus_statchg(device_t); 107 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 108 static int age_mediachange(struct ifnet *); 109 static int age_probe(device_t); 110 static void age_get_macaddr(struct age_softc *); 111 static void age_phy_reset(struct age_softc *); 112 static int age_attach(device_t); 113 static int age_detach(device_t); 114 static void age_sysctl_node(struct age_softc *); 115 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 116 static int age_check_boundary(struct age_softc *); 117 static int age_dma_alloc(struct age_softc *); 118 static void age_dma_free(struct age_softc *); 119 static int age_shutdown(device_t); 120 static void age_setwol(struct age_softc *); 121 static int age_suspend(device_t); 122 static int age_resume(device_t); 123 static int age_encap(struct age_softc *, struct mbuf **); 124 static void age_tx_task(void *, int); 125 static void age_start(struct ifnet *); 126 static void age_watchdog(struct age_softc *); 127 static int age_ioctl(struct ifnet *, u_long, caddr_t); 128 static void age_mac_config(struct age_softc *); 129 static void age_link_task(void *, int); 130 static void age_stats_update(struct age_softc *); 131 static int age_intr(void *); 132 static void age_int_task(void *, int); 133 static void age_txintr(struct age_softc *, int); 134 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 135 static int age_rxintr(struct age_softc *, int, int); 136 static void age_tick(void *); 137 static void age_reset(struct age_softc *); 138 static void age_init(void *); 139 static void age_init_locked(struct age_softc *); 140 static void age_stop(struct age_softc *); 141 static void age_stop_txmac(struct age_softc *); 142 static void age_stop_rxmac(struct age_softc *); 143 static void age_init_tx_ring(struct age_softc *); 144 static int age_init_rx_ring(struct age_softc *); 145 static void age_init_rr_ring(struct age_softc *); 146 static void age_init_cmb_block(struct age_softc *); 147 static void age_init_smb_block(struct age_softc *); 148 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 149 static void age_rxvlan(struct age_softc *); 150 static void age_rxfilter(struct age_softc *); 151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 155 156 157 static device_method_t age_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, age_probe), 160 DEVMETHOD(device_attach, age_attach), 161 DEVMETHOD(device_detach, age_detach), 162 DEVMETHOD(device_shutdown, age_shutdown), 163 DEVMETHOD(device_suspend, age_suspend), 164 DEVMETHOD(device_resume, age_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, age_miibus_readreg), 168 DEVMETHOD(miibus_writereg, age_miibus_writereg), 169 DEVMETHOD(miibus_statchg, age_miibus_statchg), 170 171 { NULL, NULL } 172 }; 173 174 static driver_t age_driver = { 175 "age", 176 age_methods, 177 sizeof(struct age_softc) 178 }; 179 180 static devclass_t age_devclass; 181 182 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 183 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 184 185 static struct resource_spec age_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec age_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec age_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static struct resource_spec age_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203 }; 204 205 /* 206 * Read a PHY register on the MII of the L1. 207 */ 208 static int 209 age_miibus_readreg(device_t dev, int phy, int reg) 210 { 211 struct age_softc *sc; 212 uint32_t v; 213 int i; 214 215 sc = device_get_softc(dev); 216 if (phy != sc->age_phyaddr) 217 return (0); 218 219 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 220 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 221 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 222 DELAY(1); 223 v = CSR_READ_4(sc, AGE_MDIO); 224 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 225 break; 226 } 227 228 if (i == 0) { 229 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 230 return (0); 231 } 232 233 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 234 } 235 236 /* 237 * Write a PHY register on the MII of the L1. 238 */ 239 static int 240 age_miibus_writereg(device_t dev, int phy, int reg, int val) 241 { 242 struct age_softc *sc; 243 uint32_t v; 244 int i; 245 246 sc = device_get_softc(dev); 247 if (phy != sc->age_phyaddr) 248 return (0); 249 250 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 251 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 252 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 253 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 254 DELAY(1); 255 v = CSR_READ_4(sc, AGE_MDIO); 256 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 257 break; 258 } 259 260 if (i == 0) 261 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 262 263 return (0); 264 } 265 266 /* 267 * Callback from MII layer when media changes. 268 */ 269 static void 270 age_miibus_statchg(device_t dev) 271 { 272 struct age_softc *sc; 273 274 sc = device_get_softc(dev); 275 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 276 } 277 278 /* 279 * Get the current interface media status. 280 */ 281 static void 282 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 283 { 284 struct age_softc *sc; 285 struct mii_data *mii; 286 287 sc = ifp->if_softc; 288 AGE_LOCK(sc); 289 mii = device_get_softc(sc->age_miibus); 290 291 mii_pollstat(mii); 292 AGE_UNLOCK(sc); 293 ifmr->ifm_status = mii->mii_media_status; 294 ifmr->ifm_active = mii->mii_media_active; 295 } 296 297 /* 298 * Set hardware to newly-selected media. 299 */ 300 static int 301 age_mediachange(struct ifnet *ifp) 302 { 303 struct age_softc *sc; 304 struct mii_data *mii; 305 struct mii_softc *miisc; 306 int error; 307 308 sc = ifp->if_softc; 309 AGE_LOCK(sc); 310 mii = device_get_softc(sc->age_miibus); 311 if (mii->mii_instance != 0) { 312 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 313 mii_phy_reset(miisc); 314 } 315 error = mii_mediachg(mii); 316 AGE_UNLOCK(sc); 317 318 return (error); 319 } 320 321 static int 322 age_probe(device_t dev) 323 { 324 struct age_dev *sp; 325 int i; 326 uint16_t vendor, devid; 327 328 vendor = pci_get_vendor(dev); 329 devid = pci_get_device(dev); 330 sp = age_devs; 331 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 332 i++, sp++) { 333 if (vendor == sp->age_vendorid && 334 devid == sp->age_deviceid) { 335 device_set_desc(dev, sp->age_name); 336 return (BUS_PROBE_DEFAULT); 337 } 338 } 339 340 return (ENXIO); 341 } 342 343 static void 344 age_get_macaddr(struct age_softc *sc) 345 { 346 uint32_t ea[2], reg; 347 int i, vpdc; 348 349 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 350 if ((reg & SPI_VPD_ENB) != 0) { 351 /* Get VPD stored in TWSI EEPROM. */ 352 reg &= ~SPI_VPD_ENB; 353 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 354 } 355 356 if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 357 /* 358 * PCI VPD capability found, let TWSI reload EEPROM. 359 * This will set ethernet address of controller. 360 */ 361 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 362 TWSI_CTRL_SW_LD_START); 363 for (i = 100; i > 0; i--) { 364 DELAY(1000); 365 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 366 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 367 break; 368 } 369 if (i == 0) 370 device_printf(sc->age_dev, 371 "reloading EEPROM timeout!\n"); 372 } else { 373 if (bootverbose) 374 device_printf(sc->age_dev, 375 "PCI VPD capability not found!\n"); 376 } 377 378 ea[0] = CSR_READ_4(sc, AGE_PAR0); 379 ea[1] = CSR_READ_4(sc, AGE_PAR1); 380 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 381 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 382 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 383 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 384 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 385 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 386 } 387 388 static void 389 age_phy_reset(struct age_softc *sc) 390 { 391 uint16_t reg, pn; 392 int i, linkup; 393 394 /* Reset PHY. */ 395 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 396 DELAY(2000); 397 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 398 DELAY(2000); 399 400 #define ATPHY_DBG_ADDR 0x1D 401 #define ATPHY_DBG_DATA 0x1E 402 #define ATPHY_CDTC 0x16 403 #define PHY_CDTC_ENB 0x0001 404 #define PHY_CDTC_POFF 8 405 #define ATPHY_CDTS 0x1C 406 #define PHY_CDTS_STAT_OK 0x0000 407 #define PHY_CDTS_STAT_SHORT 0x0100 408 #define PHY_CDTS_STAT_OPEN 0x0200 409 #define PHY_CDTS_STAT_INVAL 0x0300 410 #define PHY_CDTS_STAT_MASK 0x0300 411 412 /* Check power saving mode. Magic from Linux. */ 413 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 414 for (linkup = 0, pn = 0; pn < 4; pn++) { 415 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 416 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 417 for (i = 200; i > 0; i--) { 418 DELAY(1000); 419 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 420 ATPHY_CDTC); 421 if ((reg & PHY_CDTC_ENB) == 0) 422 break; 423 } 424 DELAY(1000); 425 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 426 ATPHY_CDTS); 427 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 428 linkup++; 429 break; 430 } 431 } 432 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 433 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 434 if (linkup == 0) { 435 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_ADDR, 0); 437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 438 ATPHY_DBG_DATA, 0x124E); 439 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 440 ATPHY_DBG_ADDR, 1); 441 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_DATA); 443 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 444 ATPHY_DBG_DATA, reg | 0x03); 445 /* XXX */ 446 DELAY(1500 * 1000); 447 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 448 ATPHY_DBG_ADDR, 0); 449 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 450 ATPHY_DBG_DATA, 0x024E); 451 } 452 453 #undef ATPHY_DBG_ADDR 454 #undef ATPHY_DBG_DATA 455 #undef ATPHY_CDTC 456 #undef PHY_CDTC_ENB 457 #undef PHY_CDTC_POFF 458 #undef ATPHY_CDTS 459 #undef PHY_CDTS_STAT_OK 460 #undef PHY_CDTS_STAT_SHORT 461 #undef PHY_CDTS_STAT_OPEN 462 #undef PHY_CDTS_STAT_INVAL 463 #undef PHY_CDTS_STAT_MASK 464 } 465 466 static int 467 age_attach(device_t dev) 468 { 469 struct age_softc *sc; 470 struct ifnet *ifp; 471 uint16_t burst; 472 int error, i, msic, msixc, pmc; 473 474 error = 0; 475 sc = device_get_softc(dev); 476 sc->age_dev = dev; 477 478 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 479 MTX_DEF); 480 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 481 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 482 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 483 484 /* Map the device. */ 485 pci_enable_busmaster(dev); 486 sc->age_res_spec = age_res_spec_mem; 487 sc->age_irq_spec = age_irq_spec_legacy; 488 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 489 if (error != 0) { 490 device_printf(dev, "cannot allocate memory resources.\n"); 491 goto fail; 492 } 493 494 /* Set PHY address. */ 495 sc->age_phyaddr = AGE_PHY_ADDR; 496 497 /* Reset PHY. */ 498 age_phy_reset(sc); 499 500 /* Reset the ethernet controller. */ 501 age_reset(sc); 502 503 /* Get PCI and chip id/revision. */ 504 sc->age_rev = pci_get_revid(dev); 505 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 506 MASTER_CHIP_REV_SHIFT; 507 if (bootverbose) { 508 device_printf(dev, "PCI device revision : 0x%04x\n", 509 sc->age_rev); 510 device_printf(dev, "Chip id/revision : 0x%04x\n", 511 sc->age_chip_rev); 512 } 513 514 /* 515 * XXX 516 * Unintialized hardware returns an invalid chip id/revision 517 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 518 * unplugged cable results in putting hardware into automatic 519 * power down mode which in turn returns invalld chip revision. 520 */ 521 if (sc->age_chip_rev == 0xFFFF) { 522 device_printf(dev,"invalid chip revision : 0x%04x -- " 523 "not initialized?\n", sc->age_chip_rev); 524 error = ENXIO; 525 goto fail; 526 } 527 528 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 529 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 530 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 531 532 /* Allocate IRQ resources. */ 533 msixc = pci_msix_count(dev); 534 msic = pci_msi_count(dev); 535 if (bootverbose) { 536 device_printf(dev, "MSIX count : %d\n", msixc); 537 device_printf(dev, "MSI count : %d\n", msic); 538 } 539 540 /* Prefer MSIX over MSI. */ 541 if (msix_disable == 0 || msi_disable == 0) { 542 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 543 pci_alloc_msix(dev, &msixc) == 0) { 544 if (msic == AGE_MSIX_MESSAGES) { 545 device_printf(dev, "Using %d MSIX messages.\n", 546 msixc); 547 sc->age_flags |= AGE_FLAG_MSIX; 548 sc->age_irq_spec = age_irq_spec_msix; 549 } else 550 pci_release_msi(dev); 551 } 552 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 553 msic == AGE_MSI_MESSAGES && 554 pci_alloc_msi(dev, &msic) == 0) { 555 if (msic == AGE_MSI_MESSAGES) { 556 device_printf(dev, "Using %d MSI messages.\n", 557 msic); 558 sc->age_flags |= AGE_FLAG_MSI; 559 sc->age_irq_spec = age_irq_spec_msi; 560 } else 561 pci_release_msi(dev); 562 } 563 } 564 565 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 566 if (error != 0) { 567 device_printf(dev, "cannot allocate IRQ resources.\n"); 568 goto fail; 569 } 570 571 572 /* Get DMA parameters from PCIe device control register. */ 573 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 574 sc->age_flags |= AGE_FLAG_PCIE; 575 burst = pci_read_config(dev, i + 0x08, 2); 576 /* Max read request size. */ 577 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 578 DMA_CFG_RD_BURST_SHIFT; 579 /* Max payload size. */ 580 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 581 DMA_CFG_WR_BURST_SHIFT; 582 if (bootverbose) { 583 device_printf(dev, "Read request size : %d bytes.\n", 584 128 << ((burst >> 12) & 0x07)); 585 device_printf(dev, "TLP payload size : %d bytes.\n", 586 128 << ((burst >> 5) & 0x07)); 587 } 588 } else { 589 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 590 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 591 } 592 593 /* Create device sysctl node. */ 594 age_sysctl_node(sc); 595 596 if ((error = age_dma_alloc(sc) != 0)) 597 goto fail; 598 599 /* Load station address. */ 600 age_get_macaddr(sc); 601 602 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 603 if (ifp == NULL) { 604 device_printf(dev, "cannot allocate ifnet structure.\n"); 605 error = ENXIO; 606 goto fail; 607 } 608 609 ifp->if_softc = sc; 610 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 611 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 612 ifp->if_ioctl = age_ioctl; 613 ifp->if_start = age_start; 614 ifp->if_init = age_init; 615 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 616 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 617 IFQ_SET_READY(&ifp->if_snd); 618 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 619 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 620 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 621 sc->age_flags |= AGE_FLAG_PMCAP; 622 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 623 } 624 ifp->if_capenable = ifp->if_capabilities; 625 626 /* Set up MII bus. */ 627 if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 628 age_mediastatus)) != 0) { 629 device_printf(dev, "no PHY found!\n"); 630 goto fail; 631 } 632 633 ether_ifattach(ifp, sc->age_eaddr); 634 635 /* VLAN capability setup. */ 636 ifp->if_capabilities |= IFCAP_VLAN_MTU; 637 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 638 ifp->if_capenable = ifp->if_capabilities; 639 640 /* Tell the upper layer(s) we support long frames. */ 641 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 642 643 /* Create local taskq. */ 644 TASK_INIT(&sc->age_tx_task, 1, age_tx_task, ifp); 645 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 646 taskqueue_thread_enqueue, &sc->age_tq); 647 if (sc->age_tq == NULL) { 648 device_printf(dev, "could not create taskqueue.\n"); 649 ether_ifdetach(ifp); 650 error = ENXIO; 651 goto fail; 652 } 653 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 654 device_get_nameunit(sc->age_dev)); 655 656 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 657 msic = AGE_MSIX_MESSAGES; 658 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 659 msic = AGE_MSI_MESSAGES; 660 else 661 msic = 1; 662 for (i = 0; i < msic; i++) { 663 error = bus_setup_intr(dev, sc->age_irq[i], 664 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 665 &sc->age_intrhand[i]); 666 if (error != 0) 667 break; 668 } 669 if (error != 0) { 670 device_printf(dev, "could not set up interrupt handler.\n"); 671 taskqueue_free(sc->age_tq); 672 sc->age_tq = NULL; 673 ether_ifdetach(ifp); 674 goto fail; 675 } 676 677 fail: 678 if (error != 0) 679 age_detach(dev); 680 681 return (error); 682 } 683 684 static int 685 age_detach(device_t dev) 686 { 687 struct age_softc *sc; 688 struct ifnet *ifp; 689 int i, msic; 690 691 sc = device_get_softc(dev); 692 693 ifp = sc->age_ifp; 694 if (device_is_attached(dev)) { 695 AGE_LOCK(sc); 696 sc->age_flags |= AGE_FLAG_DETACH; 697 age_stop(sc); 698 AGE_UNLOCK(sc); 699 callout_drain(&sc->age_tick_ch); 700 taskqueue_drain(sc->age_tq, &sc->age_int_task); 701 taskqueue_drain(sc->age_tq, &sc->age_tx_task); 702 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 703 ether_ifdetach(ifp); 704 } 705 706 if (sc->age_tq != NULL) { 707 taskqueue_drain(sc->age_tq, &sc->age_int_task); 708 taskqueue_free(sc->age_tq); 709 sc->age_tq = NULL; 710 } 711 712 if (sc->age_miibus != NULL) { 713 device_delete_child(dev, sc->age_miibus); 714 sc->age_miibus = NULL; 715 } 716 bus_generic_detach(dev); 717 age_dma_free(sc); 718 719 if (ifp != NULL) { 720 if_free(ifp); 721 sc->age_ifp = NULL; 722 } 723 724 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 725 msic = AGE_MSIX_MESSAGES; 726 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 727 msic = AGE_MSI_MESSAGES; 728 else 729 msic = 1; 730 for (i = 0; i < msic; i++) { 731 if (sc->age_intrhand[i] != NULL) { 732 bus_teardown_intr(dev, sc->age_irq[i], 733 sc->age_intrhand[i]); 734 sc->age_intrhand[i] = NULL; 735 } 736 } 737 738 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 739 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 740 pci_release_msi(dev); 741 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 742 mtx_destroy(&sc->age_mtx); 743 744 return (0); 745 } 746 747 static void 748 age_sysctl_node(struct age_softc *sc) 749 { 750 int error; 751 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 754 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 755 "I", "Statistics"); 756 757 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 758 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 759 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 760 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 761 762 /* Pull in device tunables. */ 763 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 764 error = resource_int_value(device_get_name(sc->age_dev), 765 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 766 if (error == 0) { 767 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 768 sc->age_int_mod > AGE_IM_TIMER_MAX) { 769 device_printf(sc->age_dev, 770 "int_mod value out of range; using default: %d\n", 771 AGE_IM_TIMER_DEFAULT); 772 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 773 } 774 } 775 776 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 777 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 778 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 779 0, sysctl_hw_age_proc_limit, "I", 780 "max number of Rx events to process"); 781 782 /* Pull in device tunables. */ 783 sc->age_process_limit = AGE_PROC_DEFAULT; 784 error = resource_int_value(device_get_name(sc->age_dev), 785 device_get_unit(sc->age_dev), "process_limit", 786 &sc->age_process_limit); 787 if (error == 0) { 788 if (sc->age_process_limit < AGE_PROC_MIN || 789 sc->age_process_limit > AGE_PROC_MAX) { 790 device_printf(sc->age_dev, 791 "process_limit value out of range; " 792 "using default: %d\n", AGE_PROC_DEFAULT); 793 sc->age_process_limit = AGE_PROC_DEFAULT; 794 } 795 } 796 } 797 798 struct age_dmamap_arg { 799 bus_addr_t age_busaddr; 800 }; 801 802 static void 803 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 804 { 805 struct age_dmamap_arg *ctx; 806 807 if (error != 0) 808 return; 809 810 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 811 812 ctx = (struct age_dmamap_arg *)arg; 813 ctx->age_busaddr = segs[0].ds_addr; 814 } 815 816 /* 817 * Attansic L1 controller have single register to specify high 818 * address part of DMA blocks. So all descriptor structures and 819 * DMA memory blocks should have the same high address of given 820 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 821 */ 822 static int 823 age_check_boundary(struct age_softc *sc) 824 { 825 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 826 bus_addr_t cmb_block_end, smb_block_end; 827 828 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 829 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 830 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 831 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 832 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 833 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 834 835 if ((AGE_ADDR_HI(tx_ring_end) != 836 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 837 (AGE_ADDR_HI(rx_ring_end) != 838 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 839 (AGE_ADDR_HI(rr_ring_end) != 840 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 841 (AGE_ADDR_HI(cmb_block_end) != 842 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 843 (AGE_ADDR_HI(smb_block_end) != 844 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 845 return (EFBIG); 846 847 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 848 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 849 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 850 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 851 return (EFBIG); 852 853 return (0); 854 } 855 856 static int 857 age_dma_alloc(struct age_softc *sc) 858 { 859 struct age_txdesc *txd; 860 struct age_rxdesc *rxd; 861 bus_addr_t lowaddr; 862 struct age_dmamap_arg ctx; 863 int error, i; 864 865 lowaddr = BUS_SPACE_MAXADDR; 866 867 again: 868 /* Create parent ring/DMA block tag. */ 869 error = bus_dma_tag_create( 870 bus_get_dma_tag(sc->age_dev), /* parent */ 871 1, 0, /* alignment, boundary */ 872 lowaddr, /* lowaddr */ 873 BUS_SPACE_MAXADDR, /* highaddr */ 874 NULL, NULL, /* filter, filterarg */ 875 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 876 0, /* nsegments */ 877 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 878 0, /* flags */ 879 NULL, NULL, /* lockfunc, lockarg */ 880 &sc->age_cdata.age_parent_tag); 881 if (error != 0) { 882 device_printf(sc->age_dev, 883 "could not create parent DMA tag.\n"); 884 goto fail; 885 } 886 887 /* Create tag for Tx ring. */ 888 error = bus_dma_tag_create( 889 sc->age_cdata.age_parent_tag, /* parent */ 890 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 891 BUS_SPACE_MAXADDR, /* lowaddr */ 892 BUS_SPACE_MAXADDR, /* highaddr */ 893 NULL, NULL, /* filter, filterarg */ 894 AGE_TX_RING_SZ, /* maxsize */ 895 1, /* nsegments */ 896 AGE_TX_RING_SZ, /* maxsegsize */ 897 0, /* flags */ 898 NULL, NULL, /* lockfunc, lockarg */ 899 &sc->age_cdata.age_tx_ring_tag); 900 if (error != 0) { 901 device_printf(sc->age_dev, 902 "could not create Tx ring DMA tag.\n"); 903 goto fail; 904 } 905 906 /* Create tag for Rx ring. */ 907 error = bus_dma_tag_create( 908 sc->age_cdata.age_parent_tag, /* parent */ 909 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 910 BUS_SPACE_MAXADDR, /* lowaddr */ 911 BUS_SPACE_MAXADDR, /* highaddr */ 912 NULL, NULL, /* filter, filterarg */ 913 AGE_RX_RING_SZ, /* maxsize */ 914 1, /* nsegments */ 915 AGE_RX_RING_SZ, /* maxsegsize */ 916 0, /* flags */ 917 NULL, NULL, /* lockfunc, lockarg */ 918 &sc->age_cdata.age_rx_ring_tag); 919 if (error != 0) { 920 device_printf(sc->age_dev, 921 "could not create Rx ring DMA tag.\n"); 922 goto fail; 923 } 924 925 /* Create tag for Rx return ring. */ 926 error = bus_dma_tag_create( 927 sc->age_cdata.age_parent_tag, /* parent */ 928 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 929 BUS_SPACE_MAXADDR, /* lowaddr */ 930 BUS_SPACE_MAXADDR, /* highaddr */ 931 NULL, NULL, /* filter, filterarg */ 932 AGE_RR_RING_SZ, /* maxsize */ 933 1, /* nsegments */ 934 AGE_RR_RING_SZ, /* maxsegsize */ 935 0, /* flags */ 936 NULL, NULL, /* lockfunc, lockarg */ 937 &sc->age_cdata.age_rr_ring_tag); 938 if (error != 0) { 939 device_printf(sc->age_dev, 940 "could not create Rx return ring DMA tag.\n"); 941 goto fail; 942 } 943 944 /* Create tag for coalesing message block. */ 945 error = bus_dma_tag_create( 946 sc->age_cdata.age_parent_tag, /* parent */ 947 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 948 BUS_SPACE_MAXADDR, /* lowaddr */ 949 BUS_SPACE_MAXADDR, /* highaddr */ 950 NULL, NULL, /* filter, filterarg */ 951 AGE_CMB_BLOCK_SZ, /* maxsize */ 952 1, /* nsegments */ 953 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 954 0, /* flags */ 955 NULL, NULL, /* lockfunc, lockarg */ 956 &sc->age_cdata.age_cmb_block_tag); 957 if (error != 0) { 958 device_printf(sc->age_dev, 959 "could not create CMB DMA tag.\n"); 960 goto fail; 961 } 962 963 /* Create tag for statistics message block. */ 964 error = bus_dma_tag_create( 965 sc->age_cdata.age_parent_tag, /* parent */ 966 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 967 BUS_SPACE_MAXADDR, /* lowaddr */ 968 BUS_SPACE_MAXADDR, /* highaddr */ 969 NULL, NULL, /* filter, filterarg */ 970 AGE_SMB_BLOCK_SZ, /* maxsize */ 971 1, /* nsegments */ 972 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 973 0, /* flags */ 974 NULL, NULL, /* lockfunc, lockarg */ 975 &sc->age_cdata.age_smb_block_tag); 976 if (error != 0) { 977 device_printf(sc->age_dev, 978 "could not create SMB DMA tag.\n"); 979 goto fail; 980 } 981 982 /* Allocate DMA'able memory and load the DMA map. */ 983 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 984 (void **)&sc->age_rdata.age_tx_ring, 985 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 986 &sc->age_cdata.age_tx_ring_map); 987 if (error != 0) { 988 device_printf(sc->age_dev, 989 "could not allocate DMA'able memory for Tx ring.\n"); 990 goto fail; 991 } 992 ctx.age_busaddr = 0; 993 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 994 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 995 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 996 if (error != 0 || ctx.age_busaddr == 0) { 997 device_printf(sc->age_dev, 998 "could not load DMA'able memory for Tx ring.\n"); 999 goto fail; 1000 } 1001 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 1002 /* Rx ring */ 1003 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1004 (void **)&sc->age_rdata.age_rx_ring, 1005 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1006 &sc->age_cdata.age_rx_ring_map); 1007 if (error != 0) { 1008 device_printf(sc->age_dev, 1009 "could not allocate DMA'able memory for Rx ring.\n"); 1010 goto fail; 1011 } 1012 ctx.age_busaddr = 0; 1013 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1014 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1015 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1016 if (error != 0 || ctx.age_busaddr == 0) { 1017 device_printf(sc->age_dev, 1018 "could not load DMA'able memory for Rx ring.\n"); 1019 goto fail; 1020 } 1021 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1022 /* Rx return ring */ 1023 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1024 (void **)&sc->age_rdata.age_rr_ring, 1025 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1026 &sc->age_cdata.age_rr_ring_map); 1027 if (error != 0) { 1028 device_printf(sc->age_dev, 1029 "could not allocate DMA'able memory for Rx return ring.\n"); 1030 goto fail; 1031 } 1032 ctx.age_busaddr = 0; 1033 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1034 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1035 AGE_RR_RING_SZ, age_dmamap_cb, 1036 &ctx, 0); 1037 if (error != 0 || ctx.age_busaddr == 0) { 1038 device_printf(sc->age_dev, 1039 "could not load DMA'able memory for Rx return ring.\n"); 1040 goto fail; 1041 } 1042 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1043 /* CMB block */ 1044 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1045 (void **)&sc->age_rdata.age_cmb_block, 1046 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1047 &sc->age_cdata.age_cmb_block_map); 1048 if (error != 0) { 1049 device_printf(sc->age_dev, 1050 "could not allocate DMA'able memory for CMB block.\n"); 1051 goto fail; 1052 } 1053 ctx.age_busaddr = 0; 1054 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1055 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1056 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1057 if (error != 0 || ctx.age_busaddr == 0) { 1058 device_printf(sc->age_dev, 1059 "could not load DMA'able memory for CMB block.\n"); 1060 goto fail; 1061 } 1062 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1063 /* SMB block */ 1064 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1065 (void **)&sc->age_rdata.age_smb_block, 1066 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1067 &sc->age_cdata.age_smb_block_map); 1068 if (error != 0) { 1069 device_printf(sc->age_dev, 1070 "could not allocate DMA'able memory for SMB block.\n"); 1071 goto fail; 1072 } 1073 ctx.age_busaddr = 0; 1074 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1075 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1076 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1077 if (error != 0 || ctx.age_busaddr == 0) { 1078 device_printf(sc->age_dev, 1079 "could not load DMA'able memory for SMB block.\n"); 1080 goto fail; 1081 } 1082 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1083 1084 /* 1085 * All ring buffer and DMA blocks should have the same 1086 * high address part of 64bit DMA address space. 1087 */ 1088 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1089 (error = age_check_boundary(sc)) != 0) { 1090 device_printf(sc->age_dev, "4GB boundary crossed, " 1091 "switching to 32bit DMA addressing mode.\n"); 1092 age_dma_free(sc); 1093 /* Limit DMA address space to 32bit and try again. */ 1094 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1095 goto again; 1096 } 1097 1098 /* 1099 * Create Tx/Rx buffer parent tag. 1100 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1101 * so it needs separate parent DMA tag. 1102 */ 1103 error = bus_dma_tag_create( 1104 bus_get_dma_tag(sc->age_dev), /* parent */ 1105 1, 0, /* alignment, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1110 0, /* nsegments */ 1111 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->age_cdata.age_buffer_tag); 1115 if (error != 0) { 1116 device_printf(sc->age_dev, 1117 "could not create parent buffer DMA tag.\n"); 1118 goto fail; 1119 } 1120 1121 /* Create tag for Tx buffers. */ 1122 error = bus_dma_tag_create( 1123 sc->age_cdata.age_buffer_tag, /* parent */ 1124 1, 0, /* alignment, boundary */ 1125 BUS_SPACE_MAXADDR, /* lowaddr */ 1126 BUS_SPACE_MAXADDR, /* highaddr */ 1127 NULL, NULL, /* filter, filterarg */ 1128 AGE_TSO_MAXSIZE, /* maxsize */ 1129 AGE_MAXTXSEGS, /* nsegments */ 1130 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1131 0, /* flags */ 1132 NULL, NULL, /* lockfunc, lockarg */ 1133 &sc->age_cdata.age_tx_tag); 1134 if (error != 0) { 1135 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1136 goto fail; 1137 } 1138 1139 /* Create tag for Rx buffers. */ 1140 error = bus_dma_tag_create( 1141 sc->age_cdata.age_buffer_tag, /* parent */ 1142 1, 0, /* alignment, boundary */ 1143 BUS_SPACE_MAXADDR, /* lowaddr */ 1144 BUS_SPACE_MAXADDR, /* highaddr */ 1145 NULL, NULL, /* filter, filterarg */ 1146 MCLBYTES, /* maxsize */ 1147 1, /* nsegments */ 1148 MCLBYTES, /* maxsegsize */ 1149 0, /* flags */ 1150 NULL, NULL, /* lockfunc, lockarg */ 1151 &sc->age_cdata.age_rx_tag); 1152 if (error != 0) { 1153 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1154 goto fail; 1155 } 1156 1157 /* Create DMA maps for Tx buffers. */ 1158 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1159 txd = &sc->age_cdata.age_txdesc[i]; 1160 txd->tx_m = NULL; 1161 txd->tx_dmamap = NULL; 1162 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1163 &txd->tx_dmamap); 1164 if (error != 0) { 1165 device_printf(sc->age_dev, 1166 "could not create Tx dmamap.\n"); 1167 goto fail; 1168 } 1169 } 1170 /* Create DMA maps for Rx buffers. */ 1171 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1172 &sc->age_cdata.age_rx_sparemap)) != 0) { 1173 device_printf(sc->age_dev, 1174 "could not create spare Rx dmamap.\n"); 1175 goto fail; 1176 } 1177 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1178 rxd = &sc->age_cdata.age_rxdesc[i]; 1179 rxd->rx_m = NULL; 1180 rxd->rx_dmamap = NULL; 1181 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1182 &rxd->rx_dmamap); 1183 if (error != 0) { 1184 device_printf(sc->age_dev, 1185 "could not create Rx dmamap.\n"); 1186 goto fail; 1187 } 1188 } 1189 1190 fail: 1191 return (error); 1192 } 1193 1194 static void 1195 age_dma_free(struct age_softc *sc) 1196 { 1197 struct age_txdesc *txd; 1198 struct age_rxdesc *rxd; 1199 int i; 1200 1201 /* Tx buffers */ 1202 if (sc->age_cdata.age_tx_tag != NULL) { 1203 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1204 txd = &sc->age_cdata.age_txdesc[i]; 1205 if (txd->tx_dmamap != NULL) { 1206 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1207 txd->tx_dmamap); 1208 txd->tx_dmamap = NULL; 1209 } 1210 } 1211 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1212 sc->age_cdata.age_tx_tag = NULL; 1213 } 1214 /* Rx buffers */ 1215 if (sc->age_cdata.age_rx_tag != NULL) { 1216 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1217 rxd = &sc->age_cdata.age_rxdesc[i]; 1218 if (rxd->rx_dmamap != NULL) { 1219 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1220 rxd->rx_dmamap); 1221 rxd->rx_dmamap = NULL; 1222 } 1223 } 1224 if (sc->age_cdata.age_rx_sparemap != NULL) { 1225 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1226 sc->age_cdata.age_rx_sparemap); 1227 sc->age_cdata.age_rx_sparemap = NULL; 1228 } 1229 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1230 sc->age_cdata.age_rx_tag = NULL; 1231 } 1232 /* Tx ring. */ 1233 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1234 if (sc->age_cdata.age_tx_ring_map != NULL) 1235 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1236 sc->age_cdata.age_tx_ring_map); 1237 if (sc->age_cdata.age_tx_ring_map != NULL && 1238 sc->age_rdata.age_tx_ring != NULL) 1239 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1240 sc->age_rdata.age_tx_ring, 1241 sc->age_cdata.age_tx_ring_map); 1242 sc->age_rdata.age_tx_ring = NULL; 1243 sc->age_cdata.age_tx_ring_map = NULL; 1244 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1245 sc->age_cdata.age_tx_ring_tag = NULL; 1246 } 1247 /* Rx ring. */ 1248 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1249 if (sc->age_cdata.age_rx_ring_map != NULL) 1250 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1251 sc->age_cdata.age_rx_ring_map); 1252 if (sc->age_cdata.age_rx_ring_map != NULL && 1253 sc->age_rdata.age_rx_ring != NULL) 1254 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1255 sc->age_rdata.age_rx_ring, 1256 sc->age_cdata.age_rx_ring_map); 1257 sc->age_rdata.age_rx_ring = NULL; 1258 sc->age_cdata.age_rx_ring_map = NULL; 1259 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1260 sc->age_cdata.age_rx_ring_tag = NULL; 1261 } 1262 /* Rx return ring. */ 1263 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1264 if (sc->age_cdata.age_rr_ring_map != NULL) 1265 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1266 sc->age_cdata.age_rr_ring_map); 1267 if (sc->age_cdata.age_rr_ring_map != NULL && 1268 sc->age_rdata.age_rr_ring != NULL) 1269 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1270 sc->age_rdata.age_rr_ring, 1271 sc->age_cdata.age_rr_ring_map); 1272 sc->age_rdata.age_rr_ring = NULL; 1273 sc->age_cdata.age_rr_ring_map = NULL; 1274 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1275 sc->age_cdata.age_rr_ring_tag = NULL; 1276 } 1277 /* CMB block */ 1278 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1279 if (sc->age_cdata.age_cmb_block_map != NULL) 1280 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1281 sc->age_cdata.age_cmb_block_map); 1282 if (sc->age_cdata.age_cmb_block_map != NULL && 1283 sc->age_rdata.age_cmb_block != NULL) 1284 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1285 sc->age_rdata.age_cmb_block, 1286 sc->age_cdata.age_cmb_block_map); 1287 sc->age_rdata.age_cmb_block = NULL; 1288 sc->age_cdata.age_cmb_block_map = NULL; 1289 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1290 sc->age_cdata.age_cmb_block_tag = NULL; 1291 } 1292 /* SMB block */ 1293 if (sc->age_cdata.age_smb_block_tag != NULL) { 1294 if (sc->age_cdata.age_smb_block_map != NULL) 1295 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1296 sc->age_cdata.age_smb_block_map); 1297 if (sc->age_cdata.age_smb_block_map != NULL && 1298 sc->age_rdata.age_smb_block != NULL) 1299 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1300 sc->age_rdata.age_smb_block, 1301 sc->age_cdata.age_smb_block_map); 1302 sc->age_rdata.age_smb_block = NULL; 1303 sc->age_cdata.age_smb_block_map = NULL; 1304 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1305 sc->age_cdata.age_smb_block_tag = NULL; 1306 } 1307 1308 if (sc->age_cdata.age_buffer_tag != NULL) { 1309 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1310 sc->age_cdata.age_buffer_tag = NULL; 1311 } 1312 if (sc->age_cdata.age_parent_tag != NULL) { 1313 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1314 sc->age_cdata.age_parent_tag = NULL; 1315 } 1316 } 1317 1318 /* 1319 * Make sure the interface is stopped at reboot time. 1320 */ 1321 static int 1322 age_shutdown(device_t dev) 1323 { 1324 1325 return (age_suspend(dev)); 1326 } 1327 1328 static void 1329 age_setwol(struct age_softc *sc) 1330 { 1331 struct ifnet *ifp; 1332 struct mii_data *mii; 1333 uint32_t reg, pmcs; 1334 uint16_t pmstat; 1335 int aneg, i, pmc; 1336 1337 AGE_LOCK_ASSERT(sc); 1338 1339 if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1340 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1341 /* 1342 * No PME capability, PHY power down. 1343 * XXX 1344 * Due to an unknown reason powering down PHY resulted 1345 * in unexpected results such as inaccessbility of 1346 * hardware of freshly rebooted system. Disable 1347 * powering down PHY until I got more information for 1348 * Attansic/Atheros PHY hardwares. 1349 */ 1350 #ifdef notyet 1351 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1352 MII_BMCR, BMCR_PDOWN); 1353 #endif 1354 return; 1355 } 1356 1357 ifp = sc->age_ifp; 1358 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1359 /* 1360 * Note, this driver resets the link speed to 10/100Mbps with 1361 * auto-negotiation but we don't know whether that operation 1362 * would succeed or not as it have no control after powering 1363 * off. If the renegotiation fail WOL may not work. Running 1364 * at 1Gbps will draw more power than 375mA at 3.3V which is 1365 * specified in PCI specification and that would result in 1366 * complete shutdowning power to ethernet controller. 1367 * 1368 * TODO 1369 * Save current negotiated media speed/duplex/flow-control 1370 * to softc and restore the same link again after resuming. 1371 * PHY handling such as power down/resetting to 100Mbps 1372 * may be better handled in suspend method in phy driver. 1373 */ 1374 mii = device_get_softc(sc->age_miibus); 1375 mii_pollstat(mii); 1376 aneg = 0; 1377 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1378 switch IFM_SUBTYPE(mii->mii_media_active) { 1379 case IFM_10_T: 1380 case IFM_100_TX: 1381 goto got_link; 1382 case IFM_1000_T: 1383 aneg++; 1384 default: 1385 break; 1386 } 1387 } 1388 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1389 MII_100T2CR, 0); 1390 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1391 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1392 ANAR_10 | ANAR_CSMA); 1393 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1394 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1395 DELAY(1000); 1396 if (aneg != 0) { 1397 /* Poll link state until age(4) get a 10/100 link. */ 1398 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1399 mii_pollstat(mii); 1400 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1401 switch (IFM_SUBTYPE( 1402 mii->mii_media_active)) { 1403 case IFM_10_T: 1404 case IFM_100_TX: 1405 age_mac_config(sc); 1406 goto got_link; 1407 default: 1408 break; 1409 } 1410 } 1411 AGE_UNLOCK(sc); 1412 pause("agelnk", hz); 1413 AGE_LOCK(sc); 1414 } 1415 if (i == MII_ANEGTICKS_GIGE) 1416 device_printf(sc->age_dev, 1417 "establishing link failed, " 1418 "WOL may not work!"); 1419 } 1420 /* 1421 * No link, force MAC to have 100Mbps, full-duplex link. 1422 * This is the last resort and may/may not work. 1423 */ 1424 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1425 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1426 age_mac_config(sc); 1427 } 1428 1429 got_link: 1430 pmcs = 0; 1431 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1432 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1433 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1434 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1435 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1436 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1437 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1438 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1439 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1440 reg |= MAC_CFG_RX_ENB; 1441 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1442 } 1443 1444 /* Request PME. */ 1445 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1446 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1447 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1448 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1449 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1450 #ifdef notyet 1451 /* See above for powering down PHY issues. */ 1452 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1453 /* No WOL, PHY power down. */ 1454 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1455 MII_BMCR, BMCR_PDOWN); 1456 } 1457 #endif 1458 } 1459 1460 static int 1461 age_suspend(device_t dev) 1462 { 1463 struct age_softc *sc; 1464 1465 sc = device_get_softc(dev); 1466 1467 AGE_LOCK(sc); 1468 age_stop(sc); 1469 age_setwol(sc); 1470 AGE_UNLOCK(sc); 1471 1472 return (0); 1473 } 1474 1475 static int 1476 age_resume(device_t dev) 1477 { 1478 struct age_softc *sc; 1479 struct ifnet *ifp; 1480 uint16_t cmd; 1481 1482 sc = device_get_softc(dev); 1483 1484 AGE_LOCK(sc); 1485 /* 1486 * Clear INTx emulation disable for hardwares that 1487 * is set in resume event. From Linux. 1488 */ 1489 cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); 1490 if ((cmd & 0x0400) != 0) { 1491 cmd &= ~0x0400; 1492 pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); 1493 } 1494 AGE_UNLOCK(sc); 1495 age_phy_reset(sc); 1496 AGE_LOCK(sc); 1497 ifp = sc->age_ifp; 1498 if ((ifp->if_flags & IFF_UP) != 0) 1499 age_init_locked(sc); 1500 1501 AGE_UNLOCK(sc); 1502 1503 return (0); 1504 } 1505 1506 static int 1507 age_encap(struct age_softc *sc, struct mbuf **m_head) 1508 { 1509 struct age_txdesc *txd, *txd_last; 1510 struct tx_desc *desc; 1511 struct mbuf *m; 1512 struct ip *ip; 1513 struct tcphdr *tcp; 1514 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1515 bus_dmamap_t map; 1516 uint32_t cflags, ip_off, poff, vtag; 1517 int error, i, nsegs, prod, si; 1518 1519 AGE_LOCK_ASSERT(sc); 1520 1521 M_ASSERTPKTHDR((*m_head)); 1522 1523 m = *m_head; 1524 ip = NULL; 1525 tcp = NULL; 1526 cflags = vtag = 0; 1527 ip_off = poff = 0; 1528 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1529 /* 1530 * L1 requires offset of TCP/UDP payload in its Tx 1531 * descriptor to perform hardware Tx checksum offload. 1532 * Additionally, TSO requires IP/TCP header size and 1533 * modification of IP/TCP header in order to make TSO 1534 * engine work. This kind of operation takes many CPU 1535 * cycles on FreeBSD so fast host CPU is needed to get 1536 * smooth TSO performance. 1537 */ 1538 struct ether_header *eh; 1539 1540 if (M_WRITABLE(m) == 0) { 1541 /* Get a writable copy. */ 1542 m = m_dup(*m_head, M_DONTWAIT); 1543 /* Release original mbufs. */ 1544 m_freem(*m_head); 1545 if (m == NULL) { 1546 *m_head = NULL; 1547 return (ENOBUFS); 1548 } 1549 *m_head = m; 1550 } 1551 ip_off = sizeof(struct ether_header); 1552 m = m_pullup(m, ip_off); 1553 if (m == NULL) { 1554 *m_head = NULL; 1555 return (ENOBUFS); 1556 } 1557 eh = mtod(m, struct ether_header *); 1558 /* 1559 * Check if hardware VLAN insertion is off. 1560 * Additional check for LLC/SNAP frame? 1561 */ 1562 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1563 ip_off = sizeof(struct ether_vlan_header); 1564 m = m_pullup(m, ip_off); 1565 if (m == NULL) { 1566 *m_head = NULL; 1567 return (ENOBUFS); 1568 } 1569 } 1570 m = m_pullup(m, ip_off + sizeof(struct ip)); 1571 if (m == NULL) { 1572 *m_head = NULL; 1573 return (ENOBUFS); 1574 } 1575 ip = (struct ip *)(mtod(m, char *) + ip_off); 1576 poff = ip_off + (ip->ip_hl << 2); 1577 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1578 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1579 if (m == NULL) { 1580 *m_head = NULL; 1581 return (ENOBUFS); 1582 } 1583 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1584 /* 1585 * L1 requires IP/TCP header size and offset as 1586 * well as TCP pseudo checksum which complicates 1587 * TSO configuration. I guess this comes from the 1588 * adherence to Microsoft NDIS Large Send 1589 * specification which requires insertion of 1590 * pseudo checksum by upper stack. The pseudo 1591 * checksum that NDIS refers to doesn't include 1592 * TCP payload length so age(4) should recompute 1593 * the pseudo checksum here. Hopefully this wouldn't 1594 * be much burden on modern CPUs. 1595 * Reset IP checksum and recompute TCP pseudo 1596 * checksum as NDIS specification said. 1597 */ 1598 ip->ip_sum = 0; 1599 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1600 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1601 ip->ip_dst.s_addr, 1602 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1603 else 1604 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1605 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1606 } 1607 *m_head = m; 1608 } 1609 1610 si = prod = sc->age_cdata.age_tx_prod; 1611 txd = &sc->age_cdata.age_txdesc[prod]; 1612 txd_last = txd; 1613 map = txd->tx_dmamap; 1614 1615 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1616 *m_head, txsegs, &nsegs, 0); 1617 if (error == EFBIG) { 1618 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1619 if (m == NULL) { 1620 m_freem(*m_head); 1621 *m_head = NULL; 1622 return (ENOMEM); 1623 } 1624 *m_head = m; 1625 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1626 *m_head, txsegs, &nsegs, 0); 1627 if (error != 0) { 1628 m_freem(*m_head); 1629 *m_head = NULL; 1630 return (error); 1631 } 1632 } else if (error != 0) 1633 return (error); 1634 if (nsegs == 0) { 1635 m_freem(*m_head); 1636 *m_head = NULL; 1637 return (EIO); 1638 } 1639 1640 /* Check descriptor overrun. */ 1641 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1642 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1643 return (ENOBUFS); 1644 } 1645 1646 m = *m_head; 1647 /* Configure Tx IP/TCP/UDP checksum offload. */ 1648 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1649 cflags |= AGE_TD_CSUM; 1650 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1651 cflags |= AGE_TD_TCPCSUM; 1652 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1653 cflags |= AGE_TD_UDPCSUM; 1654 /* Set checksum start offset. */ 1655 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1656 /* Set checksum insertion position of TCP/UDP. */ 1657 cflags |= ((poff + m->m_pkthdr.csum_data) << 1658 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1659 } 1660 1661 /* Configure TSO. */ 1662 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1663 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1664 /* Not TSO but IP/TCP checksum offload. */ 1665 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1666 /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1667 m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1668 } else { 1669 /* Request TSO and set MSS. */ 1670 cflags |= AGE_TD_TSO_IPV4; 1671 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1672 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1673 AGE_TD_TSO_MSS_SHIFT); 1674 } 1675 /* Set IP/TCP header size. */ 1676 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1677 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1678 } 1679 1680 /* Configure VLAN hardware tag insertion. */ 1681 if ((m->m_flags & M_VLANTAG) != 0) { 1682 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1683 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1684 cflags |= AGE_TD_INSERT_VLAN_TAG; 1685 } 1686 1687 desc = NULL; 1688 for (i = 0; i < nsegs; i++) { 1689 desc = &sc->age_rdata.age_tx_ring[prod]; 1690 desc->addr = htole64(txsegs[i].ds_addr); 1691 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1692 desc->flags = htole32(cflags); 1693 sc->age_cdata.age_tx_cnt++; 1694 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1695 } 1696 /* Update producer index. */ 1697 sc->age_cdata.age_tx_prod = prod; 1698 1699 /* Set EOP on the last descriptor. */ 1700 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1701 desc = &sc->age_rdata.age_tx_ring[prod]; 1702 desc->flags |= htole32(AGE_TD_EOP); 1703 1704 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1705 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1706 desc = &sc->age_rdata.age_tx_ring[si]; 1707 desc->flags |= htole32(AGE_TD_TSO_HDR); 1708 } 1709 1710 /* Swap dmamap of the first and the last. */ 1711 txd = &sc->age_cdata.age_txdesc[prod]; 1712 map = txd_last->tx_dmamap; 1713 txd_last->tx_dmamap = txd->tx_dmamap; 1714 txd->tx_dmamap = map; 1715 txd->tx_m = m; 1716 1717 /* Sync descriptors. */ 1718 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1719 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1720 sc->age_cdata.age_tx_ring_map, 1721 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1722 1723 return (0); 1724 } 1725 1726 static void 1727 age_tx_task(void *arg, int pending) 1728 { 1729 struct ifnet *ifp; 1730 1731 ifp = (struct ifnet *)arg; 1732 age_start(ifp); 1733 } 1734 1735 static void 1736 age_start(struct ifnet *ifp) 1737 { 1738 struct age_softc *sc; 1739 struct mbuf *m_head; 1740 int enq; 1741 1742 sc = ifp->if_softc; 1743 1744 AGE_LOCK(sc); 1745 1746 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1747 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) { 1748 AGE_UNLOCK(sc); 1749 return; 1750 } 1751 1752 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1753 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1754 if (m_head == NULL) 1755 break; 1756 /* 1757 * Pack the data into the transmit ring. If we 1758 * don't have room, set the OACTIVE flag and wait 1759 * for the NIC to drain the ring. 1760 */ 1761 if (age_encap(sc, &m_head)) { 1762 if (m_head == NULL) 1763 break; 1764 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1765 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1766 break; 1767 } 1768 1769 enq++; 1770 /* 1771 * If there's a BPF listener, bounce a copy of this frame 1772 * to him. 1773 */ 1774 ETHER_BPF_MTAP(ifp, m_head); 1775 } 1776 1777 if (enq > 0) { 1778 /* Update mbox. */ 1779 AGE_COMMIT_MBOX(sc); 1780 /* Set a timeout in case the chip goes out to lunch. */ 1781 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1782 } 1783 1784 AGE_UNLOCK(sc); 1785 } 1786 1787 static void 1788 age_watchdog(struct age_softc *sc) 1789 { 1790 struct ifnet *ifp; 1791 1792 AGE_LOCK_ASSERT(sc); 1793 1794 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1795 return; 1796 1797 ifp = sc->age_ifp; 1798 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1799 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1800 ifp->if_oerrors++; 1801 age_init_locked(sc); 1802 return; 1803 } 1804 if (sc->age_cdata.age_tx_cnt == 0) { 1805 if_printf(sc->age_ifp, 1806 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1807 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1808 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1809 return; 1810 } 1811 if_printf(sc->age_ifp, "watchdog timeout\n"); 1812 ifp->if_oerrors++; 1813 age_init_locked(sc); 1814 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1815 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 1816 } 1817 1818 static int 1819 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1820 { 1821 struct age_softc *sc; 1822 struct ifreq *ifr; 1823 struct mii_data *mii; 1824 uint32_t reg; 1825 int error, mask; 1826 1827 sc = ifp->if_softc; 1828 ifr = (struct ifreq *)data; 1829 error = 0; 1830 switch (cmd) { 1831 case SIOCSIFMTU: 1832 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1833 error = EINVAL; 1834 else if (ifp->if_mtu != ifr->ifr_mtu) { 1835 AGE_LOCK(sc); 1836 ifp->if_mtu = ifr->ifr_mtu; 1837 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1838 age_init_locked(sc); 1839 AGE_UNLOCK(sc); 1840 } 1841 break; 1842 case SIOCSIFFLAGS: 1843 AGE_LOCK(sc); 1844 if ((ifp->if_flags & IFF_UP) != 0) { 1845 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1846 if (((ifp->if_flags ^ sc->age_if_flags) 1847 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1848 age_rxfilter(sc); 1849 } else { 1850 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1851 age_init_locked(sc); 1852 } 1853 } else { 1854 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1855 age_stop(sc); 1856 } 1857 sc->age_if_flags = ifp->if_flags; 1858 AGE_UNLOCK(sc); 1859 break; 1860 case SIOCADDMULTI: 1861 case SIOCDELMULTI: 1862 AGE_LOCK(sc); 1863 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1864 age_rxfilter(sc); 1865 AGE_UNLOCK(sc); 1866 break; 1867 case SIOCSIFMEDIA: 1868 case SIOCGIFMEDIA: 1869 mii = device_get_softc(sc->age_miibus); 1870 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1871 break; 1872 case SIOCSIFCAP: 1873 AGE_LOCK(sc); 1874 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1875 if ((mask & IFCAP_TXCSUM) != 0 && 1876 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1877 ifp->if_capenable ^= IFCAP_TXCSUM; 1878 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1879 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1880 else 1881 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1882 } 1883 if ((mask & IFCAP_RXCSUM) != 0 && 1884 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1885 ifp->if_capenable ^= IFCAP_RXCSUM; 1886 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1887 reg &= ~MAC_CFG_RXCSUM_ENB; 1888 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1889 reg |= MAC_CFG_RXCSUM_ENB; 1890 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1891 } 1892 if ((mask & IFCAP_TSO4) != 0 && 1893 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1894 ifp->if_capenable ^= IFCAP_TSO4; 1895 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1896 ifp->if_hwassist |= CSUM_TSO; 1897 else 1898 ifp->if_hwassist &= ~CSUM_TSO; 1899 } 1900 1901 if ((mask & IFCAP_WOL_MCAST) != 0 && 1902 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1903 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1904 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1905 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1906 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1907 1908 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1909 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1910 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1911 age_rxvlan(sc); 1912 } 1913 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1914 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1915 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1916 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1917 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1918 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1919 /* 1920 * VLAN hardware tagging is required to do checksum 1921 * offload or TSO on VLAN interface. Checksum offload 1922 * on VLAN interface also requires hardware assistance 1923 * of parent interface. 1924 */ 1925 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 1926 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 1927 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1928 ifp->if_capenable &= 1929 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1930 AGE_UNLOCK(sc); 1931 VLAN_CAPABILITIES(ifp); 1932 break; 1933 default: 1934 error = ether_ioctl(ifp, cmd, data); 1935 break; 1936 } 1937 1938 return (error); 1939 } 1940 1941 static void 1942 age_mac_config(struct age_softc *sc) 1943 { 1944 struct mii_data *mii; 1945 uint32_t reg; 1946 1947 AGE_LOCK_ASSERT(sc); 1948 1949 mii = device_get_softc(sc->age_miibus); 1950 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1951 reg &= ~MAC_CFG_FULL_DUPLEX; 1952 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1953 reg &= ~MAC_CFG_SPEED_MASK; 1954 /* Reprogram MAC with resolved speed/duplex. */ 1955 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1956 case IFM_10_T: 1957 case IFM_100_TX: 1958 reg |= MAC_CFG_SPEED_10_100; 1959 break; 1960 case IFM_1000_T: 1961 reg |= MAC_CFG_SPEED_1000; 1962 break; 1963 } 1964 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1965 reg |= MAC_CFG_FULL_DUPLEX; 1966 #ifdef notyet 1967 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1968 reg |= MAC_CFG_TX_FC; 1969 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1970 reg |= MAC_CFG_RX_FC; 1971 #endif 1972 } 1973 1974 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1975 } 1976 1977 static void 1978 age_link_task(void *arg, int pending) 1979 { 1980 struct age_softc *sc; 1981 struct mii_data *mii; 1982 struct ifnet *ifp; 1983 uint32_t reg; 1984 1985 sc = (struct age_softc *)arg; 1986 1987 AGE_LOCK(sc); 1988 mii = device_get_softc(sc->age_miibus); 1989 ifp = sc->age_ifp; 1990 if (mii == NULL || ifp == NULL || 1991 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1992 AGE_UNLOCK(sc); 1993 return; 1994 } 1995 1996 sc->age_flags &= ~AGE_FLAG_LINK; 1997 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1998 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1999 case IFM_10_T: 2000 case IFM_100_TX: 2001 case IFM_1000_T: 2002 sc->age_flags |= AGE_FLAG_LINK; 2003 break; 2004 default: 2005 break; 2006 } 2007 } 2008 2009 /* Stop Rx/Tx MACs. */ 2010 age_stop_rxmac(sc); 2011 age_stop_txmac(sc); 2012 2013 /* Program MACs with resolved speed/duplex/flow-control. */ 2014 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2015 age_mac_config(sc); 2016 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2017 /* Restart DMA engine and Tx/Rx MAC. */ 2018 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2019 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2020 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2021 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2022 } 2023 2024 AGE_UNLOCK(sc); 2025 } 2026 2027 static void 2028 age_stats_update(struct age_softc *sc) 2029 { 2030 struct age_stats *stat; 2031 struct smb *smb; 2032 struct ifnet *ifp; 2033 2034 AGE_LOCK_ASSERT(sc); 2035 2036 stat = &sc->age_stat; 2037 2038 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2039 sc->age_cdata.age_smb_block_map, 2040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2041 2042 smb = sc->age_rdata.age_smb_block; 2043 if (smb->updated == 0) 2044 return; 2045 2046 ifp = sc->age_ifp; 2047 /* Rx stats. */ 2048 stat->rx_frames += smb->rx_frames; 2049 stat->rx_bcast_frames += smb->rx_bcast_frames; 2050 stat->rx_mcast_frames += smb->rx_mcast_frames; 2051 stat->rx_pause_frames += smb->rx_pause_frames; 2052 stat->rx_control_frames += smb->rx_control_frames; 2053 stat->rx_crcerrs += smb->rx_crcerrs; 2054 stat->rx_lenerrs += smb->rx_lenerrs; 2055 stat->rx_bytes += smb->rx_bytes; 2056 stat->rx_runts += smb->rx_runts; 2057 stat->rx_fragments += smb->rx_fragments; 2058 stat->rx_pkts_64 += smb->rx_pkts_64; 2059 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2060 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2061 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2062 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2063 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2064 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2065 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2066 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2067 stat->rx_desc_oflows += smb->rx_desc_oflows; 2068 stat->rx_alignerrs += smb->rx_alignerrs; 2069 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2070 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2071 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2072 2073 /* Tx stats. */ 2074 stat->tx_frames += smb->tx_frames; 2075 stat->tx_bcast_frames += smb->tx_bcast_frames; 2076 stat->tx_mcast_frames += smb->tx_mcast_frames; 2077 stat->tx_pause_frames += smb->tx_pause_frames; 2078 stat->tx_excess_defer += smb->tx_excess_defer; 2079 stat->tx_control_frames += smb->tx_control_frames; 2080 stat->tx_deferred += smb->tx_deferred; 2081 stat->tx_bytes += smb->tx_bytes; 2082 stat->tx_pkts_64 += smb->tx_pkts_64; 2083 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2084 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2085 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2086 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2087 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2088 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2089 stat->tx_single_colls += smb->tx_single_colls; 2090 stat->tx_multi_colls += smb->tx_multi_colls; 2091 stat->tx_late_colls += smb->tx_late_colls; 2092 stat->tx_excess_colls += smb->tx_excess_colls; 2093 stat->tx_underrun += smb->tx_underrun; 2094 stat->tx_desc_underrun += smb->tx_desc_underrun; 2095 stat->tx_lenerrs += smb->tx_lenerrs; 2096 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2097 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2098 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2099 2100 /* Update counters in ifnet. */ 2101 ifp->if_opackets += smb->tx_frames; 2102 2103 ifp->if_collisions += smb->tx_single_colls + 2104 smb->tx_multi_colls + smb->tx_late_colls + 2105 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2106 2107 ifp->if_oerrors += smb->tx_excess_colls + 2108 smb->tx_late_colls + smb->tx_underrun + 2109 smb->tx_pkts_truncated; 2110 2111 ifp->if_ipackets += smb->rx_frames; 2112 2113 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2114 smb->rx_runts + smb->rx_pkts_truncated + 2115 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2116 smb->rx_alignerrs; 2117 2118 /* Update done, clear. */ 2119 smb->updated = 0; 2120 2121 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2122 sc->age_cdata.age_smb_block_map, 2123 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2124 } 2125 2126 static int 2127 age_intr(void *arg) 2128 { 2129 struct age_softc *sc; 2130 uint32_t status; 2131 2132 sc = (struct age_softc *)arg; 2133 2134 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2135 if (status == 0 || (status & AGE_INTRS) == 0) 2136 return (FILTER_STRAY); 2137 /* Disable interrupts. */ 2138 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2139 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2140 2141 return (FILTER_HANDLED); 2142 } 2143 2144 static void 2145 age_int_task(void *arg, int pending) 2146 { 2147 struct age_softc *sc; 2148 struct ifnet *ifp; 2149 struct cmb *cmb; 2150 uint32_t status; 2151 2152 sc = (struct age_softc *)arg; 2153 2154 AGE_LOCK(sc); 2155 2156 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2157 sc->age_cdata.age_cmb_block_map, 2158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2159 cmb = sc->age_rdata.age_cmb_block; 2160 status = le32toh(cmb->intr_status); 2161 if (sc->age_morework != 0) 2162 status |= INTR_CMB_RX; 2163 if ((status & AGE_INTRS) == 0) 2164 goto done; 2165 2166 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2167 TPD_CONS_SHIFT; 2168 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2169 RRD_PROD_SHIFT; 2170 /* Let hardware know CMB was served. */ 2171 cmb->intr_status = 0; 2172 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2173 sc->age_cdata.age_cmb_block_map, 2174 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2175 2176 #if 0 2177 printf("INTR: 0x%08x\n", status); 2178 status &= ~INTR_DIS_DMA; 2179 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2180 #endif 2181 ifp = sc->age_ifp; 2182 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2183 if ((status & INTR_CMB_RX) != 0) 2184 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2185 sc->age_process_limit); 2186 if ((status & INTR_CMB_TX) != 0) 2187 age_txintr(sc, sc->age_tpd_cons); 2188 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2189 if ((status & INTR_DMA_RD_TO_RST) != 0) 2190 device_printf(sc->age_dev, 2191 "DMA read error! -- resetting\n"); 2192 if ((status & INTR_DMA_WR_TO_RST) != 0) 2193 device_printf(sc->age_dev, 2194 "DMA write error! -- resetting\n"); 2195 age_init_locked(sc); 2196 } 2197 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2198 taskqueue_enqueue(sc->age_tq, &sc->age_tx_task); 2199 if ((status & INTR_SMB) != 0) 2200 age_stats_update(sc); 2201 } 2202 2203 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2204 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2205 sc->age_cdata.age_cmb_block_map, 2206 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2207 status = le32toh(cmb->intr_status); 2208 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2209 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2210 AGE_UNLOCK(sc); 2211 return; 2212 } 2213 2214 done: 2215 /* Re-enable interrupts. */ 2216 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2217 AGE_UNLOCK(sc); 2218 } 2219 2220 static void 2221 age_txintr(struct age_softc *sc, int tpd_cons) 2222 { 2223 struct ifnet *ifp; 2224 struct age_txdesc *txd; 2225 int cons, prog; 2226 2227 AGE_LOCK_ASSERT(sc); 2228 2229 ifp = sc->age_ifp; 2230 2231 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2232 sc->age_cdata.age_tx_ring_map, 2233 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2234 2235 /* 2236 * Go through our Tx list and free mbufs for those 2237 * frames which have been transmitted. 2238 */ 2239 cons = sc->age_cdata.age_tx_cons; 2240 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2241 if (sc->age_cdata.age_tx_cnt <= 0) 2242 break; 2243 prog++; 2244 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2245 sc->age_cdata.age_tx_cnt--; 2246 txd = &sc->age_cdata.age_txdesc[cons]; 2247 /* 2248 * Clear Tx descriptors, it's not required but would 2249 * help debugging in case of Tx issues. 2250 */ 2251 txd->tx_desc->addr = 0; 2252 txd->tx_desc->len = 0; 2253 txd->tx_desc->flags = 0; 2254 2255 if (txd->tx_m == NULL) 2256 continue; 2257 /* Reclaim transmitted mbufs. */ 2258 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2259 BUS_DMASYNC_POSTWRITE); 2260 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2261 m_freem(txd->tx_m); 2262 txd->tx_m = NULL; 2263 } 2264 2265 if (prog > 0) { 2266 sc->age_cdata.age_tx_cons = cons; 2267 2268 /* 2269 * Unarm watchdog timer only when there are no pending 2270 * Tx descriptors in queue. 2271 */ 2272 if (sc->age_cdata.age_tx_cnt == 0) 2273 sc->age_watchdog_timer = 0; 2274 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2275 sc->age_cdata.age_tx_ring_map, 2276 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2277 } 2278 } 2279 2280 /* Receive a frame. */ 2281 static void 2282 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2283 { 2284 struct age_rxdesc *rxd; 2285 struct rx_desc *desc; 2286 struct ifnet *ifp; 2287 struct mbuf *mp, *m; 2288 uint32_t status, index, vtag; 2289 int count, nsegs, pktlen; 2290 int rx_cons; 2291 2292 AGE_LOCK_ASSERT(sc); 2293 2294 ifp = sc->age_ifp; 2295 status = le32toh(rxrd->flags); 2296 index = le32toh(rxrd->index); 2297 rx_cons = AGE_RX_CONS(index); 2298 nsegs = AGE_RX_NSEGS(index); 2299 2300 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2301 if ((status & AGE_RRD_ERROR) != 0 && 2302 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2303 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2304 /* 2305 * We want to pass the following frames to upper 2306 * layer regardless of error status of Rx return 2307 * ring. 2308 * 2309 * o IP/TCP/UDP checksum is bad. 2310 * o frame length and protocol specific length 2311 * does not match. 2312 */ 2313 sc->age_cdata.age_rx_cons += nsegs; 2314 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2315 return; 2316 } 2317 2318 pktlen = 0; 2319 for (count = 0; count < nsegs; count++, 2320 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2321 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2322 mp = rxd->rx_m; 2323 desc = rxd->rx_desc; 2324 /* Add a new receive buffer to the ring. */ 2325 if (age_newbuf(sc, rxd) != 0) { 2326 ifp->if_iqdrops++; 2327 /* Reuse Rx buffers. */ 2328 if (sc->age_cdata.age_rxhead != NULL) { 2329 m_freem(sc->age_cdata.age_rxhead); 2330 AGE_RXCHAIN_RESET(sc); 2331 } 2332 break; 2333 } 2334 2335 /* The length of the first mbuf is computed last. */ 2336 if (count != 0) { 2337 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2338 pktlen += mp->m_len; 2339 } 2340 2341 /* Chain received mbufs. */ 2342 if (sc->age_cdata.age_rxhead == NULL) { 2343 sc->age_cdata.age_rxhead = mp; 2344 sc->age_cdata.age_rxtail = mp; 2345 } else { 2346 mp->m_flags &= ~M_PKTHDR; 2347 sc->age_cdata.age_rxprev_tail = 2348 sc->age_cdata.age_rxtail; 2349 sc->age_cdata.age_rxtail->m_next = mp; 2350 sc->age_cdata.age_rxtail = mp; 2351 } 2352 2353 if (count == nsegs - 1) { 2354 /* 2355 * It seems that L1 controller has no way 2356 * to tell hardware to strip CRC bytes. 2357 */ 2358 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2359 if (nsegs > 1) { 2360 /* Remove the CRC bytes in chained mbufs. */ 2361 pktlen -= ETHER_CRC_LEN; 2362 if (mp->m_len <= ETHER_CRC_LEN) { 2363 sc->age_cdata.age_rxtail = 2364 sc->age_cdata.age_rxprev_tail; 2365 sc->age_cdata.age_rxtail->m_len -= 2366 (ETHER_CRC_LEN - mp->m_len); 2367 sc->age_cdata.age_rxtail->m_next = NULL; 2368 m_freem(mp); 2369 } else { 2370 mp->m_len -= ETHER_CRC_LEN; 2371 } 2372 } 2373 2374 m = sc->age_cdata.age_rxhead; 2375 m->m_flags |= M_PKTHDR; 2376 m->m_pkthdr.rcvif = ifp; 2377 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2378 /* Set the first mbuf length. */ 2379 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2380 2381 /* 2382 * Set checksum information. 2383 * It seems that L1 controller can compute partial 2384 * checksum. The partial checksum value can be used 2385 * to accelerate checksum computation for fragmented 2386 * TCP/UDP packets. Upper network stack already 2387 * takes advantage of the partial checksum value in 2388 * IP reassembly stage. But I'm not sure the 2389 * correctness of the partial hardware checksum 2390 * assistance due to lack of data sheet. If it is 2391 * proven to work on L1 I'll enable it. 2392 */ 2393 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2394 (status & AGE_RRD_IPV4) != 0) { 2395 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2396 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2397 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2398 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2399 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2400 m->m_pkthdr.csum_flags |= 2401 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2402 m->m_pkthdr.csum_data = 0xffff; 2403 } 2404 /* 2405 * Don't mark bad checksum for TCP/UDP frames 2406 * as fragmented frames may always have set 2407 * bad checksummed bit of descriptor status. 2408 */ 2409 } 2410 2411 /* Check for VLAN tagged frames. */ 2412 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2413 (status & AGE_RRD_VLAN) != 0) { 2414 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2415 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2416 m->m_flags |= M_VLANTAG; 2417 } 2418 2419 /* Pass it on. */ 2420 AGE_UNLOCK(sc); 2421 (*ifp->if_input)(ifp, m); 2422 AGE_LOCK(sc); 2423 2424 /* Reset mbuf chains. */ 2425 AGE_RXCHAIN_RESET(sc); 2426 } 2427 } 2428 2429 if (count != nsegs) { 2430 sc->age_cdata.age_rx_cons += nsegs; 2431 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2432 } else 2433 sc->age_cdata.age_rx_cons = rx_cons; 2434 } 2435 2436 static int 2437 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2438 { 2439 struct rx_rdesc *rxrd; 2440 int rr_cons, nsegs, pktlen, prog; 2441 2442 AGE_LOCK_ASSERT(sc); 2443 2444 rr_cons = sc->age_cdata.age_rr_cons; 2445 if (rr_cons == rr_prod) 2446 return (0); 2447 2448 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2449 sc->age_cdata.age_rr_ring_map, 2450 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2451 2452 for (prog = 0; rr_cons != rr_prod; prog++) { 2453 if (count <= 0) 2454 break; 2455 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2456 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2457 if (nsegs == 0) 2458 break; 2459 /* 2460 * Check number of segments against received bytes. 2461 * Non-matching value would indicate that hardware 2462 * is still trying to update Rx return descriptors. 2463 * I'm not sure whether this check is really needed. 2464 */ 2465 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2466 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2467 (MCLBYTES - ETHER_ALIGN))) 2468 break; 2469 2470 prog++; 2471 /* Received a frame. */ 2472 age_rxeof(sc, rxrd); 2473 /* Clear return ring. */ 2474 rxrd->index = 0; 2475 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2476 } 2477 2478 if (prog > 0) { 2479 /* Update the consumer index. */ 2480 sc->age_cdata.age_rr_cons = rr_cons; 2481 2482 /* Sync descriptors. */ 2483 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2484 sc->age_cdata.age_rr_ring_map, 2485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2486 2487 /* Notify hardware availability of new Rx buffers. */ 2488 AGE_COMMIT_MBOX(sc); 2489 } 2490 2491 return (count > 0 ? 0 : EAGAIN); 2492 } 2493 2494 static void 2495 age_tick(void *arg) 2496 { 2497 struct age_softc *sc; 2498 struct mii_data *mii; 2499 2500 sc = (struct age_softc *)arg; 2501 2502 AGE_LOCK_ASSERT(sc); 2503 2504 mii = device_get_softc(sc->age_miibus); 2505 mii_tick(mii); 2506 age_watchdog(sc); 2507 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2508 } 2509 2510 static void 2511 age_reset(struct age_softc *sc) 2512 { 2513 uint32_t reg; 2514 int i; 2515 2516 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2517 CSR_READ_4(sc, AGE_MASTER_CFG); 2518 DELAY(1000); 2519 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2520 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2521 break; 2522 DELAY(10); 2523 } 2524 2525 if (i == 0) 2526 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2527 /* Initialize PCIe module. From Linux. */ 2528 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2529 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2530 } 2531 2532 static void 2533 age_init(void *xsc) 2534 { 2535 struct age_softc *sc; 2536 2537 sc = (struct age_softc *)xsc; 2538 AGE_LOCK(sc); 2539 age_init_locked(sc); 2540 AGE_UNLOCK(sc); 2541 } 2542 2543 static void 2544 age_init_locked(struct age_softc *sc) 2545 { 2546 struct ifnet *ifp; 2547 struct mii_data *mii; 2548 uint8_t eaddr[ETHER_ADDR_LEN]; 2549 bus_addr_t paddr; 2550 uint32_t reg, fsize; 2551 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2552 int error; 2553 2554 AGE_LOCK_ASSERT(sc); 2555 2556 ifp = sc->age_ifp; 2557 mii = device_get_softc(sc->age_miibus); 2558 2559 /* 2560 * Cancel any pending I/O. 2561 */ 2562 age_stop(sc); 2563 2564 /* 2565 * Reset the chip to a known state. 2566 */ 2567 age_reset(sc); 2568 2569 /* Initialize descriptors. */ 2570 error = age_init_rx_ring(sc); 2571 if (error != 0) { 2572 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2573 age_stop(sc); 2574 return; 2575 } 2576 age_init_rr_ring(sc); 2577 age_init_tx_ring(sc); 2578 age_init_cmb_block(sc); 2579 age_init_smb_block(sc); 2580 2581 /* Reprogram the station address. */ 2582 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2583 CSR_WRITE_4(sc, AGE_PAR0, 2584 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2585 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2586 2587 /* Set descriptor base addresses. */ 2588 paddr = sc->age_rdata.age_tx_ring_paddr; 2589 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2590 paddr = sc->age_rdata.age_rx_ring_paddr; 2591 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2592 paddr = sc->age_rdata.age_rr_ring_paddr; 2593 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2594 paddr = sc->age_rdata.age_tx_ring_paddr; 2595 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2596 paddr = sc->age_rdata.age_cmb_block_paddr; 2597 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2598 paddr = sc->age_rdata.age_smb_block_paddr; 2599 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2600 /* Set Rx/Rx return descriptor counter. */ 2601 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2602 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2603 DESC_RRD_CNT_MASK) | 2604 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2605 /* Set Tx descriptor counter. */ 2606 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2607 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2608 2609 /* Tell hardware that we're ready to load descriptors. */ 2610 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2611 2612 /* 2613 * Initialize mailbox register. 2614 * Updated producer/consumer index information is exchanged 2615 * through this mailbox register. However Tx producer and 2616 * Rx return consumer/Rx producer are all shared such that 2617 * it's hard to separate code path between Tx and Rx without 2618 * locking. If L1 hardware have a separate mail box register 2619 * for Tx and Rx consumer/producer management we could have 2620 * indepent Tx/Rx handler which in turn Rx handler could have 2621 * been run without any locking. 2622 */ 2623 AGE_COMMIT_MBOX(sc); 2624 2625 /* Configure IPG/IFG parameters. */ 2626 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2627 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2628 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2629 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2630 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2631 2632 /* Set parameters for half-duplex media. */ 2633 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2634 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2635 HDPX_CFG_LCOL_MASK) | 2636 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2637 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2638 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2639 HDPX_CFG_ABEBT_MASK) | 2640 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2641 HDPX_CFG_JAMIPG_MASK)); 2642 2643 /* Configure interrupt moderation timer. */ 2644 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2645 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2646 reg &= ~MASTER_MTIMER_ENB; 2647 if (AGE_USECS(sc->age_int_mod) == 0) 2648 reg &= ~MASTER_ITIMER_ENB; 2649 else 2650 reg |= MASTER_ITIMER_ENB; 2651 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2652 if (bootverbose) 2653 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2654 sc->age_int_mod); 2655 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2656 2657 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2658 if (ifp->if_mtu < ETHERMTU) 2659 sc->age_max_frame_size = ETHERMTU; 2660 else 2661 sc->age_max_frame_size = ifp->if_mtu; 2662 sc->age_max_frame_size += ETHER_HDR_LEN + 2663 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2664 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2665 /* Configure jumbo frame. */ 2666 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2667 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2668 (((fsize / sizeof(uint64_t)) << 2669 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2670 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2671 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2672 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2673 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2674 2675 /* Configure flow-control parameters. From Linux. */ 2676 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2677 /* 2678 * Magic workaround for old-L1. 2679 * Don't know which hw revision requires this magic. 2680 */ 2681 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2682 /* 2683 * Another magic workaround for flow-control mode 2684 * change. From Linux. 2685 */ 2686 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2687 } 2688 /* 2689 * TODO 2690 * Should understand pause parameter relationships between FIFO 2691 * size and number of Rx descriptors and Rx return descriptors. 2692 * 2693 * Magic parameters came from Linux. 2694 */ 2695 switch (sc->age_chip_rev) { 2696 case 0x8001: 2697 case 0x9001: 2698 case 0x9002: 2699 case 0x9003: 2700 rxf_hi = AGE_RX_RING_CNT / 16; 2701 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2702 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2703 rrd_lo = AGE_RR_RING_CNT / 16; 2704 break; 2705 default: 2706 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2707 rxf_lo = reg / 16; 2708 if (rxf_lo < 192) 2709 rxf_lo = 192; 2710 rxf_hi = (reg * 7) / 8; 2711 if (rxf_hi < rxf_lo) 2712 rxf_hi = rxf_lo + 16; 2713 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2714 rrd_lo = reg / 8; 2715 rrd_hi = (reg * 7) / 8; 2716 if (rrd_lo < 2) 2717 rrd_lo = 2; 2718 if (rrd_hi < rrd_lo) 2719 rrd_hi = rrd_lo + 3; 2720 break; 2721 } 2722 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2723 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2724 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2725 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2726 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2727 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2728 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2729 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2730 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2731 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2732 2733 /* Configure RxQ. */ 2734 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2735 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2736 RXQ_CFG_RD_BURST_MASK) | 2737 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2738 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2739 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2740 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2741 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2742 2743 /* Configure TxQ. */ 2744 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2745 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2746 TXQ_CFG_TPD_BURST_MASK) | 2747 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2748 TXQ_CFG_TX_FIFO_BURST_MASK) | 2749 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2750 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2751 TXQ_CFG_ENB); 2752 2753 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2754 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2755 TX_JUMBO_TPD_TH_MASK) | 2756 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2757 TX_JUMBO_TPD_IPG_MASK)); 2758 /* Configure DMA parameters. */ 2759 CSR_WRITE_4(sc, AGE_DMA_CFG, 2760 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2761 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2762 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2763 2764 /* Configure CMB DMA write threshold. */ 2765 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2766 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2767 CMB_WR_THRESH_RRD_MASK) | 2768 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2769 CMB_WR_THRESH_TPD_MASK)); 2770 2771 /* Set CMB/SMB timer and enable them. */ 2772 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2773 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2774 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2775 /* Request SMB updates for every seconds. */ 2776 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2777 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2778 2779 /* 2780 * Disable all WOL bits as WOL can interfere normal Rx 2781 * operation. 2782 */ 2783 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2784 2785 /* 2786 * Configure Tx/Rx MACs. 2787 * - Auto-padding for short frames. 2788 * - Enable CRC generation. 2789 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2790 * of MAC is followed after link establishment. 2791 */ 2792 CSR_WRITE_4(sc, AGE_MAC_CFG, 2793 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2794 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2795 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2796 MAC_CFG_PREAMBLE_MASK)); 2797 /* Set up the receive filter. */ 2798 age_rxfilter(sc); 2799 age_rxvlan(sc); 2800 2801 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2802 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2803 reg |= MAC_CFG_RXCSUM_ENB; 2804 2805 /* Ack all pending interrupts and clear it. */ 2806 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2807 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2808 2809 /* Finally enable Tx/Rx MAC. */ 2810 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2811 2812 sc->age_flags &= ~AGE_FLAG_LINK; 2813 /* Switch to the current media. */ 2814 mii_mediachg(mii); 2815 2816 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2817 2818 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2819 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2820 } 2821 2822 static void 2823 age_stop(struct age_softc *sc) 2824 { 2825 struct ifnet *ifp; 2826 struct age_txdesc *txd; 2827 struct age_rxdesc *rxd; 2828 uint32_t reg; 2829 int i; 2830 2831 AGE_LOCK_ASSERT(sc); 2832 /* 2833 * Mark the interface down and cancel the watchdog timer. 2834 */ 2835 ifp = sc->age_ifp; 2836 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2837 sc->age_flags &= ~AGE_FLAG_LINK; 2838 callout_stop(&sc->age_tick_ch); 2839 sc->age_watchdog_timer = 0; 2840 2841 /* 2842 * Disable interrupts. 2843 */ 2844 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2845 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2846 /* Stop CMB/SMB updates. */ 2847 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2848 /* Stop Rx/Tx MAC. */ 2849 age_stop_rxmac(sc); 2850 age_stop_txmac(sc); 2851 /* Stop DMA. */ 2852 CSR_WRITE_4(sc, AGE_DMA_CFG, 2853 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2854 /* Stop TxQ/RxQ. */ 2855 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2856 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2857 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2858 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2859 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2860 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2861 break; 2862 DELAY(10); 2863 } 2864 if (i == 0) 2865 device_printf(sc->age_dev, 2866 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2867 2868 /* Reclaim Rx buffers that have been processed. */ 2869 if (sc->age_cdata.age_rxhead != NULL) 2870 m_freem(sc->age_cdata.age_rxhead); 2871 AGE_RXCHAIN_RESET(sc); 2872 /* 2873 * Free RX and TX mbufs still in the queues. 2874 */ 2875 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2876 rxd = &sc->age_cdata.age_rxdesc[i]; 2877 if (rxd->rx_m != NULL) { 2878 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2879 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2880 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2881 rxd->rx_dmamap); 2882 m_freem(rxd->rx_m); 2883 rxd->rx_m = NULL; 2884 } 2885 } 2886 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2887 txd = &sc->age_cdata.age_txdesc[i]; 2888 if (txd->tx_m != NULL) { 2889 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2890 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2891 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2892 txd->tx_dmamap); 2893 m_freem(txd->tx_m); 2894 txd->tx_m = NULL; 2895 } 2896 } 2897 } 2898 2899 static void 2900 age_stop_txmac(struct age_softc *sc) 2901 { 2902 uint32_t reg; 2903 int i; 2904 2905 AGE_LOCK_ASSERT(sc); 2906 2907 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2908 if ((reg & MAC_CFG_TX_ENB) != 0) { 2909 reg &= ~MAC_CFG_TX_ENB; 2910 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2911 } 2912 /* Stop Tx DMA engine. */ 2913 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2914 if ((reg & DMA_CFG_RD_ENB) != 0) { 2915 reg &= ~DMA_CFG_RD_ENB; 2916 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2917 } 2918 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2919 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2920 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2921 break; 2922 DELAY(10); 2923 } 2924 if (i == 0) 2925 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2926 } 2927 2928 static void 2929 age_stop_rxmac(struct age_softc *sc) 2930 { 2931 uint32_t reg; 2932 int i; 2933 2934 AGE_LOCK_ASSERT(sc); 2935 2936 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2937 if ((reg & MAC_CFG_RX_ENB) != 0) { 2938 reg &= ~MAC_CFG_RX_ENB; 2939 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2940 } 2941 /* Stop Rx DMA engine. */ 2942 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2943 if ((reg & DMA_CFG_WR_ENB) != 0) { 2944 reg &= ~DMA_CFG_WR_ENB; 2945 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2946 } 2947 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2948 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2949 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2950 break; 2951 DELAY(10); 2952 } 2953 if (i == 0) 2954 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2955 } 2956 2957 static void 2958 age_init_tx_ring(struct age_softc *sc) 2959 { 2960 struct age_ring_data *rd; 2961 struct age_txdesc *txd; 2962 int i; 2963 2964 AGE_LOCK_ASSERT(sc); 2965 2966 sc->age_cdata.age_tx_prod = 0; 2967 sc->age_cdata.age_tx_cons = 0; 2968 sc->age_cdata.age_tx_cnt = 0; 2969 2970 rd = &sc->age_rdata; 2971 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2972 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2973 txd = &sc->age_cdata.age_txdesc[i]; 2974 txd->tx_desc = &rd->age_tx_ring[i]; 2975 txd->tx_m = NULL; 2976 } 2977 2978 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2979 sc->age_cdata.age_tx_ring_map, 2980 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2981 } 2982 2983 static int 2984 age_init_rx_ring(struct age_softc *sc) 2985 { 2986 struct age_ring_data *rd; 2987 struct age_rxdesc *rxd; 2988 int i; 2989 2990 AGE_LOCK_ASSERT(sc); 2991 2992 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2993 sc->age_morework = 0; 2994 rd = &sc->age_rdata; 2995 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2996 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2997 rxd = &sc->age_cdata.age_rxdesc[i]; 2998 rxd->rx_m = NULL; 2999 rxd->rx_desc = &rd->age_rx_ring[i]; 3000 if (age_newbuf(sc, rxd) != 0) 3001 return (ENOBUFS); 3002 } 3003 3004 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3005 sc->age_cdata.age_rx_ring_map, 3006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3007 3008 return (0); 3009 } 3010 3011 static void 3012 age_init_rr_ring(struct age_softc *sc) 3013 { 3014 struct age_ring_data *rd; 3015 3016 AGE_LOCK_ASSERT(sc); 3017 3018 sc->age_cdata.age_rr_cons = 0; 3019 AGE_RXCHAIN_RESET(sc); 3020 3021 rd = &sc->age_rdata; 3022 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3023 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3024 sc->age_cdata.age_rr_ring_map, 3025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3026 } 3027 3028 static void 3029 age_init_cmb_block(struct age_softc *sc) 3030 { 3031 struct age_ring_data *rd; 3032 3033 AGE_LOCK_ASSERT(sc); 3034 3035 rd = &sc->age_rdata; 3036 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3037 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3038 sc->age_cdata.age_cmb_block_map, 3039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3040 } 3041 3042 static void 3043 age_init_smb_block(struct age_softc *sc) 3044 { 3045 struct age_ring_data *rd; 3046 3047 AGE_LOCK_ASSERT(sc); 3048 3049 rd = &sc->age_rdata; 3050 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3051 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3052 sc->age_cdata.age_smb_block_map, 3053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3054 } 3055 3056 static int 3057 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3058 { 3059 struct rx_desc *desc; 3060 struct mbuf *m; 3061 bus_dma_segment_t segs[1]; 3062 bus_dmamap_t map; 3063 int nsegs; 3064 3065 AGE_LOCK_ASSERT(sc); 3066 3067 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3068 if (m == NULL) 3069 return (ENOBUFS); 3070 m->m_len = m->m_pkthdr.len = MCLBYTES; 3071 m_adj(m, ETHER_ALIGN); 3072 3073 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3074 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3075 m_freem(m); 3076 return (ENOBUFS); 3077 } 3078 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3079 3080 if (rxd->rx_m != NULL) { 3081 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3082 BUS_DMASYNC_POSTREAD); 3083 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3084 } 3085 map = rxd->rx_dmamap; 3086 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3087 sc->age_cdata.age_rx_sparemap = map; 3088 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3089 BUS_DMASYNC_PREREAD); 3090 rxd->rx_m = m; 3091 3092 desc = rxd->rx_desc; 3093 desc->addr = htole64(segs[0].ds_addr); 3094 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3095 AGE_RD_LEN_SHIFT); 3096 return (0); 3097 } 3098 3099 static void 3100 age_rxvlan(struct age_softc *sc) 3101 { 3102 struct ifnet *ifp; 3103 uint32_t reg; 3104 3105 AGE_LOCK_ASSERT(sc); 3106 3107 ifp = sc->age_ifp; 3108 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3109 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3110 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3111 reg |= MAC_CFG_VLAN_TAG_STRIP; 3112 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3113 } 3114 3115 static void 3116 age_rxfilter(struct age_softc *sc) 3117 { 3118 struct ifnet *ifp; 3119 struct ifmultiaddr *ifma; 3120 uint32_t crc; 3121 uint32_t mchash[2]; 3122 uint32_t rxcfg; 3123 3124 AGE_LOCK_ASSERT(sc); 3125 3126 ifp = sc->age_ifp; 3127 3128 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3129 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3130 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3131 rxcfg |= MAC_CFG_BCAST; 3132 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3133 if ((ifp->if_flags & IFF_PROMISC) != 0) 3134 rxcfg |= MAC_CFG_PROMISC; 3135 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3136 rxcfg |= MAC_CFG_ALLMULTI; 3137 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3138 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3139 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3140 return; 3141 } 3142 3143 /* Program new filter. */ 3144 bzero(mchash, sizeof(mchash)); 3145 3146 IF_ADDR_LOCK(ifp); 3147 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3148 if (ifma->ifma_addr->sa_family != AF_LINK) 3149 continue; 3150 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 3151 ifma->ifma_addr), ETHER_ADDR_LEN); 3152 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3153 } 3154 IF_ADDR_UNLOCK(ifp); 3155 3156 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3157 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3158 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3159 } 3160 3161 static int 3162 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3163 { 3164 struct age_softc *sc; 3165 struct age_stats *stats; 3166 int error, result; 3167 3168 result = -1; 3169 error = sysctl_handle_int(oidp, &result, 0, req); 3170 3171 if (error != 0 || req->newptr == NULL) 3172 return (error); 3173 3174 if (result != 1) 3175 return (error); 3176 3177 sc = (struct age_softc *)arg1; 3178 stats = &sc->age_stat; 3179 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3180 printf("Transmit good frames : %ju\n", 3181 (uintmax_t)stats->tx_frames); 3182 printf("Transmit good broadcast frames : %ju\n", 3183 (uintmax_t)stats->tx_bcast_frames); 3184 printf("Transmit good multicast frames : %ju\n", 3185 (uintmax_t)stats->tx_mcast_frames); 3186 printf("Transmit pause control frames : %u\n", 3187 stats->tx_pause_frames); 3188 printf("Transmit control frames : %u\n", 3189 stats->tx_control_frames); 3190 printf("Transmit frames with excessive deferrals : %u\n", 3191 stats->tx_excess_defer); 3192 printf("Transmit deferrals : %u\n", 3193 stats->tx_deferred); 3194 printf("Transmit good octets : %ju\n", 3195 (uintmax_t)stats->tx_bytes); 3196 printf("Transmit good broadcast octets : %ju\n", 3197 (uintmax_t)stats->tx_bcast_bytes); 3198 printf("Transmit good multicast octets : %ju\n", 3199 (uintmax_t)stats->tx_mcast_bytes); 3200 printf("Transmit frames 64 bytes : %ju\n", 3201 (uintmax_t)stats->tx_pkts_64); 3202 printf("Transmit frames 65 to 127 bytes : %ju\n", 3203 (uintmax_t)stats->tx_pkts_65_127); 3204 printf("Transmit frames 128 to 255 bytes : %ju\n", 3205 (uintmax_t)stats->tx_pkts_128_255); 3206 printf("Transmit frames 256 to 511 bytes : %ju\n", 3207 (uintmax_t)stats->tx_pkts_256_511); 3208 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3209 (uintmax_t)stats->tx_pkts_512_1023); 3210 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3211 (uintmax_t)stats->tx_pkts_1024_1518); 3212 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3213 (uintmax_t)stats->tx_pkts_1519_max); 3214 printf("Transmit single collisions : %u\n", 3215 stats->tx_single_colls); 3216 printf("Transmit multiple collisions : %u\n", 3217 stats->tx_multi_colls); 3218 printf("Transmit late collisions : %u\n", 3219 stats->tx_late_colls); 3220 printf("Transmit abort due to excessive collisions : %u\n", 3221 stats->tx_excess_colls); 3222 printf("Transmit underruns due to FIFO underruns : %u\n", 3223 stats->tx_underrun); 3224 printf("Transmit descriptor write-back errors : %u\n", 3225 stats->tx_desc_underrun); 3226 printf("Transmit frames with length mismatched frame size : %u\n", 3227 stats->tx_lenerrs); 3228 printf("Transmit frames with truncated due to MTU size : %u\n", 3229 stats->tx_lenerrs); 3230 3231 printf("Receive good frames : %ju\n", 3232 (uintmax_t)stats->rx_frames); 3233 printf("Receive good broadcast frames : %ju\n", 3234 (uintmax_t)stats->rx_bcast_frames); 3235 printf("Receive good multicast frames : %ju\n", 3236 (uintmax_t)stats->rx_mcast_frames); 3237 printf("Receive pause control frames : %u\n", 3238 stats->rx_pause_frames); 3239 printf("Receive control frames : %u\n", 3240 stats->rx_control_frames); 3241 printf("Receive CRC errors : %u\n", 3242 stats->rx_crcerrs); 3243 printf("Receive frames with length errors : %u\n", 3244 stats->rx_lenerrs); 3245 printf("Receive good octets : %ju\n", 3246 (uintmax_t)stats->rx_bytes); 3247 printf("Receive good broadcast octets : %ju\n", 3248 (uintmax_t)stats->rx_bcast_bytes); 3249 printf("Receive good multicast octets : %ju\n", 3250 (uintmax_t)stats->rx_mcast_bytes); 3251 printf("Receive frames too short : %u\n", 3252 stats->rx_runts); 3253 printf("Receive fragmented frames : %ju\n", 3254 (uintmax_t)stats->rx_fragments); 3255 printf("Receive frames 64 bytes : %ju\n", 3256 (uintmax_t)stats->rx_pkts_64); 3257 printf("Receive frames 65 to 127 bytes : %ju\n", 3258 (uintmax_t)stats->rx_pkts_65_127); 3259 printf("Receive frames 128 to 255 bytes : %ju\n", 3260 (uintmax_t)stats->rx_pkts_128_255); 3261 printf("Receive frames 256 to 511 bytes : %ju\n", 3262 (uintmax_t)stats->rx_pkts_256_511); 3263 printf("Receive frames 512 to 1024 bytes : %ju\n", 3264 (uintmax_t)stats->rx_pkts_512_1023); 3265 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3266 (uintmax_t)stats->rx_pkts_1024_1518); 3267 printf("Receive frames 1519 to MTU bytes : %ju\n", 3268 (uintmax_t)stats->rx_pkts_1519_max); 3269 printf("Receive frames too long : %ju\n", 3270 (uint64_t)stats->rx_pkts_truncated); 3271 printf("Receive frames with FIFO overflow : %u\n", 3272 stats->rx_fifo_oflows); 3273 printf("Receive frames with return descriptor overflow : %u\n", 3274 stats->rx_desc_oflows); 3275 printf("Receive frames with alignment errors : %u\n", 3276 stats->rx_alignerrs); 3277 printf("Receive frames dropped due to address filtering : %ju\n", 3278 (uint64_t)stats->rx_pkts_filtered); 3279 3280 return (error); 3281 } 3282 3283 static int 3284 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3285 { 3286 int error, value; 3287 3288 if (arg1 == NULL) 3289 return (EINVAL); 3290 value = *(int *)arg1; 3291 error = sysctl_handle_int(oidp, &value, 0, req); 3292 if (error || req->newptr == NULL) 3293 return (error); 3294 if (value < low || value > high) 3295 return (EINVAL); 3296 *(int *)arg1 = value; 3297 3298 return (0); 3299 } 3300 3301 static int 3302 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3303 { 3304 return (sysctl_int_range(oidp, arg1, arg2, req, 3305 AGE_PROC_MIN, AGE_PROC_MAX)); 3306 } 3307 3308 static int 3309 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3310 { 3311 3312 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3313 AGE_IM_TIMER_MAX)); 3314 } 3315