1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/age/if_agereg.h> 72 #include <dev/age/if_agevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78 79 MODULE_DEPEND(age, pci, 1, 1, 1); 80 MODULE_DEPEND(age, ether, 1, 1, 1); 81 MODULE_DEPEND(age, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 static int msix_disable = 0; 86 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 87 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 88 89 /* 90 * Devices supported by this driver. 91 */ 92 static struct age_dev { 93 uint16_t age_vendorid; 94 uint16_t age_deviceid; 95 const char *age_name; 96 } age_devs[] = { 97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99 }; 100 101 static int age_miibus_readreg(device_t, int, int); 102 static int age_miibus_writereg(device_t, int, int, int); 103 static void age_miibus_statchg(device_t); 104 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 105 static int age_mediachange(struct ifnet *); 106 static int age_probe(device_t); 107 static void age_get_macaddr(struct age_softc *); 108 static void age_phy_reset(struct age_softc *); 109 static int age_attach(device_t); 110 static int age_detach(device_t); 111 static void age_sysctl_node(struct age_softc *); 112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 static int age_check_boundary(struct age_softc *); 114 static int age_dma_alloc(struct age_softc *); 115 static void age_dma_free(struct age_softc *); 116 static int age_shutdown(device_t); 117 static void age_setwol(struct age_softc *); 118 static int age_suspend(device_t); 119 static int age_resume(device_t); 120 static int age_encap(struct age_softc *, struct mbuf **); 121 static void age_start(struct ifnet *); 122 static void age_start_locked(struct ifnet *); 123 static void age_watchdog(struct age_softc *); 124 static int age_ioctl(struct ifnet *, u_long, caddr_t); 125 static void age_mac_config(struct age_softc *); 126 static void age_link_task(void *, int); 127 static void age_stats_update(struct age_softc *); 128 static int age_intr(void *); 129 static void age_int_task(void *, int); 130 static void age_txintr(struct age_softc *, int); 131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132 static int age_rxintr(struct age_softc *, int, int); 133 static void age_tick(void *); 134 static void age_reset(struct age_softc *); 135 static void age_init(void *); 136 static void age_init_locked(struct age_softc *); 137 static void age_stop(struct age_softc *); 138 static void age_stop_txmac(struct age_softc *); 139 static void age_stop_rxmac(struct age_softc *); 140 static void age_init_tx_ring(struct age_softc *); 141 static int age_init_rx_ring(struct age_softc *); 142 static void age_init_rr_ring(struct age_softc *); 143 static void age_init_cmb_block(struct age_softc *); 144 static void age_init_smb_block(struct age_softc *); 145 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 146 static void age_rxvlan(struct age_softc *); 147 static void age_rxfilter(struct age_softc *); 148 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152 153 154 static device_method_t age_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, age_probe), 157 DEVMETHOD(device_attach, age_attach), 158 DEVMETHOD(device_detach, age_detach), 159 DEVMETHOD(device_shutdown, age_shutdown), 160 DEVMETHOD(device_suspend, age_suspend), 161 DEVMETHOD(device_resume, age_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, age_miibus_readreg), 165 DEVMETHOD(miibus_writereg, age_miibus_writereg), 166 DEVMETHOD(miibus_statchg, age_miibus_statchg), 167 168 { NULL, NULL } 169 }; 170 171 static driver_t age_driver = { 172 "age", 173 age_methods, 174 sizeof(struct age_softc) 175 }; 176 177 static devclass_t age_devclass; 178 179 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181 182 static struct resource_spec age_res_spec_mem[] = { 183 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184 { -1, 0, 0 } 185 }; 186 187 static struct resource_spec age_irq_spec_legacy[] = { 188 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189 { -1, 0, 0 } 190 }; 191 192 static struct resource_spec age_irq_spec_msi[] = { 193 { SYS_RES_IRQ, 1, RF_ACTIVE }, 194 { -1, 0, 0 } 195 }; 196 197 static struct resource_spec age_irq_spec_msix[] = { 198 { SYS_RES_IRQ, 1, RF_ACTIVE }, 199 { -1, 0, 0 } 200 }; 201 202 /* 203 * Read a PHY register on the MII of the L1. 204 */ 205 static int 206 age_miibus_readreg(device_t dev, int phy, int reg) 207 { 208 struct age_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(1); 218 v = CSR_READ_4(sc, AGE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229 } 230 231 /* 232 * Write a PHY register on the MII of the L1. 233 */ 234 static int 235 age_miibus_writereg(device_t dev, int phy, int reg, int val) 236 { 237 struct age_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 247 DELAY(1); 248 v = CSR_READ_4(sc, AGE_MDIO); 249 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250 break; 251 } 252 253 if (i == 0) 254 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 255 256 return (0); 257 } 258 259 /* 260 * Callback from MII layer when media changes. 261 */ 262 static void 263 age_miibus_statchg(device_t dev) 264 { 265 struct age_softc *sc; 266 267 sc = device_get_softc(dev); 268 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 269 } 270 271 /* 272 * Get the current interface media status. 273 */ 274 static void 275 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 276 { 277 struct age_softc *sc; 278 struct mii_data *mii; 279 280 sc = ifp->if_softc; 281 AGE_LOCK(sc); 282 mii = device_get_softc(sc->age_miibus); 283 284 mii_pollstat(mii); 285 AGE_UNLOCK(sc); 286 ifmr->ifm_status = mii->mii_media_status; 287 ifmr->ifm_active = mii->mii_media_active; 288 } 289 290 /* 291 * Set hardware to newly-selected media. 292 */ 293 static int 294 age_mediachange(struct ifnet *ifp) 295 { 296 struct age_softc *sc; 297 struct mii_data *mii; 298 struct mii_softc *miisc; 299 int error; 300 301 sc = ifp->if_softc; 302 AGE_LOCK(sc); 303 mii = device_get_softc(sc->age_miibus); 304 if (mii->mii_instance != 0) { 305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 306 mii_phy_reset(miisc); 307 } 308 error = mii_mediachg(mii); 309 AGE_UNLOCK(sc); 310 311 return (error); 312 } 313 314 static int 315 age_probe(device_t dev) 316 { 317 struct age_dev *sp; 318 int i; 319 uint16_t vendor, devid; 320 321 vendor = pci_get_vendor(dev); 322 devid = pci_get_device(dev); 323 sp = age_devs; 324 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 325 i++, sp++) { 326 if (vendor == sp->age_vendorid && 327 devid == sp->age_deviceid) { 328 device_set_desc(dev, sp->age_name); 329 return (BUS_PROBE_DEFAULT); 330 } 331 } 332 333 return (ENXIO); 334 } 335 336 static void 337 age_get_macaddr(struct age_softc *sc) 338 { 339 uint32_t ea[2], reg; 340 int i, vpdc; 341 342 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 343 if ((reg & SPI_VPD_ENB) != 0) { 344 /* Get VPD stored in TWSI EEPROM. */ 345 reg &= ~SPI_VPD_ENB; 346 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 347 } 348 349 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 350 /* 351 * PCI VPD capability found, let TWSI reload EEPROM. 352 * This will set ethernet address of controller. 353 */ 354 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 355 TWSI_CTRL_SW_LD_START); 356 for (i = 100; i > 0; i--) { 357 DELAY(1000); 358 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 359 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 360 break; 361 } 362 if (i == 0) 363 device_printf(sc->age_dev, 364 "reloading EEPROM timeout!\n"); 365 } else { 366 if (bootverbose) 367 device_printf(sc->age_dev, 368 "PCI VPD capability not found!\n"); 369 } 370 371 ea[0] = CSR_READ_4(sc, AGE_PAR0); 372 ea[1] = CSR_READ_4(sc, AGE_PAR1); 373 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 374 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 375 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 376 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 377 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 378 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 379 } 380 381 static void 382 age_phy_reset(struct age_softc *sc) 383 { 384 uint16_t reg, pn; 385 int i, linkup; 386 387 /* Reset PHY. */ 388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 389 DELAY(2000); 390 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 391 DELAY(2000); 392 393 #define ATPHY_DBG_ADDR 0x1D 394 #define ATPHY_DBG_DATA 0x1E 395 #define ATPHY_CDTC 0x16 396 #define PHY_CDTC_ENB 0x0001 397 #define PHY_CDTC_POFF 8 398 #define ATPHY_CDTS 0x1C 399 #define PHY_CDTS_STAT_OK 0x0000 400 #define PHY_CDTS_STAT_SHORT 0x0100 401 #define PHY_CDTS_STAT_OPEN 0x0200 402 #define PHY_CDTS_STAT_INVAL 0x0300 403 #define PHY_CDTS_STAT_MASK 0x0300 404 405 /* Check power saving mode. Magic from Linux. */ 406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 407 for (linkup = 0, pn = 0; pn < 4; pn++) { 408 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 409 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 410 for (i = 200; i > 0; i--) { 411 DELAY(1000); 412 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 413 ATPHY_CDTC); 414 if ((reg & PHY_CDTC_ENB) == 0) 415 break; 416 } 417 DELAY(1000); 418 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 419 ATPHY_CDTS); 420 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 421 linkup++; 422 break; 423 } 424 } 425 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 426 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 427 if (linkup == 0) { 428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429 ATPHY_DBG_ADDR, 0); 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431 ATPHY_DBG_DATA, 0x124E); 432 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_ADDR, 1); 434 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_DATA); 436 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 437 ATPHY_DBG_DATA, reg | 0x03); 438 /* XXX */ 439 DELAY(1500 * 1000); 440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441 ATPHY_DBG_ADDR, 0); 442 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 443 ATPHY_DBG_DATA, 0x024E); 444 } 445 446 #undef ATPHY_DBG_ADDR 447 #undef ATPHY_DBG_DATA 448 #undef ATPHY_CDTC 449 #undef PHY_CDTC_ENB 450 #undef PHY_CDTC_POFF 451 #undef ATPHY_CDTS 452 #undef PHY_CDTS_STAT_OK 453 #undef PHY_CDTS_STAT_SHORT 454 #undef PHY_CDTS_STAT_OPEN 455 #undef PHY_CDTS_STAT_INVAL 456 #undef PHY_CDTS_STAT_MASK 457 } 458 459 static int 460 age_attach(device_t dev) 461 { 462 struct age_softc *sc; 463 struct ifnet *ifp; 464 uint16_t burst; 465 int error, i, msic, msixc, pmc; 466 467 error = 0; 468 sc = device_get_softc(dev); 469 sc->age_dev = dev; 470 471 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 472 MTX_DEF); 473 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 474 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 475 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 476 477 /* Map the device. */ 478 pci_enable_busmaster(dev); 479 sc->age_res_spec = age_res_spec_mem; 480 sc->age_irq_spec = age_irq_spec_legacy; 481 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 482 if (error != 0) { 483 device_printf(dev, "cannot allocate memory resources.\n"); 484 goto fail; 485 } 486 487 /* Set PHY address. */ 488 sc->age_phyaddr = AGE_PHY_ADDR; 489 490 /* Reset PHY. */ 491 age_phy_reset(sc); 492 493 /* Reset the ethernet controller. */ 494 age_reset(sc); 495 496 /* Get PCI and chip id/revision. */ 497 sc->age_rev = pci_get_revid(dev); 498 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 499 MASTER_CHIP_REV_SHIFT; 500 if (bootverbose) { 501 device_printf(dev, "PCI device revision : 0x%04x\n", 502 sc->age_rev); 503 device_printf(dev, "Chip id/revision : 0x%04x\n", 504 sc->age_chip_rev); 505 } 506 507 /* 508 * XXX 509 * Unintialized hardware returns an invalid chip id/revision 510 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 511 * unplugged cable results in putting hardware into automatic 512 * power down mode which in turn returns invalld chip revision. 513 */ 514 if (sc->age_chip_rev == 0xFFFF) { 515 device_printf(dev,"invalid chip revision : 0x%04x -- " 516 "not initialized?\n", sc->age_chip_rev); 517 error = ENXIO; 518 goto fail; 519 } 520 521 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 522 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 523 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 524 525 /* Allocate IRQ resources. */ 526 msixc = pci_msix_count(dev); 527 msic = pci_msi_count(dev); 528 if (bootverbose) { 529 device_printf(dev, "MSIX count : %d\n", msixc); 530 device_printf(dev, "MSI count : %d\n", msic); 531 } 532 533 /* Prefer MSIX over MSI. */ 534 if (msix_disable == 0 || msi_disable == 0) { 535 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 536 pci_alloc_msix(dev, &msixc) == 0) { 537 if (msic == AGE_MSIX_MESSAGES) { 538 device_printf(dev, "Using %d MSIX messages.\n", 539 msixc); 540 sc->age_flags |= AGE_FLAG_MSIX; 541 sc->age_irq_spec = age_irq_spec_msix; 542 } else 543 pci_release_msi(dev); 544 } 545 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 546 msic == AGE_MSI_MESSAGES && 547 pci_alloc_msi(dev, &msic) == 0) { 548 if (msic == AGE_MSI_MESSAGES) { 549 device_printf(dev, "Using %d MSI messages.\n", 550 msic); 551 sc->age_flags |= AGE_FLAG_MSI; 552 sc->age_irq_spec = age_irq_spec_msi; 553 } else 554 pci_release_msi(dev); 555 } 556 } 557 558 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 559 if (error != 0) { 560 device_printf(dev, "cannot allocate IRQ resources.\n"); 561 goto fail; 562 } 563 564 565 /* Get DMA parameters from PCIe device control register. */ 566 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 567 sc->age_flags |= AGE_FLAG_PCIE; 568 burst = pci_read_config(dev, i + 0x08, 2); 569 /* Max read request size. */ 570 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 571 DMA_CFG_RD_BURST_SHIFT; 572 /* Max payload size. */ 573 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 574 DMA_CFG_WR_BURST_SHIFT; 575 if (bootverbose) { 576 device_printf(dev, "Read request size : %d bytes.\n", 577 128 << ((burst >> 12) & 0x07)); 578 device_printf(dev, "TLP payload size : %d bytes.\n", 579 128 << ((burst >> 5) & 0x07)); 580 } 581 } else { 582 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 583 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 584 } 585 586 /* Create device sysctl node. */ 587 age_sysctl_node(sc); 588 589 if ((error = age_dma_alloc(sc) != 0)) 590 goto fail; 591 592 /* Load station address. */ 593 age_get_macaddr(sc); 594 595 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 596 if (ifp == NULL) { 597 device_printf(dev, "cannot allocate ifnet structure.\n"); 598 error = ENXIO; 599 goto fail; 600 } 601 602 ifp->if_softc = sc; 603 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 605 ifp->if_ioctl = age_ioctl; 606 ifp->if_start = age_start; 607 ifp->if_init = age_init; 608 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 609 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 610 IFQ_SET_READY(&ifp->if_snd); 611 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 612 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 613 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 614 sc->age_flags |= AGE_FLAG_PMCAP; 615 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 616 } 617 ifp->if_capenable = ifp->if_capabilities; 618 619 /* Set up MII bus. */ 620 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 621 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 622 0); 623 if (error != 0) { 624 device_printf(dev, "attaching PHYs failed\n"); 625 goto fail; 626 } 627 628 ether_ifattach(ifp, sc->age_eaddr); 629 630 /* VLAN capability setup. */ 631 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 632 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 633 ifp->if_capenable = ifp->if_capabilities; 634 635 /* Tell the upper layer(s) we support long frames. */ 636 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 637 638 /* Create local taskq. */ 639 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 640 taskqueue_thread_enqueue, &sc->age_tq); 641 if (sc->age_tq == NULL) { 642 device_printf(dev, "could not create taskqueue.\n"); 643 ether_ifdetach(ifp); 644 error = ENXIO; 645 goto fail; 646 } 647 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 648 device_get_nameunit(sc->age_dev)); 649 650 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 651 msic = AGE_MSIX_MESSAGES; 652 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 653 msic = AGE_MSI_MESSAGES; 654 else 655 msic = 1; 656 for (i = 0; i < msic; i++) { 657 error = bus_setup_intr(dev, sc->age_irq[i], 658 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 659 &sc->age_intrhand[i]); 660 if (error != 0) 661 break; 662 } 663 if (error != 0) { 664 device_printf(dev, "could not set up interrupt handler.\n"); 665 taskqueue_free(sc->age_tq); 666 sc->age_tq = NULL; 667 ether_ifdetach(ifp); 668 goto fail; 669 } 670 671 fail: 672 if (error != 0) 673 age_detach(dev); 674 675 return (error); 676 } 677 678 static int 679 age_detach(device_t dev) 680 { 681 struct age_softc *sc; 682 struct ifnet *ifp; 683 int i, msic; 684 685 sc = device_get_softc(dev); 686 687 ifp = sc->age_ifp; 688 if (device_is_attached(dev)) { 689 AGE_LOCK(sc); 690 sc->age_flags |= AGE_FLAG_DETACH; 691 age_stop(sc); 692 AGE_UNLOCK(sc); 693 callout_drain(&sc->age_tick_ch); 694 taskqueue_drain(sc->age_tq, &sc->age_int_task); 695 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 696 ether_ifdetach(ifp); 697 } 698 699 if (sc->age_tq != NULL) { 700 taskqueue_drain(sc->age_tq, &sc->age_int_task); 701 taskqueue_free(sc->age_tq); 702 sc->age_tq = NULL; 703 } 704 705 if (sc->age_miibus != NULL) { 706 device_delete_child(dev, sc->age_miibus); 707 sc->age_miibus = NULL; 708 } 709 bus_generic_detach(dev); 710 age_dma_free(sc); 711 712 if (ifp != NULL) { 713 if_free(ifp); 714 sc->age_ifp = NULL; 715 } 716 717 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 718 msic = AGE_MSIX_MESSAGES; 719 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 720 msic = AGE_MSI_MESSAGES; 721 else 722 msic = 1; 723 for (i = 0; i < msic; i++) { 724 if (sc->age_intrhand[i] != NULL) { 725 bus_teardown_intr(dev, sc->age_irq[i], 726 sc->age_intrhand[i]); 727 sc->age_intrhand[i] = NULL; 728 } 729 } 730 731 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 732 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 733 pci_release_msi(dev); 734 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 735 mtx_destroy(&sc->age_mtx); 736 737 return (0); 738 } 739 740 static void 741 age_sysctl_node(struct age_softc *sc) 742 { 743 int error; 744 745 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 746 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 747 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 748 "I", "Statistics"); 749 750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 752 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 753 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 754 755 /* Pull in device tunables. */ 756 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 757 error = resource_int_value(device_get_name(sc->age_dev), 758 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 759 if (error == 0) { 760 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 761 sc->age_int_mod > AGE_IM_TIMER_MAX) { 762 device_printf(sc->age_dev, 763 "int_mod value out of range; using default: %d\n", 764 AGE_IM_TIMER_DEFAULT); 765 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 766 } 767 } 768 769 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 770 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 771 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 772 0, sysctl_hw_age_proc_limit, "I", 773 "max number of Rx events to process"); 774 775 /* Pull in device tunables. */ 776 sc->age_process_limit = AGE_PROC_DEFAULT; 777 error = resource_int_value(device_get_name(sc->age_dev), 778 device_get_unit(sc->age_dev), "process_limit", 779 &sc->age_process_limit); 780 if (error == 0) { 781 if (sc->age_process_limit < AGE_PROC_MIN || 782 sc->age_process_limit > AGE_PROC_MAX) { 783 device_printf(sc->age_dev, 784 "process_limit value out of range; " 785 "using default: %d\n", AGE_PROC_DEFAULT); 786 sc->age_process_limit = AGE_PROC_DEFAULT; 787 } 788 } 789 } 790 791 struct age_dmamap_arg { 792 bus_addr_t age_busaddr; 793 }; 794 795 static void 796 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 797 { 798 struct age_dmamap_arg *ctx; 799 800 if (error != 0) 801 return; 802 803 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 804 805 ctx = (struct age_dmamap_arg *)arg; 806 ctx->age_busaddr = segs[0].ds_addr; 807 } 808 809 /* 810 * Attansic L1 controller have single register to specify high 811 * address part of DMA blocks. So all descriptor structures and 812 * DMA memory blocks should have the same high address of given 813 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 814 */ 815 static int 816 age_check_boundary(struct age_softc *sc) 817 { 818 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 819 bus_addr_t cmb_block_end, smb_block_end; 820 821 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 822 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 823 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 824 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 825 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 826 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 827 828 if ((AGE_ADDR_HI(tx_ring_end) != 829 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 830 (AGE_ADDR_HI(rx_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 832 (AGE_ADDR_HI(rr_ring_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 834 (AGE_ADDR_HI(cmb_block_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 836 (AGE_ADDR_HI(smb_block_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 838 return (EFBIG); 839 840 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 841 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 842 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 844 return (EFBIG); 845 846 return (0); 847 } 848 849 static int 850 age_dma_alloc(struct age_softc *sc) 851 { 852 struct age_txdesc *txd; 853 struct age_rxdesc *rxd; 854 bus_addr_t lowaddr; 855 struct age_dmamap_arg ctx; 856 int error, i; 857 858 lowaddr = BUS_SPACE_MAXADDR; 859 860 again: 861 /* Create parent ring/DMA block tag. */ 862 error = bus_dma_tag_create( 863 bus_get_dma_tag(sc->age_dev), /* parent */ 864 1, 0, /* alignment, boundary */ 865 lowaddr, /* lowaddr */ 866 BUS_SPACE_MAXADDR, /* highaddr */ 867 NULL, NULL, /* filter, filterarg */ 868 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 869 0, /* nsegments */ 870 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 871 0, /* flags */ 872 NULL, NULL, /* lockfunc, lockarg */ 873 &sc->age_cdata.age_parent_tag); 874 if (error != 0) { 875 device_printf(sc->age_dev, 876 "could not create parent DMA tag.\n"); 877 goto fail; 878 } 879 880 /* Create tag for Tx ring. */ 881 error = bus_dma_tag_create( 882 sc->age_cdata.age_parent_tag, /* parent */ 883 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 884 BUS_SPACE_MAXADDR, /* lowaddr */ 885 BUS_SPACE_MAXADDR, /* highaddr */ 886 NULL, NULL, /* filter, filterarg */ 887 AGE_TX_RING_SZ, /* maxsize */ 888 1, /* nsegments */ 889 AGE_TX_RING_SZ, /* maxsegsize */ 890 0, /* flags */ 891 NULL, NULL, /* lockfunc, lockarg */ 892 &sc->age_cdata.age_tx_ring_tag); 893 if (error != 0) { 894 device_printf(sc->age_dev, 895 "could not create Tx ring DMA tag.\n"); 896 goto fail; 897 } 898 899 /* Create tag for Rx ring. */ 900 error = bus_dma_tag_create( 901 sc->age_cdata.age_parent_tag, /* parent */ 902 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 AGE_RX_RING_SZ, /* maxsize */ 907 1, /* nsegments */ 908 AGE_RX_RING_SZ, /* maxsegsize */ 909 0, /* flags */ 910 NULL, NULL, /* lockfunc, lockarg */ 911 &sc->age_cdata.age_rx_ring_tag); 912 if (error != 0) { 913 device_printf(sc->age_dev, 914 "could not create Rx ring DMA tag.\n"); 915 goto fail; 916 } 917 918 /* Create tag for Rx return ring. */ 919 error = bus_dma_tag_create( 920 sc->age_cdata.age_parent_tag, /* parent */ 921 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 922 BUS_SPACE_MAXADDR, /* lowaddr */ 923 BUS_SPACE_MAXADDR, /* highaddr */ 924 NULL, NULL, /* filter, filterarg */ 925 AGE_RR_RING_SZ, /* maxsize */ 926 1, /* nsegments */ 927 AGE_RR_RING_SZ, /* maxsegsize */ 928 0, /* flags */ 929 NULL, NULL, /* lockfunc, lockarg */ 930 &sc->age_cdata.age_rr_ring_tag); 931 if (error != 0) { 932 device_printf(sc->age_dev, 933 "could not create Rx return ring DMA tag.\n"); 934 goto fail; 935 } 936 937 /* Create tag for coalesing message block. */ 938 error = bus_dma_tag_create( 939 sc->age_cdata.age_parent_tag, /* parent */ 940 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 941 BUS_SPACE_MAXADDR, /* lowaddr */ 942 BUS_SPACE_MAXADDR, /* highaddr */ 943 NULL, NULL, /* filter, filterarg */ 944 AGE_CMB_BLOCK_SZ, /* maxsize */ 945 1, /* nsegments */ 946 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 947 0, /* flags */ 948 NULL, NULL, /* lockfunc, lockarg */ 949 &sc->age_cdata.age_cmb_block_tag); 950 if (error != 0) { 951 device_printf(sc->age_dev, 952 "could not create CMB DMA tag.\n"); 953 goto fail; 954 } 955 956 /* Create tag for statistics message block. */ 957 error = bus_dma_tag_create( 958 sc->age_cdata.age_parent_tag, /* parent */ 959 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 960 BUS_SPACE_MAXADDR, /* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 AGE_SMB_BLOCK_SZ, /* maxsize */ 964 1, /* nsegments */ 965 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 966 0, /* flags */ 967 NULL, NULL, /* lockfunc, lockarg */ 968 &sc->age_cdata.age_smb_block_tag); 969 if (error != 0) { 970 device_printf(sc->age_dev, 971 "could not create SMB DMA tag.\n"); 972 goto fail; 973 } 974 975 /* Allocate DMA'able memory and load the DMA map. */ 976 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 977 (void **)&sc->age_rdata.age_tx_ring, 978 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 979 &sc->age_cdata.age_tx_ring_map); 980 if (error != 0) { 981 device_printf(sc->age_dev, 982 "could not allocate DMA'able memory for Tx ring.\n"); 983 goto fail; 984 } 985 ctx.age_busaddr = 0; 986 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 987 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 988 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 989 if (error != 0 || ctx.age_busaddr == 0) { 990 device_printf(sc->age_dev, 991 "could not load DMA'able memory for Tx ring.\n"); 992 goto fail; 993 } 994 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 995 /* Rx ring */ 996 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 997 (void **)&sc->age_rdata.age_rx_ring, 998 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 999 &sc->age_cdata.age_rx_ring_map); 1000 if (error != 0) { 1001 device_printf(sc->age_dev, 1002 "could not allocate DMA'able memory for Rx ring.\n"); 1003 goto fail; 1004 } 1005 ctx.age_busaddr = 0; 1006 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1007 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1008 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1009 if (error != 0 || ctx.age_busaddr == 0) { 1010 device_printf(sc->age_dev, 1011 "could not load DMA'able memory for Rx ring.\n"); 1012 goto fail; 1013 } 1014 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1015 /* Rx return ring */ 1016 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1017 (void **)&sc->age_rdata.age_rr_ring, 1018 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1019 &sc->age_cdata.age_rr_ring_map); 1020 if (error != 0) { 1021 device_printf(sc->age_dev, 1022 "could not allocate DMA'able memory for Rx return ring.\n"); 1023 goto fail; 1024 } 1025 ctx.age_busaddr = 0; 1026 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1027 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1028 AGE_RR_RING_SZ, age_dmamap_cb, 1029 &ctx, 0); 1030 if (error != 0 || ctx.age_busaddr == 0) { 1031 device_printf(sc->age_dev, 1032 "could not load DMA'able memory for Rx return ring.\n"); 1033 goto fail; 1034 } 1035 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1036 /* CMB block */ 1037 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1038 (void **)&sc->age_rdata.age_cmb_block, 1039 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1040 &sc->age_cdata.age_cmb_block_map); 1041 if (error != 0) { 1042 device_printf(sc->age_dev, 1043 "could not allocate DMA'able memory for CMB block.\n"); 1044 goto fail; 1045 } 1046 ctx.age_busaddr = 0; 1047 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1048 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1049 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1050 if (error != 0 || ctx.age_busaddr == 0) { 1051 device_printf(sc->age_dev, 1052 "could not load DMA'able memory for CMB block.\n"); 1053 goto fail; 1054 } 1055 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1056 /* SMB block */ 1057 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1058 (void **)&sc->age_rdata.age_smb_block, 1059 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1060 &sc->age_cdata.age_smb_block_map); 1061 if (error != 0) { 1062 device_printf(sc->age_dev, 1063 "could not allocate DMA'able memory for SMB block.\n"); 1064 goto fail; 1065 } 1066 ctx.age_busaddr = 0; 1067 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1068 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1069 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1070 if (error != 0 || ctx.age_busaddr == 0) { 1071 device_printf(sc->age_dev, 1072 "could not load DMA'able memory for SMB block.\n"); 1073 goto fail; 1074 } 1075 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1076 1077 /* 1078 * All ring buffer and DMA blocks should have the same 1079 * high address part of 64bit DMA address space. 1080 */ 1081 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1082 (error = age_check_boundary(sc)) != 0) { 1083 device_printf(sc->age_dev, "4GB boundary crossed, " 1084 "switching to 32bit DMA addressing mode.\n"); 1085 age_dma_free(sc); 1086 /* Limit DMA address space to 32bit and try again. */ 1087 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1088 goto again; 1089 } 1090 1091 /* 1092 * Create Tx/Rx buffer parent tag. 1093 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1094 * so it needs separate parent DMA tag. 1095 * XXX 1096 * It seems enabling 64bit DMA causes data corruption. Limit 1097 * DMA address space to 32bit. 1098 */ 1099 error = bus_dma_tag_create( 1100 bus_get_dma_tag(sc->age_dev), /* parent */ 1101 1, 0, /* alignment, boundary */ 1102 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1103 BUS_SPACE_MAXADDR, /* highaddr */ 1104 NULL, NULL, /* filter, filterarg */ 1105 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1106 0, /* nsegments */ 1107 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1108 0, /* flags */ 1109 NULL, NULL, /* lockfunc, lockarg */ 1110 &sc->age_cdata.age_buffer_tag); 1111 if (error != 0) { 1112 device_printf(sc->age_dev, 1113 "could not create parent buffer DMA tag.\n"); 1114 goto fail; 1115 } 1116 1117 /* Create tag for Tx buffers. */ 1118 error = bus_dma_tag_create( 1119 sc->age_cdata.age_buffer_tag, /* parent */ 1120 1, 0, /* alignment, boundary */ 1121 BUS_SPACE_MAXADDR, /* lowaddr */ 1122 BUS_SPACE_MAXADDR, /* highaddr */ 1123 NULL, NULL, /* filter, filterarg */ 1124 AGE_TSO_MAXSIZE, /* maxsize */ 1125 AGE_MAXTXSEGS, /* nsegments */ 1126 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1127 0, /* flags */ 1128 NULL, NULL, /* lockfunc, lockarg */ 1129 &sc->age_cdata.age_tx_tag); 1130 if (error != 0) { 1131 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1132 goto fail; 1133 } 1134 1135 /* Create tag for Rx buffers. */ 1136 error = bus_dma_tag_create( 1137 sc->age_cdata.age_buffer_tag, /* parent */ 1138 1, 0, /* alignment, boundary */ 1139 BUS_SPACE_MAXADDR, /* lowaddr */ 1140 BUS_SPACE_MAXADDR, /* highaddr */ 1141 NULL, NULL, /* filter, filterarg */ 1142 MCLBYTES, /* maxsize */ 1143 1, /* nsegments */ 1144 MCLBYTES, /* maxsegsize */ 1145 0, /* flags */ 1146 NULL, NULL, /* lockfunc, lockarg */ 1147 &sc->age_cdata.age_rx_tag); 1148 if (error != 0) { 1149 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1150 goto fail; 1151 } 1152 1153 /* Create DMA maps for Tx buffers. */ 1154 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1155 txd = &sc->age_cdata.age_txdesc[i]; 1156 txd->tx_m = NULL; 1157 txd->tx_dmamap = NULL; 1158 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1159 &txd->tx_dmamap); 1160 if (error != 0) { 1161 device_printf(sc->age_dev, 1162 "could not create Tx dmamap.\n"); 1163 goto fail; 1164 } 1165 } 1166 /* Create DMA maps for Rx buffers. */ 1167 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1168 &sc->age_cdata.age_rx_sparemap)) != 0) { 1169 device_printf(sc->age_dev, 1170 "could not create spare Rx dmamap.\n"); 1171 goto fail; 1172 } 1173 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1174 rxd = &sc->age_cdata.age_rxdesc[i]; 1175 rxd->rx_m = NULL; 1176 rxd->rx_dmamap = NULL; 1177 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1178 &rxd->rx_dmamap); 1179 if (error != 0) { 1180 device_printf(sc->age_dev, 1181 "could not create Rx dmamap.\n"); 1182 goto fail; 1183 } 1184 } 1185 1186 fail: 1187 return (error); 1188 } 1189 1190 static void 1191 age_dma_free(struct age_softc *sc) 1192 { 1193 struct age_txdesc *txd; 1194 struct age_rxdesc *rxd; 1195 int i; 1196 1197 /* Tx buffers */ 1198 if (sc->age_cdata.age_tx_tag != NULL) { 1199 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1200 txd = &sc->age_cdata.age_txdesc[i]; 1201 if (txd->tx_dmamap != NULL) { 1202 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1203 txd->tx_dmamap); 1204 txd->tx_dmamap = NULL; 1205 } 1206 } 1207 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1208 sc->age_cdata.age_tx_tag = NULL; 1209 } 1210 /* Rx buffers */ 1211 if (sc->age_cdata.age_rx_tag != NULL) { 1212 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1213 rxd = &sc->age_cdata.age_rxdesc[i]; 1214 if (rxd->rx_dmamap != NULL) { 1215 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1216 rxd->rx_dmamap); 1217 rxd->rx_dmamap = NULL; 1218 } 1219 } 1220 if (sc->age_cdata.age_rx_sparemap != NULL) { 1221 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1222 sc->age_cdata.age_rx_sparemap); 1223 sc->age_cdata.age_rx_sparemap = NULL; 1224 } 1225 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1226 sc->age_cdata.age_rx_tag = NULL; 1227 } 1228 /* Tx ring. */ 1229 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1230 if (sc->age_cdata.age_tx_ring_map != NULL) 1231 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1232 sc->age_cdata.age_tx_ring_map); 1233 if (sc->age_cdata.age_tx_ring_map != NULL && 1234 sc->age_rdata.age_tx_ring != NULL) 1235 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1236 sc->age_rdata.age_tx_ring, 1237 sc->age_cdata.age_tx_ring_map); 1238 sc->age_rdata.age_tx_ring = NULL; 1239 sc->age_cdata.age_tx_ring_map = NULL; 1240 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1241 sc->age_cdata.age_tx_ring_tag = NULL; 1242 } 1243 /* Rx ring. */ 1244 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1245 if (sc->age_cdata.age_rx_ring_map != NULL) 1246 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1247 sc->age_cdata.age_rx_ring_map); 1248 if (sc->age_cdata.age_rx_ring_map != NULL && 1249 sc->age_rdata.age_rx_ring != NULL) 1250 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1251 sc->age_rdata.age_rx_ring, 1252 sc->age_cdata.age_rx_ring_map); 1253 sc->age_rdata.age_rx_ring = NULL; 1254 sc->age_cdata.age_rx_ring_map = NULL; 1255 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1256 sc->age_cdata.age_rx_ring_tag = NULL; 1257 } 1258 /* Rx return ring. */ 1259 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1260 if (sc->age_cdata.age_rr_ring_map != NULL) 1261 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1262 sc->age_cdata.age_rr_ring_map); 1263 if (sc->age_cdata.age_rr_ring_map != NULL && 1264 sc->age_rdata.age_rr_ring != NULL) 1265 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1266 sc->age_rdata.age_rr_ring, 1267 sc->age_cdata.age_rr_ring_map); 1268 sc->age_rdata.age_rr_ring = NULL; 1269 sc->age_cdata.age_rr_ring_map = NULL; 1270 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1271 sc->age_cdata.age_rr_ring_tag = NULL; 1272 } 1273 /* CMB block */ 1274 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1275 if (sc->age_cdata.age_cmb_block_map != NULL) 1276 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1277 sc->age_cdata.age_cmb_block_map); 1278 if (sc->age_cdata.age_cmb_block_map != NULL && 1279 sc->age_rdata.age_cmb_block != NULL) 1280 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1281 sc->age_rdata.age_cmb_block, 1282 sc->age_cdata.age_cmb_block_map); 1283 sc->age_rdata.age_cmb_block = NULL; 1284 sc->age_cdata.age_cmb_block_map = NULL; 1285 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1286 sc->age_cdata.age_cmb_block_tag = NULL; 1287 } 1288 /* SMB block */ 1289 if (sc->age_cdata.age_smb_block_tag != NULL) { 1290 if (sc->age_cdata.age_smb_block_map != NULL) 1291 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1292 sc->age_cdata.age_smb_block_map); 1293 if (sc->age_cdata.age_smb_block_map != NULL && 1294 sc->age_rdata.age_smb_block != NULL) 1295 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1296 sc->age_rdata.age_smb_block, 1297 sc->age_cdata.age_smb_block_map); 1298 sc->age_rdata.age_smb_block = NULL; 1299 sc->age_cdata.age_smb_block_map = NULL; 1300 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1301 sc->age_cdata.age_smb_block_tag = NULL; 1302 } 1303 1304 if (sc->age_cdata.age_buffer_tag != NULL) { 1305 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1306 sc->age_cdata.age_buffer_tag = NULL; 1307 } 1308 if (sc->age_cdata.age_parent_tag != NULL) { 1309 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1310 sc->age_cdata.age_parent_tag = NULL; 1311 } 1312 } 1313 1314 /* 1315 * Make sure the interface is stopped at reboot time. 1316 */ 1317 static int 1318 age_shutdown(device_t dev) 1319 { 1320 1321 return (age_suspend(dev)); 1322 } 1323 1324 static void 1325 age_setwol(struct age_softc *sc) 1326 { 1327 struct ifnet *ifp; 1328 struct mii_data *mii; 1329 uint32_t reg, pmcs; 1330 uint16_t pmstat; 1331 int aneg, i, pmc; 1332 1333 AGE_LOCK_ASSERT(sc); 1334 1335 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1336 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1337 /* 1338 * No PME capability, PHY power down. 1339 * XXX 1340 * Due to an unknown reason powering down PHY resulted 1341 * in unexpected results such as inaccessbility of 1342 * hardware of freshly rebooted system. Disable 1343 * powering down PHY until I got more information for 1344 * Attansic/Atheros PHY hardwares. 1345 */ 1346 #ifdef notyet 1347 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1348 MII_BMCR, BMCR_PDOWN); 1349 #endif 1350 return; 1351 } 1352 1353 ifp = sc->age_ifp; 1354 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1355 /* 1356 * Note, this driver resets the link speed to 10/100Mbps with 1357 * auto-negotiation but we don't know whether that operation 1358 * would succeed or not as it have no control after powering 1359 * off. If the renegotiation fail WOL may not work. Running 1360 * at 1Gbps will draw more power than 375mA at 3.3V which is 1361 * specified in PCI specification and that would result in 1362 * complete shutdowning power to ethernet controller. 1363 * 1364 * TODO 1365 * Save current negotiated media speed/duplex/flow-control 1366 * to softc and restore the same link again after resuming. 1367 * PHY handling such as power down/resetting to 100Mbps 1368 * may be better handled in suspend method in phy driver. 1369 */ 1370 mii = device_get_softc(sc->age_miibus); 1371 mii_pollstat(mii); 1372 aneg = 0; 1373 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1374 switch IFM_SUBTYPE(mii->mii_media_active) { 1375 case IFM_10_T: 1376 case IFM_100_TX: 1377 goto got_link; 1378 case IFM_1000_T: 1379 aneg++; 1380 default: 1381 break; 1382 } 1383 } 1384 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385 MII_100T2CR, 0); 1386 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1387 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1388 ANAR_10 | ANAR_CSMA); 1389 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1390 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1391 DELAY(1000); 1392 if (aneg != 0) { 1393 /* Poll link state until age(4) get a 10/100 link. */ 1394 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1395 mii_pollstat(mii); 1396 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1397 switch (IFM_SUBTYPE( 1398 mii->mii_media_active)) { 1399 case IFM_10_T: 1400 case IFM_100_TX: 1401 age_mac_config(sc); 1402 goto got_link; 1403 default: 1404 break; 1405 } 1406 } 1407 AGE_UNLOCK(sc); 1408 pause("agelnk", hz); 1409 AGE_LOCK(sc); 1410 } 1411 if (i == MII_ANEGTICKS_GIGE) 1412 device_printf(sc->age_dev, 1413 "establishing link failed, " 1414 "WOL may not work!"); 1415 } 1416 /* 1417 * No link, force MAC to have 100Mbps, full-duplex link. 1418 * This is the last resort and may/may not work. 1419 */ 1420 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1421 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1422 age_mac_config(sc); 1423 } 1424 1425 got_link: 1426 pmcs = 0; 1427 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1428 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1429 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1430 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1431 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1432 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1433 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1434 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1435 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1436 reg |= MAC_CFG_RX_ENB; 1437 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1438 } 1439 1440 /* Request PME. */ 1441 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1442 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1443 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1444 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1445 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1446 #ifdef notyet 1447 /* See above for powering down PHY issues. */ 1448 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1449 /* No WOL, PHY power down. */ 1450 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1451 MII_BMCR, BMCR_PDOWN); 1452 } 1453 #endif 1454 } 1455 1456 static int 1457 age_suspend(device_t dev) 1458 { 1459 struct age_softc *sc; 1460 1461 sc = device_get_softc(dev); 1462 1463 AGE_LOCK(sc); 1464 age_stop(sc); 1465 age_setwol(sc); 1466 AGE_UNLOCK(sc); 1467 1468 return (0); 1469 } 1470 1471 static int 1472 age_resume(device_t dev) 1473 { 1474 struct age_softc *sc; 1475 struct ifnet *ifp; 1476 1477 sc = device_get_softc(dev); 1478 1479 AGE_LOCK(sc); 1480 age_phy_reset(sc); 1481 ifp = sc->age_ifp; 1482 if ((ifp->if_flags & IFF_UP) != 0) 1483 age_init_locked(sc); 1484 1485 AGE_UNLOCK(sc); 1486 1487 return (0); 1488 } 1489 1490 static int 1491 age_encap(struct age_softc *sc, struct mbuf **m_head) 1492 { 1493 struct age_txdesc *txd, *txd_last; 1494 struct tx_desc *desc; 1495 struct mbuf *m; 1496 struct ip *ip; 1497 struct tcphdr *tcp; 1498 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1499 bus_dmamap_t map; 1500 uint32_t cflags, ip_off, poff, vtag; 1501 int error, i, nsegs, prod, si; 1502 1503 AGE_LOCK_ASSERT(sc); 1504 1505 M_ASSERTPKTHDR((*m_head)); 1506 1507 m = *m_head; 1508 ip = NULL; 1509 tcp = NULL; 1510 cflags = vtag = 0; 1511 ip_off = poff = 0; 1512 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1513 /* 1514 * L1 requires offset of TCP/UDP payload in its Tx 1515 * descriptor to perform hardware Tx checksum offload. 1516 * Additionally, TSO requires IP/TCP header size and 1517 * modification of IP/TCP header in order to make TSO 1518 * engine work. This kind of operation takes many CPU 1519 * cycles on FreeBSD so fast host CPU is needed to get 1520 * smooth TSO performance. 1521 */ 1522 struct ether_header *eh; 1523 1524 if (M_WRITABLE(m) == 0) { 1525 /* Get a writable copy. */ 1526 m = m_dup(*m_head, M_DONTWAIT); 1527 /* Release original mbufs. */ 1528 m_freem(*m_head); 1529 if (m == NULL) { 1530 *m_head = NULL; 1531 return (ENOBUFS); 1532 } 1533 *m_head = m; 1534 } 1535 ip_off = sizeof(struct ether_header); 1536 m = m_pullup(m, ip_off); 1537 if (m == NULL) { 1538 *m_head = NULL; 1539 return (ENOBUFS); 1540 } 1541 eh = mtod(m, struct ether_header *); 1542 /* 1543 * Check if hardware VLAN insertion is off. 1544 * Additional check for LLC/SNAP frame? 1545 */ 1546 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1547 ip_off = sizeof(struct ether_vlan_header); 1548 m = m_pullup(m, ip_off); 1549 if (m == NULL) { 1550 *m_head = NULL; 1551 return (ENOBUFS); 1552 } 1553 } 1554 m = m_pullup(m, ip_off + sizeof(struct ip)); 1555 if (m == NULL) { 1556 *m_head = NULL; 1557 return (ENOBUFS); 1558 } 1559 ip = (struct ip *)(mtod(m, char *) + ip_off); 1560 poff = ip_off + (ip->ip_hl << 2); 1561 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1562 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1563 if (m == NULL) { 1564 *m_head = NULL; 1565 return (ENOBUFS); 1566 } 1567 ip = (struct ip *)(mtod(m, char *) + ip_off); 1568 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1569 /* 1570 * L1 requires IP/TCP header size and offset as 1571 * well as TCP pseudo checksum which complicates 1572 * TSO configuration. I guess this comes from the 1573 * adherence to Microsoft NDIS Large Send 1574 * specification which requires insertion of 1575 * pseudo checksum by upper stack. The pseudo 1576 * checksum that NDIS refers to doesn't include 1577 * TCP payload length so age(4) should recompute 1578 * the pseudo checksum here. Hopefully this wouldn't 1579 * be much burden on modern CPUs. 1580 * Reset IP checksum and recompute TCP pseudo 1581 * checksum as NDIS specification said. 1582 */ 1583 ip->ip_sum = 0; 1584 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) 1585 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1586 ip->ip_dst.s_addr, 1587 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1588 else 1589 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1590 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1591 } 1592 *m_head = m; 1593 } 1594 1595 si = prod = sc->age_cdata.age_tx_prod; 1596 txd = &sc->age_cdata.age_txdesc[prod]; 1597 txd_last = txd; 1598 map = txd->tx_dmamap; 1599 1600 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1601 *m_head, txsegs, &nsegs, 0); 1602 if (error == EFBIG) { 1603 m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1604 if (m == NULL) { 1605 m_freem(*m_head); 1606 *m_head = NULL; 1607 return (ENOMEM); 1608 } 1609 *m_head = m; 1610 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1611 *m_head, txsegs, &nsegs, 0); 1612 if (error != 0) { 1613 m_freem(*m_head); 1614 *m_head = NULL; 1615 return (error); 1616 } 1617 } else if (error != 0) 1618 return (error); 1619 if (nsegs == 0) { 1620 m_freem(*m_head); 1621 *m_head = NULL; 1622 return (EIO); 1623 } 1624 1625 /* Check descriptor overrun. */ 1626 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1627 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1628 return (ENOBUFS); 1629 } 1630 1631 m = *m_head; 1632 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1633 /* Configure TSO. */ 1634 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1635 /* Not TSO but IP/TCP checksum offload. */ 1636 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1637 /* Clear TSO in order not to set AGE_TD_TSO_HDR. */ 1638 m->m_pkthdr.csum_flags &= ~CSUM_TSO; 1639 } else { 1640 /* Request TSO and set MSS. */ 1641 cflags |= AGE_TD_TSO_IPV4; 1642 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1643 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1644 AGE_TD_TSO_MSS_SHIFT); 1645 } 1646 /* Set IP/TCP header size. */ 1647 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1648 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1649 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1650 /* Configure Tx IP/TCP/UDP checksum offload. */ 1651 cflags |= AGE_TD_CSUM; 1652 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1653 cflags |= AGE_TD_TCPCSUM; 1654 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1655 cflags |= AGE_TD_UDPCSUM; 1656 /* Set checksum start offset. */ 1657 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1658 /* Set checksum insertion position of TCP/UDP. */ 1659 cflags |= ((poff + m->m_pkthdr.csum_data) << 1660 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1661 } 1662 1663 /* Configure VLAN hardware tag insertion. */ 1664 if ((m->m_flags & M_VLANTAG) != 0) { 1665 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1666 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1667 cflags |= AGE_TD_INSERT_VLAN_TAG; 1668 } 1669 1670 desc = NULL; 1671 for (i = 0; i < nsegs; i++) { 1672 desc = &sc->age_rdata.age_tx_ring[prod]; 1673 desc->addr = htole64(txsegs[i].ds_addr); 1674 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1675 desc->flags = htole32(cflags); 1676 sc->age_cdata.age_tx_cnt++; 1677 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1678 } 1679 /* Update producer index. */ 1680 sc->age_cdata.age_tx_prod = prod; 1681 1682 /* Set EOP on the last descriptor. */ 1683 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1684 desc = &sc->age_rdata.age_tx_ring[prod]; 1685 desc->flags |= htole32(AGE_TD_EOP); 1686 1687 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1688 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1689 desc = &sc->age_rdata.age_tx_ring[si]; 1690 desc->flags |= htole32(AGE_TD_TSO_HDR); 1691 } 1692 1693 /* Swap dmamap of the first and the last. */ 1694 txd = &sc->age_cdata.age_txdesc[prod]; 1695 map = txd_last->tx_dmamap; 1696 txd_last->tx_dmamap = txd->tx_dmamap; 1697 txd->tx_dmamap = map; 1698 txd->tx_m = m; 1699 1700 /* Sync descriptors. */ 1701 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1702 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1703 sc->age_cdata.age_tx_ring_map, 1704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1705 1706 return (0); 1707 } 1708 1709 static void 1710 age_start(struct ifnet *ifp) 1711 { 1712 struct age_softc *sc; 1713 1714 sc = ifp->if_softc; 1715 AGE_LOCK(sc); 1716 age_start_locked(ifp); 1717 AGE_UNLOCK(sc); 1718 } 1719 1720 static void 1721 age_start_locked(struct ifnet *ifp) 1722 { 1723 struct age_softc *sc; 1724 struct mbuf *m_head; 1725 int enq; 1726 1727 sc = ifp->if_softc; 1728 1729 AGE_LOCK_ASSERT(sc); 1730 1731 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1732 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1733 return; 1734 1735 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1736 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1737 if (m_head == NULL) 1738 break; 1739 /* 1740 * Pack the data into the transmit ring. If we 1741 * don't have room, set the OACTIVE flag and wait 1742 * for the NIC to drain the ring. 1743 */ 1744 if (age_encap(sc, &m_head)) { 1745 if (m_head == NULL) 1746 break; 1747 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1748 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1749 break; 1750 } 1751 1752 enq++; 1753 /* 1754 * If there's a BPF listener, bounce a copy of this frame 1755 * to him. 1756 */ 1757 ETHER_BPF_MTAP(ifp, m_head); 1758 } 1759 1760 if (enq > 0) { 1761 /* Update mbox. */ 1762 AGE_COMMIT_MBOX(sc); 1763 /* Set a timeout in case the chip goes out to lunch. */ 1764 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1765 } 1766 } 1767 1768 static void 1769 age_watchdog(struct age_softc *sc) 1770 { 1771 struct ifnet *ifp; 1772 1773 AGE_LOCK_ASSERT(sc); 1774 1775 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1776 return; 1777 1778 ifp = sc->age_ifp; 1779 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1780 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1781 ifp->if_oerrors++; 1782 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1783 age_init_locked(sc); 1784 return; 1785 } 1786 if (sc->age_cdata.age_tx_cnt == 0) { 1787 if_printf(sc->age_ifp, 1788 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1789 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1790 age_start_locked(ifp); 1791 return; 1792 } 1793 if_printf(sc->age_ifp, "watchdog timeout\n"); 1794 ifp->if_oerrors++; 1795 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1796 age_init_locked(sc); 1797 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1798 age_start_locked(ifp); 1799 } 1800 1801 static int 1802 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1803 { 1804 struct age_softc *sc; 1805 struct ifreq *ifr; 1806 struct mii_data *mii; 1807 uint32_t reg; 1808 int error, mask; 1809 1810 sc = ifp->if_softc; 1811 ifr = (struct ifreq *)data; 1812 error = 0; 1813 switch (cmd) { 1814 case SIOCSIFMTU: 1815 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1816 error = EINVAL; 1817 else if (ifp->if_mtu != ifr->ifr_mtu) { 1818 AGE_LOCK(sc); 1819 ifp->if_mtu = ifr->ifr_mtu; 1820 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1821 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1822 age_init_locked(sc); 1823 } 1824 AGE_UNLOCK(sc); 1825 } 1826 break; 1827 case SIOCSIFFLAGS: 1828 AGE_LOCK(sc); 1829 if ((ifp->if_flags & IFF_UP) != 0) { 1830 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1831 if (((ifp->if_flags ^ sc->age_if_flags) 1832 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1833 age_rxfilter(sc); 1834 } else { 1835 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1836 age_init_locked(sc); 1837 } 1838 } else { 1839 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1840 age_stop(sc); 1841 } 1842 sc->age_if_flags = ifp->if_flags; 1843 AGE_UNLOCK(sc); 1844 break; 1845 case SIOCADDMULTI: 1846 case SIOCDELMULTI: 1847 AGE_LOCK(sc); 1848 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1849 age_rxfilter(sc); 1850 AGE_UNLOCK(sc); 1851 break; 1852 case SIOCSIFMEDIA: 1853 case SIOCGIFMEDIA: 1854 mii = device_get_softc(sc->age_miibus); 1855 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1856 break; 1857 case SIOCSIFCAP: 1858 AGE_LOCK(sc); 1859 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1860 if ((mask & IFCAP_TXCSUM) != 0 && 1861 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1862 ifp->if_capenable ^= IFCAP_TXCSUM; 1863 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1864 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1865 else 1866 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1867 } 1868 if ((mask & IFCAP_RXCSUM) != 0 && 1869 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1870 ifp->if_capenable ^= IFCAP_RXCSUM; 1871 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1872 reg &= ~MAC_CFG_RXCSUM_ENB; 1873 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1874 reg |= MAC_CFG_RXCSUM_ENB; 1875 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1876 } 1877 if ((mask & IFCAP_TSO4) != 0 && 1878 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1879 ifp->if_capenable ^= IFCAP_TSO4; 1880 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1881 ifp->if_hwassist |= CSUM_TSO; 1882 else 1883 ifp->if_hwassist &= ~CSUM_TSO; 1884 } 1885 1886 if ((mask & IFCAP_WOL_MCAST) != 0 && 1887 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1888 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1889 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1890 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1891 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1892 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1893 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1894 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1895 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1896 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1897 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1898 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1899 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1900 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1901 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1902 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1903 age_rxvlan(sc); 1904 } 1905 AGE_UNLOCK(sc); 1906 VLAN_CAPABILITIES(ifp); 1907 break; 1908 default: 1909 error = ether_ioctl(ifp, cmd, data); 1910 break; 1911 } 1912 1913 return (error); 1914 } 1915 1916 static void 1917 age_mac_config(struct age_softc *sc) 1918 { 1919 struct mii_data *mii; 1920 uint32_t reg; 1921 1922 AGE_LOCK_ASSERT(sc); 1923 1924 mii = device_get_softc(sc->age_miibus); 1925 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1926 reg &= ~MAC_CFG_FULL_DUPLEX; 1927 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1928 reg &= ~MAC_CFG_SPEED_MASK; 1929 /* Reprogram MAC with resolved speed/duplex. */ 1930 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1931 case IFM_10_T: 1932 case IFM_100_TX: 1933 reg |= MAC_CFG_SPEED_10_100; 1934 break; 1935 case IFM_1000_T: 1936 reg |= MAC_CFG_SPEED_1000; 1937 break; 1938 } 1939 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1940 reg |= MAC_CFG_FULL_DUPLEX; 1941 #ifdef notyet 1942 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1943 reg |= MAC_CFG_TX_FC; 1944 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1945 reg |= MAC_CFG_RX_FC; 1946 #endif 1947 } 1948 1949 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1950 } 1951 1952 static void 1953 age_link_task(void *arg, int pending) 1954 { 1955 struct age_softc *sc; 1956 struct mii_data *mii; 1957 struct ifnet *ifp; 1958 uint32_t reg; 1959 1960 sc = (struct age_softc *)arg; 1961 1962 AGE_LOCK(sc); 1963 mii = device_get_softc(sc->age_miibus); 1964 ifp = sc->age_ifp; 1965 if (mii == NULL || ifp == NULL || 1966 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1967 AGE_UNLOCK(sc); 1968 return; 1969 } 1970 1971 sc->age_flags &= ~AGE_FLAG_LINK; 1972 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1973 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1974 case IFM_10_T: 1975 case IFM_100_TX: 1976 case IFM_1000_T: 1977 sc->age_flags |= AGE_FLAG_LINK; 1978 break; 1979 default: 1980 break; 1981 } 1982 } 1983 1984 /* Stop Rx/Tx MACs. */ 1985 age_stop_rxmac(sc); 1986 age_stop_txmac(sc); 1987 1988 /* Program MACs with resolved speed/duplex/flow-control. */ 1989 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1990 age_mac_config(sc); 1991 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1992 /* Restart DMA engine and Tx/Rx MAC. */ 1993 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1994 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1995 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1996 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1997 } 1998 1999 AGE_UNLOCK(sc); 2000 } 2001 2002 static void 2003 age_stats_update(struct age_softc *sc) 2004 { 2005 struct age_stats *stat; 2006 struct smb *smb; 2007 struct ifnet *ifp; 2008 2009 AGE_LOCK_ASSERT(sc); 2010 2011 stat = &sc->age_stat; 2012 2013 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2014 sc->age_cdata.age_smb_block_map, 2015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2016 2017 smb = sc->age_rdata.age_smb_block; 2018 if (smb->updated == 0) 2019 return; 2020 2021 ifp = sc->age_ifp; 2022 /* Rx stats. */ 2023 stat->rx_frames += smb->rx_frames; 2024 stat->rx_bcast_frames += smb->rx_bcast_frames; 2025 stat->rx_mcast_frames += smb->rx_mcast_frames; 2026 stat->rx_pause_frames += smb->rx_pause_frames; 2027 stat->rx_control_frames += smb->rx_control_frames; 2028 stat->rx_crcerrs += smb->rx_crcerrs; 2029 stat->rx_lenerrs += smb->rx_lenerrs; 2030 stat->rx_bytes += smb->rx_bytes; 2031 stat->rx_runts += smb->rx_runts; 2032 stat->rx_fragments += smb->rx_fragments; 2033 stat->rx_pkts_64 += smb->rx_pkts_64; 2034 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2035 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2036 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2037 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2038 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2039 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2040 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2041 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2042 stat->rx_desc_oflows += smb->rx_desc_oflows; 2043 stat->rx_alignerrs += smb->rx_alignerrs; 2044 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2045 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2046 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2047 2048 /* Tx stats. */ 2049 stat->tx_frames += smb->tx_frames; 2050 stat->tx_bcast_frames += smb->tx_bcast_frames; 2051 stat->tx_mcast_frames += smb->tx_mcast_frames; 2052 stat->tx_pause_frames += smb->tx_pause_frames; 2053 stat->tx_excess_defer += smb->tx_excess_defer; 2054 stat->tx_control_frames += smb->tx_control_frames; 2055 stat->tx_deferred += smb->tx_deferred; 2056 stat->tx_bytes += smb->tx_bytes; 2057 stat->tx_pkts_64 += smb->tx_pkts_64; 2058 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2059 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2060 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2061 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2062 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2063 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2064 stat->tx_single_colls += smb->tx_single_colls; 2065 stat->tx_multi_colls += smb->tx_multi_colls; 2066 stat->tx_late_colls += smb->tx_late_colls; 2067 stat->tx_excess_colls += smb->tx_excess_colls; 2068 stat->tx_underrun += smb->tx_underrun; 2069 stat->tx_desc_underrun += smb->tx_desc_underrun; 2070 stat->tx_lenerrs += smb->tx_lenerrs; 2071 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2072 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2073 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2074 2075 /* Update counters in ifnet. */ 2076 ifp->if_opackets += smb->tx_frames; 2077 2078 ifp->if_collisions += smb->tx_single_colls + 2079 smb->tx_multi_colls + smb->tx_late_colls + 2080 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2081 2082 ifp->if_oerrors += smb->tx_excess_colls + 2083 smb->tx_late_colls + smb->tx_underrun + 2084 smb->tx_pkts_truncated; 2085 2086 ifp->if_ipackets += smb->rx_frames; 2087 2088 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2089 smb->rx_runts + smb->rx_pkts_truncated + 2090 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2091 smb->rx_alignerrs; 2092 2093 /* Update done, clear. */ 2094 smb->updated = 0; 2095 2096 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2097 sc->age_cdata.age_smb_block_map, 2098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2099 } 2100 2101 static int 2102 age_intr(void *arg) 2103 { 2104 struct age_softc *sc; 2105 uint32_t status; 2106 2107 sc = (struct age_softc *)arg; 2108 2109 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2110 if (status == 0 || (status & AGE_INTRS) == 0) 2111 return (FILTER_STRAY); 2112 /* Disable interrupts. */ 2113 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2114 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2115 2116 return (FILTER_HANDLED); 2117 } 2118 2119 static void 2120 age_int_task(void *arg, int pending) 2121 { 2122 struct age_softc *sc; 2123 struct ifnet *ifp; 2124 struct cmb *cmb; 2125 uint32_t status; 2126 2127 sc = (struct age_softc *)arg; 2128 2129 AGE_LOCK(sc); 2130 2131 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2132 sc->age_cdata.age_cmb_block_map, 2133 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2134 cmb = sc->age_rdata.age_cmb_block; 2135 status = le32toh(cmb->intr_status); 2136 if (sc->age_morework != 0) 2137 status |= INTR_CMB_RX; 2138 if ((status & AGE_INTRS) == 0) 2139 goto done; 2140 2141 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2142 TPD_CONS_SHIFT; 2143 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2144 RRD_PROD_SHIFT; 2145 /* Let hardware know CMB was served. */ 2146 cmb->intr_status = 0; 2147 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2148 sc->age_cdata.age_cmb_block_map, 2149 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2150 2151 #if 0 2152 printf("INTR: 0x%08x\n", status); 2153 status &= ~INTR_DIS_DMA; 2154 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2155 #endif 2156 ifp = sc->age_ifp; 2157 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2158 if ((status & INTR_CMB_RX) != 0) 2159 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2160 sc->age_process_limit); 2161 if ((status & INTR_CMB_TX) != 0) 2162 age_txintr(sc, sc->age_tpd_cons); 2163 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2164 if ((status & INTR_DMA_RD_TO_RST) != 0) 2165 device_printf(sc->age_dev, 2166 "DMA read error! -- resetting\n"); 2167 if ((status & INTR_DMA_WR_TO_RST) != 0) 2168 device_printf(sc->age_dev, 2169 "DMA write error! -- resetting\n"); 2170 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2171 age_init_locked(sc); 2172 } 2173 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2174 age_start_locked(ifp); 2175 if ((status & INTR_SMB) != 0) 2176 age_stats_update(sc); 2177 } 2178 2179 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2180 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2181 sc->age_cdata.age_cmb_block_map, 2182 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2183 status = le32toh(cmb->intr_status); 2184 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2185 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2186 AGE_UNLOCK(sc); 2187 return; 2188 } 2189 2190 done: 2191 /* Re-enable interrupts. */ 2192 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2193 AGE_UNLOCK(sc); 2194 } 2195 2196 static void 2197 age_txintr(struct age_softc *sc, int tpd_cons) 2198 { 2199 struct ifnet *ifp; 2200 struct age_txdesc *txd; 2201 int cons, prog; 2202 2203 AGE_LOCK_ASSERT(sc); 2204 2205 ifp = sc->age_ifp; 2206 2207 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2208 sc->age_cdata.age_tx_ring_map, 2209 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2210 2211 /* 2212 * Go through our Tx list and free mbufs for those 2213 * frames which have been transmitted. 2214 */ 2215 cons = sc->age_cdata.age_tx_cons; 2216 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2217 if (sc->age_cdata.age_tx_cnt <= 0) 2218 break; 2219 prog++; 2220 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2221 sc->age_cdata.age_tx_cnt--; 2222 txd = &sc->age_cdata.age_txdesc[cons]; 2223 /* 2224 * Clear Tx descriptors, it's not required but would 2225 * help debugging in case of Tx issues. 2226 */ 2227 txd->tx_desc->addr = 0; 2228 txd->tx_desc->len = 0; 2229 txd->tx_desc->flags = 0; 2230 2231 if (txd->tx_m == NULL) 2232 continue; 2233 /* Reclaim transmitted mbufs. */ 2234 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2235 BUS_DMASYNC_POSTWRITE); 2236 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2237 m_freem(txd->tx_m); 2238 txd->tx_m = NULL; 2239 } 2240 2241 if (prog > 0) { 2242 sc->age_cdata.age_tx_cons = cons; 2243 2244 /* 2245 * Unarm watchdog timer only when there are no pending 2246 * Tx descriptors in queue. 2247 */ 2248 if (sc->age_cdata.age_tx_cnt == 0) 2249 sc->age_watchdog_timer = 0; 2250 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2251 sc->age_cdata.age_tx_ring_map, 2252 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2253 } 2254 } 2255 2256 /* Receive a frame. */ 2257 static void 2258 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2259 { 2260 struct age_rxdesc *rxd; 2261 struct rx_desc *desc; 2262 struct ifnet *ifp; 2263 struct mbuf *mp, *m; 2264 uint32_t status, index, vtag; 2265 int count, nsegs, pktlen; 2266 int rx_cons; 2267 2268 AGE_LOCK_ASSERT(sc); 2269 2270 ifp = sc->age_ifp; 2271 status = le32toh(rxrd->flags); 2272 index = le32toh(rxrd->index); 2273 rx_cons = AGE_RX_CONS(index); 2274 nsegs = AGE_RX_NSEGS(index); 2275 2276 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2277 if ((status & AGE_RRD_ERROR) != 0 && 2278 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2279 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2280 /* 2281 * We want to pass the following frames to upper 2282 * layer regardless of error status of Rx return 2283 * ring. 2284 * 2285 * o IP/TCP/UDP checksum is bad. 2286 * o frame length and protocol specific length 2287 * does not match. 2288 */ 2289 sc->age_cdata.age_rx_cons += nsegs; 2290 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2291 return; 2292 } 2293 2294 pktlen = 0; 2295 for (count = 0; count < nsegs; count++, 2296 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2297 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2298 mp = rxd->rx_m; 2299 desc = rxd->rx_desc; 2300 /* Add a new receive buffer to the ring. */ 2301 if (age_newbuf(sc, rxd) != 0) { 2302 ifp->if_iqdrops++; 2303 /* Reuse Rx buffers. */ 2304 if (sc->age_cdata.age_rxhead != NULL) { 2305 m_freem(sc->age_cdata.age_rxhead); 2306 AGE_RXCHAIN_RESET(sc); 2307 } 2308 break; 2309 } 2310 2311 /* The length of the first mbuf is computed last. */ 2312 if (count != 0) { 2313 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2314 pktlen += mp->m_len; 2315 } 2316 2317 /* Chain received mbufs. */ 2318 if (sc->age_cdata.age_rxhead == NULL) { 2319 sc->age_cdata.age_rxhead = mp; 2320 sc->age_cdata.age_rxtail = mp; 2321 } else { 2322 mp->m_flags &= ~M_PKTHDR; 2323 sc->age_cdata.age_rxprev_tail = 2324 sc->age_cdata.age_rxtail; 2325 sc->age_cdata.age_rxtail->m_next = mp; 2326 sc->age_cdata.age_rxtail = mp; 2327 } 2328 2329 if (count == nsegs - 1) { 2330 /* 2331 * It seems that L1 controller has no way 2332 * to tell hardware to strip CRC bytes. 2333 */ 2334 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2335 if (nsegs > 1) { 2336 /* Remove the CRC bytes in chained mbufs. */ 2337 pktlen -= ETHER_CRC_LEN; 2338 if (mp->m_len <= ETHER_CRC_LEN) { 2339 sc->age_cdata.age_rxtail = 2340 sc->age_cdata.age_rxprev_tail; 2341 sc->age_cdata.age_rxtail->m_len -= 2342 (ETHER_CRC_LEN - mp->m_len); 2343 sc->age_cdata.age_rxtail->m_next = NULL; 2344 m_freem(mp); 2345 } else { 2346 mp->m_len -= ETHER_CRC_LEN; 2347 } 2348 } 2349 2350 m = sc->age_cdata.age_rxhead; 2351 m->m_flags |= M_PKTHDR; 2352 m->m_pkthdr.rcvif = ifp; 2353 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2354 /* Set the first mbuf length. */ 2355 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2356 2357 /* 2358 * Set checksum information. 2359 * It seems that L1 controller can compute partial 2360 * checksum. The partial checksum value can be used 2361 * to accelerate checksum computation for fragmented 2362 * TCP/UDP packets. Upper network stack already 2363 * takes advantage of the partial checksum value in 2364 * IP reassembly stage. But I'm not sure the 2365 * correctness of the partial hardware checksum 2366 * assistance due to lack of data sheet. If it is 2367 * proven to work on L1 I'll enable it. 2368 */ 2369 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2370 (status & AGE_RRD_IPV4) != 0) { 2371 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2372 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2373 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2374 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2375 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2376 m->m_pkthdr.csum_flags |= 2377 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2378 m->m_pkthdr.csum_data = 0xffff; 2379 } 2380 /* 2381 * Don't mark bad checksum for TCP/UDP frames 2382 * as fragmented frames may always have set 2383 * bad checksummed bit of descriptor status. 2384 */ 2385 } 2386 2387 /* Check for VLAN tagged frames. */ 2388 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2389 (status & AGE_RRD_VLAN) != 0) { 2390 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2391 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2392 m->m_flags |= M_VLANTAG; 2393 } 2394 2395 /* Pass it on. */ 2396 AGE_UNLOCK(sc); 2397 (*ifp->if_input)(ifp, m); 2398 AGE_LOCK(sc); 2399 2400 /* Reset mbuf chains. */ 2401 AGE_RXCHAIN_RESET(sc); 2402 } 2403 } 2404 2405 if (count != nsegs) { 2406 sc->age_cdata.age_rx_cons += nsegs; 2407 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2408 } else 2409 sc->age_cdata.age_rx_cons = rx_cons; 2410 } 2411 2412 static int 2413 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2414 { 2415 struct rx_rdesc *rxrd; 2416 int rr_cons, nsegs, pktlen, prog; 2417 2418 AGE_LOCK_ASSERT(sc); 2419 2420 rr_cons = sc->age_cdata.age_rr_cons; 2421 if (rr_cons == rr_prod) 2422 return (0); 2423 2424 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2425 sc->age_cdata.age_rr_ring_map, 2426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2427 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2428 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2429 2430 for (prog = 0; rr_cons != rr_prod; prog++) { 2431 if (count <= 0) 2432 break; 2433 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2434 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2435 if (nsegs == 0) 2436 break; 2437 /* 2438 * Check number of segments against received bytes. 2439 * Non-matching value would indicate that hardware 2440 * is still trying to update Rx return descriptors. 2441 * I'm not sure whether this check is really needed. 2442 */ 2443 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2444 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2445 (MCLBYTES - ETHER_ALIGN))) 2446 break; 2447 2448 prog++; 2449 /* Received a frame. */ 2450 age_rxeof(sc, rxrd); 2451 /* Clear return ring. */ 2452 rxrd->index = 0; 2453 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2454 } 2455 2456 if (prog > 0) { 2457 /* Update the consumer index. */ 2458 sc->age_cdata.age_rr_cons = rr_cons; 2459 2460 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2461 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2462 /* Sync descriptors. */ 2463 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2464 sc->age_cdata.age_rr_ring_map, 2465 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2466 2467 /* Notify hardware availability of new Rx buffers. */ 2468 AGE_COMMIT_MBOX(sc); 2469 } 2470 2471 return (count > 0 ? 0 : EAGAIN); 2472 } 2473 2474 static void 2475 age_tick(void *arg) 2476 { 2477 struct age_softc *sc; 2478 struct mii_data *mii; 2479 2480 sc = (struct age_softc *)arg; 2481 2482 AGE_LOCK_ASSERT(sc); 2483 2484 mii = device_get_softc(sc->age_miibus); 2485 mii_tick(mii); 2486 age_watchdog(sc); 2487 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2488 } 2489 2490 static void 2491 age_reset(struct age_softc *sc) 2492 { 2493 uint32_t reg; 2494 int i; 2495 2496 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2497 CSR_READ_4(sc, AGE_MASTER_CFG); 2498 DELAY(1000); 2499 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2500 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2501 break; 2502 DELAY(10); 2503 } 2504 2505 if (i == 0) 2506 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2507 /* Initialize PCIe module. From Linux. */ 2508 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2509 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2510 } 2511 2512 static void 2513 age_init(void *xsc) 2514 { 2515 struct age_softc *sc; 2516 2517 sc = (struct age_softc *)xsc; 2518 AGE_LOCK(sc); 2519 age_init_locked(sc); 2520 AGE_UNLOCK(sc); 2521 } 2522 2523 static void 2524 age_init_locked(struct age_softc *sc) 2525 { 2526 struct ifnet *ifp; 2527 struct mii_data *mii; 2528 uint8_t eaddr[ETHER_ADDR_LEN]; 2529 bus_addr_t paddr; 2530 uint32_t reg, fsize; 2531 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2532 int error; 2533 2534 AGE_LOCK_ASSERT(sc); 2535 2536 ifp = sc->age_ifp; 2537 mii = device_get_softc(sc->age_miibus); 2538 2539 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2540 return; 2541 2542 /* 2543 * Cancel any pending I/O. 2544 */ 2545 age_stop(sc); 2546 2547 /* 2548 * Reset the chip to a known state. 2549 */ 2550 age_reset(sc); 2551 2552 /* Initialize descriptors. */ 2553 error = age_init_rx_ring(sc); 2554 if (error != 0) { 2555 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2556 age_stop(sc); 2557 return; 2558 } 2559 age_init_rr_ring(sc); 2560 age_init_tx_ring(sc); 2561 age_init_cmb_block(sc); 2562 age_init_smb_block(sc); 2563 2564 /* Reprogram the station address. */ 2565 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2566 CSR_WRITE_4(sc, AGE_PAR0, 2567 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2568 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2569 2570 /* Set descriptor base addresses. */ 2571 paddr = sc->age_rdata.age_tx_ring_paddr; 2572 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2573 paddr = sc->age_rdata.age_rx_ring_paddr; 2574 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2575 paddr = sc->age_rdata.age_rr_ring_paddr; 2576 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2577 paddr = sc->age_rdata.age_tx_ring_paddr; 2578 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2579 paddr = sc->age_rdata.age_cmb_block_paddr; 2580 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2581 paddr = sc->age_rdata.age_smb_block_paddr; 2582 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2583 /* Set Rx/Rx return descriptor counter. */ 2584 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2585 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2586 DESC_RRD_CNT_MASK) | 2587 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2588 /* Set Tx descriptor counter. */ 2589 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2590 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2591 2592 /* Tell hardware that we're ready to load descriptors. */ 2593 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2594 2595 /* 2596 * Initialize mailbox register. 2597 * Updated producer/consumer index information is exchanged 2598 * through this mailbox register. However Tx producer and 2599 * Rx return consumer/Rx producer are all shared such that 2600 * it's hard to separate code path between Tx and Rx without 2601 * locking. If L1 hardware have a separate mail box register 2602 * for Tx and Rx consumer/producer management we could have 2603 * indepent Tx/Rx handler which in turn Rx handler could have 2604 * been run without any locking. 2605 */ 2606 AGE_COMMIT_MBOX(sc); 2607 2608 /* Configure IPG/IFG parameters. */ 2609 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2610 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2611 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2612 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2613 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2614 2615 /* Set parameters for half-duplex media. */ 2616 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2617 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2618 HDPX_CFG_LCOL_MASK) | 2619 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2620 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2621 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2622 HDPX_CFG_ABEBT_MASK) | 2623 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2624 HDPX_CFG_JAMIPG_MASK)); 2625 2626 /* Configure interrupt moderation timer. */ 2627 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2628 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2629 reg &= ~MASTER_MTIMER_ENB; 2630 if (AGE_USECS(sc->age_int_mod) == 0) 2631 reg &= ~MASTER_ITIMER_ENB; 2632 else 2633 reg |= MASTER_ITIMER_ENB; 2634 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2635 if (bootverbose) 2636 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2637 sc->age_int_mod); 2638 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2639 2640 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2641 if (ifp->if_mtu < ETHERMTU) 2642 sc->age_max_frame_size = ETHERMTU; 2643 else 2644 sc->age_max_frame_size = ifp->if_mtu; 2645 sc->age_max_frame_size += ETHER_HDR_LEN + 2646 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2647 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2648 /* Configure jumbo frame. */ 2649 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2650 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2651 (((fsize / sizeof(uint64_t)) << 2652 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2653 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2654 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2655 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2656 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2657 2658 /* Configure flow-control parameters. From Linux. */ 2659 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2660 /* 2661 * Magic workaround for old-L1. 2662 * Don't know which hw revision requires this magic. 2663 */ 2664 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2665 /* 2666 * Another magic workaround for flow-control mode 2667 * change. From Linux. 2668 */ 2669 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2670 } 2671 /* 2672 * TODO 2673 * Should understand pause parameter relationships between FIFO 2674 * size and number of Rx descriptors and Rx return descriptors. 2675 * 2676 * Magic parameters came from Linux. 2677 */ 2678 switch (sc->age_chip_rev) { 2679 case 0x8001: 2680 case 0x9001: 2681 case 0x9002: 2682 case 0x9003: 2683 rxf_hi = AGE_RX_RING_CNT / 16; 2684 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2685 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2686 rrd_lo = AGE_RR_RING_CNT / 16; 2687 break; 2688 default: 2689 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2690 rxf_lo = reg / 16; 2691 if (rxf_lo < 192) 2692 rxf_lo = 192; 2693 rxf_hi = (reg * 7) / 8; 2694 if (rxf_hi < rxf_lo) 2695 rxf_hi = rxf_lo + 16; 2696 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2697 rrd_lo = reg / 8; 2698 rrd_hi = (reg * 7) / 8; 2699 if (rrd_lo < 2) 2700 rrd_lo = 2; 2701 if (rrd_hi < rrd_lo) 2702 rrd_hi = rrd_lo + 3; 2703 break; 2704 } 2705 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2706 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2707 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2708 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2709 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2710 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2711 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2712 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2713 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2714 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2715 2716 /* Configure RxQ. */ 2717 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2718 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2719 RXQ_CFG_RD_BURST_MASK) | 2720 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2721 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2722 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2723 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2724 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2725 2726 /* Configure TxQ. */ 2727 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2728 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2729 TXQ_CFG_TPD_BURST_MASK) | 2730 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2731 TXQ_CFG_TX_FIFO_BURST_MASK) | 2732 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2733 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2734 TXQ_CFG_ENB); 2735 2736 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2737 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2738 TX_JUMBO_TPD_TH_MASK) | 2739 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2740 TX_JUMBO_TPD_IPG_MASK)); 2741 /* Configure DMA parameters. */ 2742 CSR_WRITE_4(sc, AGE_DMA_CFG, 2743 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2744 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2745 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2746 2747 /* Configure CMB DMA write threshold. */ 2748 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2749 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2750 CMB_WR_THRESH_RRD_MASK) | 2751 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2752 CMB_WR_THRESH_TPD_MASK)); 2753 2754 /* Set CMB/SMB timer and enable them. */ 2755 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2756 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2757 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2758 /* Request SMB updates for every seconds. */ 2759 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2760 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2761 2762 /* 2763 * Disable all WOL bits as WOL can interfere normal Rx 2764 * operation. 2765 */ 2766 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2767 2768 /* 2769 * Configure Tx/Rx MACs. 2770 * - Auto-padding for short frames. 2771 * - Enable CRC generation. 2772 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2773 * of MAC is followed after link establishment. 2774 */ 2775 CSR_WRITE_4(sc, AGE_MAC_CFG, 2776 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2777 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2778 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2779 MAC_CFG_PREAMBLE_MASK)); 2780 /* Set up the receive filter. */ 2781 age_rxfilter(sc); 2782 age_rxvlan(sc); 2783 2784 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2785 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2786 reg |= MAC_CFG_RXCSUM_ENB; 2787 2788 /* Ack all pending interrupts and clear it. */ 2789 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2790 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2791 2792 /* Finally enable Tx/Rx MAC. */ 2793 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2794 2795 sc->age_flags &= ~AGE_FLAG_LINK; 2796 /* Switch to the current media. */ 2797 mii_mediachg(mii); 2798 2799 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2800 2801 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2802 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2803 } 2804 2805 static void 2806 age_stop(struct age_softc *sc) 2807 { 2808 struct ifnet *ifp; 2809 struct age_txdesc *txd; 2810 struct age_rxdesc *rxd; 2811 uint32_t reg; 2812 int i; 2813 2814 AGE_LOCK_ASSERT(sc); 2815 /* 2816 * Mark the interface down and cancel the watchdog timer. 2817 */ 2818 ifp = sc->age_ifp; 2819 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2820 sc->age_flags &= ~AGE_FLAG_LINK; 2821 callout_stop(&sc->age_tick_ch); 2822 sc->age_watchdog_timer = 0; 2823 2824 /* 2825 * Disable interrupts. 2826 */ 2827 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2828 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2829 /* Stop CMB/SMB updates. */ 2830 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2831 /* Stop Rx/Tx MAC. */ 2832 age_stop_rxmac(sc); 2833 age_stop_txmac(sc); 2834 /* Stop DMA. */ 2835 CSR_WRITE_4(sc, AGE_DMA_CFG, 2836 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2837 /* Stop TxQ/RxQ. */ 2838 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2839 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2840 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2841 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2842 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2843 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2844 break; 2845 DELAY(10); 2846 } 2847 if (i == 0) 2848 device_printf(sc->age_dev, 2849 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2850 2851 /* Reclaim Rx buffers that have been processed. */ 2852 if (sc->age_cdata.age_rxhead != NULL) 2853 m_freem(sc->age_cdata.age_rxhead); 2854 AGE_RXCHAIN_RESET(sc); 2855 /* 2856 * Free RX and TX mbufs still in the queues. 2857 */ 2858 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2859 rxd = &sc->age_cdata.age_rxdesc[i]; 2860 if (rxd->rx_m != NULL) { 2861 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2862 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2863 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2864 rxd->rx_dmamap); 2865 m_freem(rxd->rx_m); 2866 rxd->rx_m = NULL; 2867 } 2868 } 2869 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2870 txd = &sc->age_cdata.age_txdesc[i]; 2871 if (txd->tx_m != NULL) { 2872 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2873 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2874 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2875 txd->tx_dmamap); 2876 m_freem(txd->tx_m); 2877 txd->tx_m = NULL; 2878 } 2879 } 2880 } 2881 2882 static void 2883 age_stop_txmac(struct age_softc *sc) 2884 { 2885 uint32_t reg; 2886 int i; 2887 2888 AGE_LOCK_ASSERT(sc); 2889 2890 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2891 if ((reg & MAC_CFG_TX_ENB) != 0) { 2892 reg &= ~MAC_CFG_TX_ENB; 2893 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2894 } 2895 /* Stop Tx DMA engine. */ 2896 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2897 if ((reg & DMA_CFG_RD_ENB) != 0) { 2898 reg &= ~DMA_CFG_RD_ENB; 2899 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2900 } 2901 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2902 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2903 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2904 break; 2905 DELAY(10); 2906 } 2907 if (i == 0) 2908 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2909 } 2910 2911 static void 2912 age_stop_rxmac(struct age_softc *sc) 2913 { 2914 uint32_t reg; 2915 int i; 2916 2917 AGE_LOCK_ASSERT(sc); 2918 2919 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2920 if ((reg & MAC_CFG_RX_ENB) != 0) { 2921 reg &= ~MAC_CFG_RX_ENB; 2922 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2923 } 2924 /* Stop Rx DMA engine. */ 2925 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2926 if ((reg & DMA_CFG_WR_ENB) != 0) { 2927 reg &= ~DMA_CFG_WR_ENB; 2928 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2929 } 2930 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2931 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2932 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2933 break; 2934 DELAY(10); 2935 } 2936 if (i == 0) 2937 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2938 } 2939 2940 static void 2941 age_init_tx_ring(struct age_softc *sc) 2942 { 2943 struct age_ring_data *rd; 2944 struct age_txdesc *txd; 2945 int i; 2946 2947 AGE_LOCK_ASSERT(sc); 2948 2949 sc->age_cdata.age_tx_prod = 0; 2950 sc->age_cdata.age_tx_cons = 0; 2951 sc->age_cdata.age_tx_cnt = 0; 2952 2953 rd = &sc->age_rdata; 2954 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2955 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2956 txd = &sc->age_cdata.age_txdesc[i]; 2957 txd->tx_desc = &rd->age_tx_ring[i]; 2958 txd->tx_m = NULL; 2959 } 2960 2961 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2962 sc->age_cdata.age_tx_ring_map, 2963 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2964 } 2965 2966 static int 2967 age_init_rx_ring(struct age_softc *sc) 2968 { 2969 struct age_ring_data *rd; 2970 struct age_rxdesc *rxd; 2971 int i; 2972 2973 AGE_LOCK_ASSERT(sc); 2974 2975 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2976 sc->age_morework = 0; 2977 rd = &sc->age_rdata; 2978 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2979 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2980 rxd = &sc->age_cdata.age_rxdesc[i]; 2981 rxd->rx_m = NULL; 2982 rxd->rx_desc = &rd->age_rx_ring[i]; 2983 if (age_newbuf(sc, rxd) != 0) 2984 return (ENOBUFS); 2985 } 2986 2987 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2988 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2989 2990 return (0); 2991 } 2992 2993 static void 2994 age_init_rr_ring(struct age_softc *sc) 2995 { 2996 struct age_ring_data *rd; 2997 2998 AGE_LOCK_ASSERT(sc); 2999 3000 sc->age_cdata.age_rr_cons = 0; 3001 AGE_RXCHAIN_RESET(sc); 3002 3003 rd = &sc->age_rdata; 3004 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3005 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3006 sc->age_cdata.age_rr_ring_map, 3007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3008 } 3009 3010 static void 3011 age_init_cmb_block(struct age_softc *sc) 3012 { 3013 struct age_ring_data *rd; 3014 3015 AGE_LOCK_ASSERT(sc); 3016 3017 rd = &sc->age_rdata; 3018 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3019 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3020 sc->age_cdata.age_cmb_block_map, 3021 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3022 } 3023 3024 static void 3025 age_init_smb_block(struct age_softc *sc) 3026 { 3027 struct age_ring_data *rd; 3028 3029 AGE_LOCK_ASSERT(sc); 3030 3031 rd = &sc->age_rdata; 3032 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3033 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3034 sc->age_cdata.age_smb_block_map, 3035 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3036 } 3037 3038 static int 3039 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3040 { 3041 struct rx_desc *desc; 3042 struct mbuf *m; 3043 bus_dma_segment_t segs[1]; 3044 bus_dmamap_t map; 3045 int nsegs; 3046 3047 AGE_LOCK_ASSERT(sc); 3048 3049 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3050 if (m == NULL) 3051 return (ENOBUFS); 3052 m->m_len = m->m_pkthdr.len = MCLBYTES; 3053 m_adj(m, ETHER_ALIGN); 3054 3055 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3056 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3057 m_freem(m); 3058 return (ENOBUFS); 3059 } 3060 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3061 3062 if (rxd->rx_m != NULL) { 3063 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3064 BUS_DMASYNC_POSTREAD); 3065 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3066 } 3067 map = rxd->rx_dmamap; 3068 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3069 sc->age_cdata.age_rx_sparemap = map; 3070 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3071 BUS_DMASYNC_PREREAD); 3072 rxd->rx_m = m; 3073 3074 desc = rxd->rx_desc; 3075 desc->addr = htole64(segs[0].ds_addr); 3076 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3077 AGE_RD_LEN_SHIFT); 3078 return (0); 3079 } 3080 3081 static void 3082 age_rxvlan(struct age_softc *sc) 3083 { 3084 struct ifnet *ifp; 3085 uint32_t reg; 3086 3087 AGE_LOCK_ASSERT(sc); 3088 3089 ifp = sc->age_ifp; 3090 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3091 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3092 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3093 reg |= MAC_CFG_VLAN_TAG_STRIP; 3094 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3095 } 3096 3097 static void 3098 age_rxfilter(struct age_softc *sc) 3099 { 3100 struct ifnet *ifp; 3101 struct ifmultiaddr *ifma; 3102 uint32_t crc; 3103 uint32_t mchash[2]; 3104 uint32_t rxcfg; 3105 3106 AGE_LOCK_ASSERT(sc); 3107 3108 ifp = sc->age_ifp; 3109 3110 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3111 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3112 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3113 rxcfg |= MAC_CFG_BCAST; 3114 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3115 if ((ifp->if_flags & IFF_PROMISC) != 0) 3116 rxcfg |= MAC_CFG_PROMISC; 3117 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3118 rxcfg |= MAC_CFG_ALLMULTI; 3119 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3120 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3121 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3122 return; 3123 } 3124 3125 /* Program new filter. */ 3126 bzero(mchash, sizeof(mchash)); 3127 3128 if_maddr_rlock(ifp); 3129 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3130 if (ifma->ifma_addr->sa_family != AF_LINK) 3131 continue; 3132 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3133 ifma->ifma_addr), ETHER_ADDR_LEN); 3134 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3135 } 3136 if_maddr_runlock(ifp); 3137 3138 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3139 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3140 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3141 } 3142 3143 static int 3144 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3145 { 3146 struct age_softc *sc; 3147 struct age_stats *stats; 3148 int error, result; 3149 3150 result = -1; 3151 error = sysctl_handle_int(oidp, &result, 0, req); 3152 3153 if (error != 0 || req->newptr == NULL) 3154 return (error); 3155 3156 if (result != 1) 3157 return (error); 3158 3159 sc = (struct age_softc *)arg1; 3160 stats = &sc->age_stat; 3161 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3162 printf("Transmit good frames : %ju\n", 3163 (uintmax_t)stats->tx_frames); 3164 printf("Transmit good broadcast frames : %ju\n", 3165 (uintmax_t)stats->tx_bcast_frames); 3166 printf("Transmit good multicast frames : %ju\n", 3167 (uintmax_t)stats->tx_mcast_frames); 3168 printf("Transmit pause control frames : %u\n", 3169 stats->tx_pause_frames); 3170 printf("Transmit control frames : %u\n", 3171 stats->tx_control_frames); 3172 printf("Transmit frames with excessive deferrals : %u\n", 3173 stats->tx_excess_defer); 3174 printf("Transmit deferrals : %u\n", 3175 stats->tx_deferred); 3176 printf("Transmit good octets : %ju\n", 3177 (uintmax_t)stats->tx_bytes); 3178 printf("Transmit good broadcast octets : %ju\n", 3179 (uintmax_t)stats->tx_bcast_bytes); 3180 printf("Transmit good multicast octets : %ju\n", 3181 (uintmax_t)stats->tx_mcast_bytes); 3182 printf("Transmit frames 64 bytes : %ju\n", 3183 (uintmax_t)stats->tx_pkts_64); 3184 printf("Transmit frames 65 to 127 bytes : %ju\n", 3185 (uintmax_t)stats->tx_pkts_65_127); 3186 printf("Transmit frames 128 to 255 bytes : %ju\n", 3187 (uintmax_t)stats->tx_pkts_128_255); 3188 printf("Transmit frames 256 to 511 bytes : %ju\n", 3189 (uintmax_t)stats->tx_pkts_256_511); 3190 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3191 (uintmax_t)stats->tx_pkts_512_1023); 3192 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3193 (uintmax_t)stats->tx_pkts_1024_1518); 3194 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3195 (uintmax_t)stats->tx_pkts_1519_max); 3196 printf("Transmit single collisions : %u\n", 3197 stats->tx_single_colls); 3198 printf("Transmit multiple collisions : %u\n", 3199 stats->tx_multi_colls); 3200 printf("Transmit late collisions : %u\n", 3201 stats->tx_late_colls); 3202 printf("Transmit abort due to excessive collisions : %u\n", 3203 stats->tx_excess_colls); 3204 printf("Transmit underruns due to FIFO underruns : %u\n", 3205 stats->tx_underrun); 3206 printf("Transmit descriptor write-back errors : %u\n", 3207 stats->tx_desc_underrun); 3208 printf("Transmit frames with length mismatched frame size : %u\n", 3209 stats->tx_lenerrs); 3210 printf("Transmit frames with truncated due to MTU size : %u\n", 3211 stats->tx_lenerrs); 3212 3213 printf("Receive good frames : %ju\n", 3214 (uintmax_t)stats->rx_frames); 3215 printf("Receive good broadcast frames : %ju\n", 3216 (uintmax_t)stats->rx_bcast_frames); 3217 printf("Receive good multicast frames : %ju\n", 3218 (uintmax_t)stats->rx_mcast_frames); 3219 printf("Receive pause control frames : %u\n", 3220 stats->rx_pause_frames); 3221 printf("Receive control frames : %u\n", 3222 stats->rx_control_frames); 3223 printf("Receive CRC errors : %u\n", 3224 stats->rx_crcerrs); 3225 printf("Receive frames with length errors : %u\n", 3226 stats->rx_lenerrs); 3227 printf("Receive good octets : %ju\n", 3228 (uintmax_t)stats->rx_bytes); 3229 printf("Receive good broadcast octets : %ju\n", 3230 (uintmax_t)stats->rx_bcast_bytes); 3231 printf("Receive good multicast octets : %ju\n", 3232 (uintmax_t)stats->rx_mcast_bytes); 3233 printf("Receive frames too short : %u\n", 3234 stats->rx_runts); 3235 printf("Receive fragmented frames : %ju\n", 3236 (uintmax_t)stats->rx_fragments); 3237 printf("Receive frames 64 bytes : %ju\n", 3238 (uintmax_t)stats->rx_pkts_64); 3239 printf("Receive frames 65 to 127 bytes : %ju\n", 3240 (uintmax_t)stats->rx_pkts_65_127); 3241 printf("Receive frames 128 to 255 bytes : %ju\n", 3242 (uintmax_t)stats->rx_pkts_128_255); 3243 printf("Receive frames 256 to 511 bytes : %ju\n", 3244 (uintmax_t)stats->rx_pkts_256_511); 3245 printf("Receive frames 512 to 1024 bytes : %ju\n", 3246 (uintmax_t)stats->rx_pkts_512_1023); 3247 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3248 (uintmax_t)stats->rx_pkts_1024_1518); 3249 printf("Receive frames 1519 to MTU bytes : %ju\n", 3250 (uintmax_t)stats->rx_pkts_1519_max); 3251 printf("Receive frames too long : %ju\n", 3252 (uint64_t)stats->rx_pkts_truncated); 3253 printf("Receive frames with FIFO overflow : %u\n", 3254 stats->rx_fifo_oflows); 3255 printf("Receive frames with return descriptor overflow : %u\n", 3256 stats->rx_desc_oflows); 3257 printf("Receive frames with alignment errors : %u\n", 3258 stats->rx_alignerrs); 3259 printf("Receive frames dropped due to address filtering : %ju\n", 3260 (uint64_t)stats->rx_pkts_filtered); 3261 3262 return (error); 3263 } 3264 3265 static int 3266 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3267 { 3268 int error, value; 3269 3270 if (arg1 == NULL) 3271 return (EINVAL); 3272 value = *(int *)arg1; 3273 error = sysctl_handle_int(oidp, &value, 0, req); 3274 if (error || req->newptr == NULL) 3275 return (error); 3276 if (value < low || value > high) 3277 return (EINVAL); 3278 *(int *)arg1 = value; 3279 3280 return (0); 3281 } 3282 3283 static int 3284 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3285 { 3286 return (sysctl_int_range(oidp, arg1, arg2, req, 3287 AGE_PROC_MIN, AGE_PROC_MAX)); 3288 } 3289 3290 static int 3291 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3292 { 3293 3294 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3295 AGE_IM_TIMER_MAX)); 3296 } 3297