1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/mbuf.h> 39 #include <sys/rman.h> 40 #include <sys/module.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <machine/bus.h> 69 #include <machine/in_cksum.h> 70 71 #include <dev/age/if_agereg.h> 72 #include <dev/age/if_agevar.h> 73 74 /* "device miibus" required. See GENERIC if you get errors here. */ 75 #include "miibus_if.h" 76 77 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78 79 MODULE_DEPEND(age, pci, 1, 1, 1); 80 MODULE_DEPEND(age, ether, 1, 1, 1); 81 MODULE_DEPEND(age, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 static int msix_disable = 0; 86 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 87 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 88 89 /* 90 * Devices supported by this driver. 91 */ 92 static struct age_dev { 93 uint16_t age_vendorid; 94 uint16_t age_deviceid; 95 const char *age_name; 96 } age_devs[] = { 97 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99 }; 100 101 static int age_miibus_readreg(device_t, int, int); 102 static int age_miibus_writereg(device_t, int, int, int); 103 static void age_miibus_statchg(device_t); 104 static void age_mediastatus(if_t, struct ifmediareq *); 105 static int age_mediachange(if_t); 106 static int age_probe(device_t); 107 static void age_get_macaddr(struct age_softc *); 108 static void age_phy_reset(struct age_softc *); 109 static int age_attach(device_t); 110 static int age_detach(device_t); 111 static void age_sysctl_node(struct age_softc *); 112 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 static int age_check_boundary(struct age_softc *); 114 static int age_dma_alloc(struct age_softc *); 115 static void age_dma_free(struct age_softc *); 116 static int age_shutdown(device_t); 117 static void age_setwol(struct age_softc *); 118 static int age_suspend(device_t); 119 static int age_resume(device_t); 120 static int age_encap(struct age_softc *, struct mbuf **); 121 static void age_start(if_t); 122 static void age_start_locked(if_t); 123 static void age_watchdog(struct age_softc *); 124 static int age_ioctl(if_t, u_long, caddr_t); 125 static void age_mac_config(struct age_softc *); 126 static void age_link_task(void *, int); 127 static void age_stats_update(struct age_softc *); 128 static int age_intr(void *); 129 static void age_int_task(void *, int); 130 static void age_txintr(struct age_softc *, int); 131 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132 static int age_rxintr(struct age_softc *, int, int); 133 static void age_tick(void *); 134 static void age_reset(struct age_softc *); 135 static void age_init(void *); 136 static void age_init_locked(struct age_softc *); 137 static void age_stop(struct age_softc *); 138 static void age_stop_txmac(struct age_softc *); 139 static void age_stop_rxmac(struct age_softc *); 140 static void age_init_tx_ring(struct age_softc *); 141 static int age_init_rx_ring(struct age_softc *); 142 static void age_init_rr_ring(struct age_softc *); 143 static void age_init_cmb_block(struct age_softc *); 144 static void age_init_smb_block(struct age_softc *); 145 #ifndef __NO_STRICT_ALIGNMENT 146 static struct mbuf *age_fixup_rx(if_t, struct mbuf *); 147 #endif 148 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 149 static void age_rxvlan(struct age_softc *); 150 static void age_rxfilter(struct age_softc *); 151 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 152 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 153 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 154 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 155 156 static device_method_t age_methods[] = { 157 /* Device interface. */ 158 DEVMETHOD(device_probe, age_probe), 159 DEVMETHOD(device_attach, age_attach), 160 DEVMETHOD(device_detach, age_detach), 161 DEVMETHOD(device_shutdown, age_shutdown), 162 DEVMETHOD(device_suspend, age_suspend), 163 DEVMETHOD(device_resume, age_resume), 164 165 /* MII interface. */ 166 DEVMETHOD(miibus_readreg, age_miibus_readreg), 167 DEVMETHOD(miibus_writereg, age_miibus_writereg), 168 DEVMETHOD(miibus_statchg, age_miibus_statchg), 169 { NULL, NULL } 170 }; 171 172 static driver_t age_driver = { 173 "age", 174 age_methods, 175 sizeof(struct age_softc) 176 }; 177 178 DRIVER_MODULE(age, pci, age_driver, 0, 0); 179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 180 nitems(age_devs)); 181 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0); 182 183 static struct resource_spec age_res_spec_mem[] = { 184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 185 { -1, 0, 0 } 186 }; 187 188 static struct resource_spec age_irq_spec_legacy[] = { 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 190 { -1, 0, 0 } 191 }; 192 193 static struct resource_spec age_irq_spec_msi[] = { 194 { SYS_RES_IRQ, 1, RF_ACTIVE }, 195 { -1, 0, 0 } 196 }; 197 198 static struct resource_spec age_irq_spec_msix[] = { 199 { SYS_RES_IRQ, 1, RF_ACTIVE }, 200 { -1, 0, 0 } 201 }; 202 203 /* 204 * Read a PHY register on the MII of the L1. 205 */ 206 static int 207 age_miibus_readreg(device_t dev, int phy, int reg) 208 { 209 struct age_softc *sc; 210 uint32_t v; 211 int i; 212 213 sc = device_get_softc(dev); 214 215 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 216 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 218 DELAY(1); 219 v = CSR_READ_4(sc, AGE_MDIO); 220 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 221 break; 222 } 223 224 if (i == 0) { 225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 226 return (0); 227 } 228 229 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 230 } 231 232 /* 233 * Write a PHY register on the MII of the L1. 234 */ 235 static int 236 age_miibus_writereg(device_t dev, int phy, int reg, int val) 237 { 238 struct age_softc *sc; 239 uint32_t v; 240 int i; 241 242 sc = device_get_softc(dev); 243 244 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 245 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 246 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 248 DELAY(1); 249 v = CSR_READ_4(sc, AGE_MDIO); 250 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 251 break; 252 } 253 254 if (i == 0) 255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 256 257 return (0); 258 } 259 260 /* 261 * Callback from MII layer when media changes. 262 */ 263 static void 264 age_miibus_statchg(device_t dev) 265 { 266 struct age_softc *sc; 267 268 sc = device_get_softc(dev); 269 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 270 } 271 272 /* 273 * Get the current interface media status. 274 */ 275 static void 276 age_mediastatus(if_t ifp, struct ifmediareq *ifmr) 277 { 278 struct age_softc *sc; 279 struct mii_data *mii; 280 281 sc = if_getsoftc(ifp); 282 AGE_LOCK(sc); 283 mii = device_get_softc(sc->age_miibus); 284 285 mii_pollstat(mii); 286 ifmr->ifm_status = mii->mii_media_status; 287 ifmr->ifm_active = mii->mii_media_active; 288 AGE_UNLOCK(sc); 289 } 290 291 /* 292 * Set hardware to newly-selected media. 293 */ 294 static int 295 age_mediachange(if_t ifp) 296 { 297 struct age_softc *sc; 298 struct mii_data *mii; 299 struct mii_softc *miisc; 300 int error; 301 302 sc = if_getsoftc(ifp); 303 AGE_LOCK(sc); 304 mii = device_get_softc(sc->age_miibus); 305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 306 PHY_RESET(miisc); 307 error = mii_mediachg(mii); 308 AGE_UNLOCK(sc); 309 310 return (error); 311 } 312 313 static int 314 age_probe(device_t dev) 315 { 316 struct age_dev *sp; 317 int i; 318 uint16_t vendor, devid; 319 320 vendor = pci_get_vendor(dev); 321 devid = pci_get_device(dev); 322 sp = age_devs; 323 for (i = 0; i < nitems(age_devs); i++, sp++) { 324 if (vendor == sp->age_vendorid && 325 devid == sp->age_deviceid) { 326 device_set_desc(dev, sp->age_name); 327 return (BUS_PROBE_DEFAULT); 328 } 329 } 330 331 return (ENXIO); 332 } 333 334 static void 335 age_get_macaddr(struct age_softc *sc) 336 { 337 uint32_t ea[2], reg; 338 int i, vpdc; 339 340 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 341 if ((reg & SPI_VPD_ENB) != 0) { 342 /* Get VPD stored in TWSI EEPROM. */ 343 reg &= ~SPI_VPD_ENB; 344 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 345 } 346 347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 348 /* 349 * PCI VPD capability found, let TWSI reload EEPROM. 350 * This will set ethernet address of controller. 351 */ 352 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 353 TWSI_CTRL_SW_LD_START); 354 for (i = 100; i > 0; i--) { 355 DELAY(1000); 356 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 357 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 358 break; 359 } 360 if (i == 0) 361 device_printf(sc->age_dev, 362 "reloading EEPROM timeout!\n"); 363 } else { 364 if (bootverbose) 365 device_printf(sc->age_dev, 366 "PCI VPD capability not found!\n"); 367 } 368 369 ea[0] = CSR_READ_4(sc, AGE_PAR0); 370 ea[1] = CSR_READ_4(sc, AGE_PAR1); 371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 377 } 378 379 static void 380 age_phy_reset(struct age_softc *sc) 381 { 382 uint16_t reg, pn; 383 int i, linkup; 384 385 /* Reset PHY. */ 386 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 387 DELAY(2000); 388 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 389 DELAY(2000); 390 391 #define ATPHY_DBG_ADDR 0x1D 392 #define ATPHY_DBG_DATA 0x1E 393 #define ATPHY_CDTC 0x16 394 #define PHY_CDTC_ENB 0x0001 395 #define PHY_CDTC_POFF 8 396 #define ATPHY_CDTS 0x1C 397 #define PHY_CDTS_STAT_OK 0x0000 398 #define PHY_CDTS_STAT_SHORT 0x0100 399 #define PHY_CDTS_STAT_OPEN 0x0200 400 #define PHY_CDTS_STAT_INVAL 0x0300 401 #define PHY_CDTS_STAT_MASK 0x0300 402 403 /* Check power saving mode. Magic from Linux. */ 404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 405 for (linkup = 0, pn = 0; pn < 4; pn++) { 406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 407 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 408 for (i = 200; i > 0; i--) { 409 DELAY(1000); 410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 411 ATPHY_CDTC); 412 if ((reg & PHY_CDTC_ENB) == 0) 413 break; 414 } 415 DELAY(1000); 416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 417 ATPHY_CDTS); 418 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 419 linkup++; 420 break; 421 } 422 } 423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 424 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 425 if (linkup == 0) { 426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 427 ATPHY_DBG_ADDR, 0); 428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429 ATPHY_DBG_DATA, 0x124E); 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431 ATPHY_DBG_ADDR, 1); 432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_DATA); 434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_DATA, reg | 0x03); 436 /* XXX */ 437 DELAY(1500 * 1000); 438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 439 ATPHY_DBG_ADDR, 0); 440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441 ATPHY_DBG_DATA, 0x024E); 442 } 443 444 #undef ATPHY_DBG_ADDR 445 #undef ATPHY_DBG_DATA 446 #undef ATPHY_CDTC 447 #undef PHY_CDTC_ENB 448 #undef PHY_CDTC_POFF 449 #undef ATPHY_CDTS 450 #undef PHY_CDTS_STAT_OK 451 #undef PHY_CDTS_STAT_SHORT 452 #undef PHY_CDTS_STAT_OPEN 453 #undef PHY_CDTS_STAT_INVAL 454 #undef PHY_CDTS_STAT_MASK 455 } 456 457 static int 458 age_attach(device_t dev) 459 { 460 struct age_softc *sc; 461 if_t ifp; 462 uint16_t burst; 463 int error, i, msic, msixc; 464 465 error = 0; 466 sc = device_get_softc(dev); 467 sc->age_dev = dev; 468 469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 470 MTX_DEF); 471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 474 475 /* Map the device. */ 476 pci_enable_busmaster(dev); 477 sc->age_res_spec = age_res_spec_mem; 478 sc->age_irq_spec = age_irq_spec_legacy; 479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 480 if (error != 0) { 481 device_printf(dev, "cannot allocate memory resources.\n"); 482 goto fail; 483 } 484 485 /* Set PHY address. */ 486 sc->age_phyaddr = AGE_PHY_ADDR; 487 488 /* Reset PHY. */ 489 age_phy_reset(sc); 490 491 /* Reset the ethernet controller. */ 492 age_reset(sc); 493 494 /* Get PCI and chip id/revision. */ 495 sc->age_rev = pci_get_revid(dev); 496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 497 MASTER_CHIP_REV_SHIFT; 498 if (bootverbose) { 499 device_printf(dev, "PCI device revision : 0x%04x\n", 500 sc->age_rev); 501 device_printf(dev, "Chip id/revision : 0x%04x\n", 502 sc->age_chip_rev); 503 } 504 505 /* 506 * XXX 507 * Unintialized hardware returns an invalid chip id/revision 508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 509 * unplugged cable results in putting hardware into automatic 510 * power down mode which in turn returns invalld chip revision. 511 */ 512 if (sc->age_chip_rev == 0xFFFF) { 513 device_printf(dev,"invalid chip revision : 0x%04x -- " 514 "not initialized?\n", sc->age_chip_rev); 515 error = ENXIO; 516 goto fail; 517 } 518 519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 520 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 521 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 522 523 /* Allocate IRQ resources. */ 524 msixc = pci_msix_count(dev); 525 msic = pci_msi_count(dev); 526 if (bootverbose) { 527 device_printf(dev, "MSIX count : %d\n", msixc); 528 device_printf(dev, "MSI count : %d\n", msic); 529 } 530 531 /* Prefer MSIX over MSI. */ 532 if (msix_disable == 0 || msi_disable == 0) { 533 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 534 pci_alloc_msix(dev, &msixc) == 0) { 535 if (msic == AGE_MSIX_MESSAGES) { 536 device_printf(dev, "Using %d MSIX messages.\n", 537 msixc); 538 sc->age_flags |= AGE_FLAG_MSIX; 539 sc->age_irq_spec = age_irq_spec_msix; 540 } else 541 pci_release_msi(dev); 542 } 543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 544 msic == AGE_MSI_MESSAGES && 545 pci_alloc_msi(dev, &msic) == 0) { 546 if (msic == AGE_MSI_MESSAGES) { 547 device_printf(dev, "Using %d MSI messages.\n", 548 msic); 549 sc->age_flags |= AGE_FLAG_MSI; 550 sc->age_irq_spec = age_irq_spec_msi; 551 } else 552 pci_release_msi(dev); 553 } 554 } 555 556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 557 if (error != 0) { 558 device_printf(dev, "cannot allocate IRQ resources.\n"); 559 goto fail; 560 } 561 562 /* Get DMA parameters from PCIe device control register. */ 563 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 564 sc->age_flags |= AGE_FLAG_PCIE; 565 burst = pci_read_config(dev, i + 0x08, 2); 566 /* Max read request size. */ 567 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 568 DMA_CFG_RD_BURST_SHIFT; 569 /* Max payload size. */ 570 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 571 DMA_CFG_WR_BURST_SHIFT; 572 if (bootverbose) { 573 device_printf(dev, "Read request size : %d bytes.\n", 574 128 << ((burst >> 12) & 0x07)); 575 device_printf(dev, "TLP payload size : %d bytes.\n", 576 128 << ((burst >> 5) & 0x07)); 577 } 578 } else { 579 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 580 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 581 } 582 583 /* Create device sysctl node. */ 584 age_sysctl_node(sc); 585 586 if ((error = age_dma_alloc(sc)) != 0) 587 goto fail; 588 589 /* Load station address. */ 590 age_get_macaddr(sc); 591 592 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 593 if_setsoftc(ifp, sc); 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 596 if_setioctlfn(ifp, age_ioctl); 597 if_setstartfn(ifp, age_start); 598 if_setinitfn(ifp, age_init); 599 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1); 600 if_setsendqready(ifp); 601 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 602 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO); 603 if (pci_has_pm(dev)) { 604 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 605 } 606 if_setcapenable(ifp, if_getcapabilities(ifp)); 607 608 /* Set up MII bus. */ 609 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 610 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 611 0); 612 if (error != 0) { 613 device_printf(dev, "attaching PHYs failed\n"); 614 goto fail; 615 } 616 617 ether_ifattach(ifp, sc->age_eaddr); 618 619 /* VLAN capability setup. */ 620 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 621 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 622 if_setcapenable(ifp, if_getcapabilities(ifp)); 623 624 /* Tell the upper layer(s) we support long frames. */ 625 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 626 627 /* Create local taskq. */ 628 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 629 taskqueue_thread_enqueue, &sc->age_tq); 630 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 631 device_get_nameunit(sc->age_dev)); 632 633 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 634 msic = AGE_MSIX_MESSAGES; 635 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 636 msic = AGE_MSI_MESSAGES; 637 else 638 msic = 1; 639 for (i = 0; i < msic; i++) { 640 error = bus_setup_intr(dev, sc->age_irq[i], 641 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 642 &sc->age_intrhand[i]); 643 if (error != 0) 644 break; 645 } 646 if (error != 0) { 647 device_printf(dev, "could not set up interrupt handler.\n"); 648 taskqueue_free(sc->age_tq); 649 sc->age_tq = NULL; 650 ether_ifdetach(ifp); 651 goto fail; 652 } 653 654 fail: 655 if (error != 0) 656 age_detach(dev); 657 658 return (error); 659 } 660 661 static int 662 age_detach(device_t dev) 663 { 664 struct age_softc *sc; 665 if_t ifp; 666 int i, msic; 667 668 sc = device_get_softc(dev); 669 670 ifp = sc->age_ifp; 671 if (device_is_attached(dev)) { 672 AGE_LOCK(sc); 673 sc->age_flags |= AGE_FLAG_DETACH; 674 age_stop(sc); 675 AGE_UNLOCK(sc); 676 callout_drain(&sc->age_tick_ch); 677 taskqueue_drain(sc->age_tq, &sc->age_int_task); 678 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 679 ether_ifdetach(ifp); 680 } 681 682 if (sc->age_tq != NULL) { 683 taskqueue_drain(sc->age_tq, &sc->age_int_task); 684 taskqueue_free(sc->age_tq); 685 sc->age_tq = NULL; 686 } 687 688 bus_generic_detach(dev); 689 age_dma_free(sc); 690 691 if (ifp != NULL) { 692 if_free(ifp); 693 sc->age_ifp = NULL; 694 } 695 696 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 697 msic = AGE_MSIX_MESSAGES; 698 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 699 msic = AGE_MSI_MESSAGES; 700 else 701 msic = 1; 702 for (i = 0; i < msic; i++) { 703 if (sc->age_intrhand[i] != NULL) { 704 bus_teardown_intr(dev, sc->age_irq[i], 705 sc->age_intrhand[i]); 706 sc->age_intrhand[i] = NULL; 707 } 708 } 709 710 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 711 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 712 pci_release_msi(dev); 713 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 714 mtx_destroy(&sc->age_mtx); 715 716 return (0); 717 } 718 719 static void 720 age_sysctl_node(struct age_softc *sc) 721 { 722 int error; 723 724 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 725 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 726 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 727 sc, 0, sysctl_age_stats, "I", "Statistics"); 728 729 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 730 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 731 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 732 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", 733 "age interrupt moderation"); 734 735 /* Pull in device tunables. */ 736 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 737 error = resource_int_value(device_get_name(sc->age_dev), 738 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 739 if (error == 0) { 740 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 741 sc->age_int_mod > AGE_IM_TIMER_MAX) { 742 device_printf(sc->age_dev, 743 "int_mod value out of range; using default: %d\n", 744 AGE_IM_TIMER_DEFAULT); 745 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 746 } 747 } 748 749 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 751 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 752 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", 753 "max number of Rx events to process"); 754 755 /* Pull in device tunables. */ 756 sc->age_process_limit = AGE_PROC_DEFAULT; 757 error = resource_int_value(device_get_name(sc->age_dev), 758 device_get_unit(sc->age_dev), "process_limit", 759 &sc->age_process_limit); 760 if (error == 0) { 761 if (sc->age_process_limit < AGE_PROC_MIN || 762 sc->age_process_limit > AGE_PROC_MAX) { 763 device_printf(sc->age_dev, 764 "process_limit value out of range; " 765 "using default: %d\n", AGE_PROC_DEFAULT); 766 sc->age_process_limit = AGE_PROC_DEFAULT; 767 } 768 } 769 } 770 771 struct age_dmamap_arg { 772 bus_addr_t age_busaddr; 773 }; 774 775 static void 776 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 777 { 778 struct age_dmamap_arg *ctx; 779 780 if (error != 0) 781 return; 782 783 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 784 785 ctx = (struct age_dmamap_arg *)arg; 786 ctx->age_busaddr = segs[0].ds_addr; 787 } 788 789 /* 790 * Attansic L1 controller have single register to specify high 791 * address part of DMA blocks. So all descriptor structures and 792 * DMA memory blocks should have the same high address of given 793 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 794 */ 795 static int 796 age_check_boundary(struct age_softc *sc) 797 { 798 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 799 bus_addr_t cmb_block_end, smb_block_end; 800 801 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 802 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 803 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 804 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 805 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 806 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 807 808 if ((AGE_ADDR_HI(tx_ring_end) != 809 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 810 (AGE_ADDR_HI(rx_ring_end) != 811 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 812 (AGE_ADDR_HI(rr_ring_end) != 813 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 814 (AGE_ADDR_HI(cmb_block_end) != 815 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 816 (AGE_ADDR_HI(smb_block_end) != 817 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 818 return (EFBIG); 819 820 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 821 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 822 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 823 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 824 return (EFBIG); 825 826 return (0); 827 } 828 829 static int 830 age_dma_alloc(struct age_softc *sc) 831 { 832 struct age_txdesc *txd; 833 struct age_rxdesc *rxd; 834 bus_addr_t lowaddr; 835 struct age_dmamap_arg ctx; 836 int error, i; 837 838 lowaddr = BUS_SPACE_MAXADDR; 839 840 again: 841 /* Create parent ring/DMA block tag. */ 842 error = bus_dma_tag_create( 843 bus_get_dma_tag(sc->age_dev), /* parent */ 844 1, 0, /* alignment, boundary */ 845 lowaddr, /* lowaddr */ 846 BUS_SPACE_MAXADDR, /* highaddr */ 847 NULL, NULL, /* filter, filterarg */ 848 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 849 0, /* nsegments */ 850 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 851 0, /* flags */ 852 NULL, NULL, /* lockfunc, lockarg */ 853 &sc->age_cdata.age_parent_tag); 854 if (error != 0) { 855 device_printf(sc->age_dev, 856 "could not create parent DMA tag.\n"); 857 goto fail; 858 } 859 860 /* Create tag for Tx ring. */ 861 error = bus_dma_tag_create( 862 sc->age_cdata.age_parent_tag, /* parent */ 863 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 864 BUS_SPACE_MAXADDR, /* lowaddr */ 865 BUS_SPACE_MAXADDR, /* highaddr */ 866 NULL, NULL, /* filter, filterarg */ 867 AGE_TX_RING_SZ, /* maxsize */ 868 1, /* nsegments */ 869 AGE_TX_RING_SZ, /* maxsegsize */ 870 0, /* flags */ 871 NULL, NULL, /* lockfunc, lockarg */ 872 &sc->age_cdata.age_tx_ring_tag); 873 if (error != 0) { 874 device_printf(sc->age_dev, 875 "could not create Tx ring DMA tag.\n"); 876 goto fail; 877 } 878 879 /* Create tag for Rx ring. */ 880 error = bus_dma_tag_create( 881 sc->age_cdata.age_parent_tag, /* parent */ 882 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 883 BUS_SPACE_MAXADDR, /* lowaddr */ 884 BUS_SPACE_MAXADDR, /* highaddr */ 885 NULL, NULL, /* filter, filterarg */ 886 AGE_RX_RING_SZ, /* maxsize */ 887 1, /* nsegments */ 888 AGE_RX_RING_SZ, /* maxsegsize */ 889 0, /* flags */ 890 NULL, NULL, /* lockfunc, lockarg */ 891 &sc->age_cdata.age_rx_ring_tag); 892 if (error != 0) { 893 device_printf(sc->age_dev, 894 "could not create Rx ring DMA tag.\n"); 895 goto fail; 896 } 897 898 /* Create tag for Rx return ring. */ 899 error = bus_dma_tag_create( 900 sc->age_cdata.age_parent_tag, /* parent */ 901 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 902 BUS_SPACE_MAXADDR, /* lowaddr */ 903 BUS_SPACE_MAXADDR, /* highaddr */ 904 NULL, NULL, /* filter, filterarg */ 905 AGE_RR_RING_SZ, /* maxsize */ 906 1, /* nsegments */ 907 AGE_RR_RING_SZ, /* maxsegsize */ 908 0, /* flags */ 909 NULL, NULL, /* lockfunc, lockarg */ 910 &sc->age_cdata.age_rr_ring_tag); 911 if (error != 0) { 912 device_printf(sc->age_dev, 913 "could not create Rx return ring DMA tag.\n"); 914 goto fail; 915 } 916 917 /* Create tag for coalesing message block. */ 918 error = bus_dma_tag_create( 919 sc->age_cdata.age_parent_tag, /* parent */ 920 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 921 BUS_SPACE_MAXADDR, /* lowaddr */ 922 BUS_SPACE_MAXADDR, /* highaddr */ 923 NULL, NULL, /* filter, filterarg */ 924 AGE_CMB_BLOCK_SZ, /* maxsize */ 925 1, /* nsegments */ 926 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 927 0, /* flags */ 928 NULL, NULL, /* lockfunc, lockarg */ 929 &sc->age_cdata.age_cmb_block_tag); 930 if (error != 0) { 931 device_printf(sc->age_dev, 932 "could not create CMB DMA tag.\n"); 933 goto fail; 934 } 935 936 /* Create tag for statistics message block. */ 937 error = bus_dma_tag_create( 938 sc->age_cdata.age_parent_tag, /* parent */ 939 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 940 BUS_SPACE_MAXADDR, /* lowaddr */ 941 BUS_SPACE_MAXADDR, /* highaddr */ 942 NULL, NULL, /* filter, filterarg */ 943 AGE_SMB_BLOCK_SZ, /* maxsize */ 944 1, /* nsegments */ 945 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 946 0, /* flags */ 947 NULL, NULL, /* lockfunc, lockarg */ 948 &sc->age_cdata.age_smb_block_tag); 949 if (error != 0) { 950 device_printf(sc->age_dev, 951 "could not create SMB DMA tag.\n"); 952 goto fail; 953 } 954 955 /* Allocate DMA'able memory and load the DMA map. */ 956 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 957 (void **)&sc->age_rdata.age_tx_ring, 958 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 959 &sc->age_cdata.age_tx_ring_map); 960 if (error != 0) { 961 device_printf(sc->age_dev, 962 "could not allocate DMA'able memory for Tx ring.\n"); 963 goto fail; 964 } 965 ctx.age_busaddr = 0; 966 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 967 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 968 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 969 if (error != 0 || ctx.age_busaddr == 0) { 970 device_printf(sc->age_dev, 971 "could not load DMA'able memory for Tx ring.\n"); 972 goto fail; 973 } 974 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 975 /* Rx ring */ 976 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 977 (void **)&sc->age_rdata.age_rx_ring, 978 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 979 &sc->age_cdata.age_rx_ring_map); 980 if (error != 0) { 981 device_printf(sc->age_dev, 982 "could not allocate DMA'able memory for Rx ring.\n"); 983 goto fail; 984 } 985 ctx.age_busaddr = 0; 986 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 987 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 988 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 989 if (error != 0 || ctx.age_busaddr == 0) { 990 device_printf(sc->age_dev, 991 "could not load DMA'able memory for Rx ring.\n"); 992 goto fail; 993 } 994 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 995 /* Rx return ring */ 996 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 997 (void **)&sc->age_rdata.age_rr_ring, 998 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 999 &sc->age_cdata.age_rr_ring_map); 1000 if (error != 0) { 1001 device_printf(sc->age_dev, 1002 "could not allocate DMA'able memory for Rx return ring.\n"); 1003 goto fail; 1004 } 1005 ctx.age_busaddr = 0; 1006 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1007 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1008 AGE_RR_RING_SZ, age_dmamap_cb, 1009 &ctx, 0); 1010 if (error != 0 || ctx.age_busaddr == 0) { 1011 device_printf(sc->age_dev, 1012 "could not load DMA'able memory for Rx return ring.\n"); 1013 goto fail; 1014 } 1015 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1016 /* CMB block */ 1017 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1018 (void **)&sc->age_rdata.age_cmb_block, 1019 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1020 &sc->age_cdata.age_cmb_block_map); 1021 if (error != 0) { 1022 device_printf(sc->age_dev, 1023 "could not allocate DMA'able memory for CMB block.\n"); 1024 goto fail; 1025 } 1026 ctx.age_busaddr = 0; 1027 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1028 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1029 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1030 if (error != 0 || ctx.age_busaddr == 0) { 1031 device_printf(sc->age_dev, 1032 "could not load DMA'able memory for CMB block.\n"); 1033 goto fail; 1034 } 1035 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1036 /* SMB block */ 1037 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1038 (void **)&sc->age_rdata.age_smb_block, 1039 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1040 &sc->age_cdata.age_smb_block_map); 1041 if (error != 0) { 1042 device_printf(sc->age_dev, 1043 "could not allocate DMA'able memory for SMB block.\n"); 1044 goto fail; 1045 } 1046 ctx.age_busaddr = 0; 1047 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1048 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1049 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1050 if (error != 0 || ctx.age_busaddr == 0) { 1051 device_printf(sc->age_dev, 1052 "could not load DMA'able memory for SMB block.\n"); 1053 goto fail; 1054 } 1055 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1056 1057 /* 1058 * All ring buffer and DMA blocks should have the same 1059 * high address part of 64bit DMA address space. 1060 */ 1061 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1062 (error = age_check_boundary(sc)) != 0) { 1063 device_printf(sc->age_dev, "4GB boundary crossed, " 1064 "switching to 32bit DMA addressing mode.\n"); 1065 age_dma_free(sc); 1066 /* Limit DMA address space to 32bit and try again. */ 1067 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1068 goto again; 1069 } 1070 1071 /* 1072 * Create Tx/Rx buffer parent tag. 1073 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1074 * so it needs separate parent DMA tag. 1075 * XXX 1076 * It seems enabling 64bit DMA causes data corruption. Limit 1077 * DMA address space to 32bit. 1078 */ 1079 error = bus_dma_tag_create( 1080 bus_get_dma_tag(sc->age_dev), /* parent */ 1081 1, 0, /* alignment, boundary */ 1082 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1083 BUS_SPACE_MAXADDR, /* highaddr */ 1084 NULL, NULL, /* filter, filterarg */ 1085 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1086 0, /* nsegments */ 1087 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1088 0, /* flags */ 1089 NULL, NULL, /* lockfunc, lockarg */ 1090 &sc->age_cdata.age_buffer_tag); 1091 if (error != 0) { 1092 device_printf(sc->age_dev, 1093 "could not create parent buffer DMA tag.\n"); 1094 goto fail; 1095 } 1096 1097 /* Create tag for Tx buffers. */ 1098 error = bus_dma_tag_create( 1099 sc->age_cdata.age_buffer_tag, /* parent */ 1100 1, 0, /* alignment, boundary */ 1101 BUS_SPACE_MAXADDR, /* lowaddr */ 1102 BUS_SPACE_MAXADDR, /* highaddr */ 1103 NULL, NULL, /* filter, filterarg */ 1104 AGE_TSO_MAXSIZE, /* maxsize */ 1105 AGE_MAXTXSEGS, /* nsegments */ 1106 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1107 0, /* flags */ 1108 NULL, NULL, /* lockfunc, lockarg */ 1109 &sc->age_cdata.age_tx_tag); 1110 if (error != 0) { 1111 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1112 goto fail; 1113 } 1114 1115 /* Create tag for Rx buffers. */ 1116 error = bus_dma_tag_create( 1117 sc->age_cdata.age_buffer_tag, /* parent */ 1118 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1119 BUS_SPACE_MAXADDR, /* lowaddr */ 1120 BUS_SPACE_MAXADDR, /* highaddr */ 1121 NULL, NULL, /* filter, filterarg */ 1122 MCLBYTES, /* maxsize */ 1123 1, /* nsegments */ 1124 MCLBYTES, /* maxsegsize */ 1125 0, /* flags */ 1126 NULL, NULL, /* lockfunc, lockarg */ 1127 &sc->age_cdata.age_rx_tag); 1128 if (error != 0) { 1129 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1130 goto fail; 1131 } 1132 1133 /* Create DMA maps for Tx buffers. */ 1134 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1135 txd = &sc->age_cdata.age_txdesc[i]; 1136 txd->tx_m = NULL; 1137 txd->tx_dmamap = NULL; 1138 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1139 &txd->tx_dmamap); 1140 if (error != 0) { 1141 device_printf(sc->age_dev, 1142 "could not create Tx dmamap.\n"); 1143 goto fail; 1144 } 1145 } 1146 /* Create DMA maps for Rx buffers. */ 1147 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1148 &sc->age_cdata.age_rx_sparemap)) != 0) { 1149 device_printf(sc->age_dev, 1150 "could not create spare Rx dmamap.\n"); 1151 goto fail; 1152 } 1153 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1154 rxd = &sc->age_cdata.age_rxdesc[i]; 1155 rxd->rx_m = NULL; 1156 rxd->rx_dmamap = NULL; 1157 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1158 &rxd->rx_dmamap); 1159 if (error != 0) { 1160 device_printf(sc->age_dev, 1161 "could not create Rx dmamap.\n"); 1162 goto fail; 1163 } 1164 } 1165 1166 fail: 1167 return (error); 1168 } 1169 1170 static void 1171 age_dma_free(struct age_softc *sc) 1172 { 1173 struct age_txdesc *txd; 1174 struct age_rxdesc *rxd; 1175 int i; 1176 1177 /* Tx buffers */ 1178 if (sc->age_cdata.age_tx_tag != NULL) { 1179 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1180 txd = &sc->age_cdata.age_txdesc[i]; 1181 if (txd->tx_dmamap != NULL) { 1182 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1183 txd->tx_dmamap); 1184 txd->tx_dmamap = NULL; 1185 } 1186 } 1187 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1188 sc->age_cdata.age_tx_tag = NULL; 1189 } 1190 /* Rx buffers */ 1191 if (sc->age_cdata.age_rx_tag != NULL) { 1192 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1193 rxd = &sc->age_cdata.age_rxdesc[i]; 1194 if (rxd->rx_dmamap != NULL) { 1195 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1196 rxd->rx_dmamap); 1197 rxd->rx_dmamap = NULL; 1198 } 1199 } 1200 if (sc->age_cdata.age_rx_sparemap != NULL) { 1201 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1202 sc->age_cdata.age_rx_sparemap); 1203 sc->age_cdata.age_rx_sparemap = NULL; 1204 } 1205 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1206 sc->age_cdata.age_rx_tag = NULL; 1207 } 1208 /* Tx ring. */ 1209 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1210 if (sc->age_rdata.age_tx_ring_paddr != 0) 1211 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1212 sc->age_cdata.age_tx_ring_map); 1213 if (sc->age_rdata.age_tx_ring != NULL) 1214 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1215 sc->age_rdata.age_tx_ring, 1216 sc->age_cdata.age_tx_ring_map); 1217 sc->age_rdata.age_tx_ring_paddr = 0; 1218 sc->age_rdata.age_tx_ring = NULL; 1219 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1220 sc->age_cdata.age_tx_ring_tag = NULL; 1221 } 1222 /* Rx ring. */ 1223 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1224 if (sc->age_rdata.age_rx_ring_paddr != 0) 1225 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1226 sc->age_cdata.age_rx_ring_map); 1227 if (sc->age_rdata.age_rx_ring != NULL) 1228 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1229 sc->age_rdata.age_rx_ring, 1230 sc->age_cdata.age_rx_ring_map); 1231 sc->age_rdata.age_rx_ring_paddr = 0; 1232 sc->age_rdata.age_rx_ring = NULL; 1233 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1234 sc->age_cdata.age_rx_ring_tag = NULL; 1235 } 1236 /* Rx return ring. */ 1237 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1238 if (sc->age_rdata.age_rr_ring_paddr != 0) 1239 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1240 sc->age_cdata.age_rr_ring_map); 1241 if (sc->age_rdata.age_rr_ring != NULL) 1242 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1243 sc->age_rdata.age_rr_ring, 1244 sc->age_cdata.age_rr_ring_map); 1245 sc->age_rdata.age_rr_ring_paddr = 0; 1246 sc->age_rdata.age_rr_ring = NULL; 1247 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1248 sc->age_cdata.age_rr_ring_tag = NULL; 1249 } 1250 /* CMB block */ 1251 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1252 if (sc->age_rdata.age_cmb_block_paddr != 0) 1253 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1254 sc->age_cdata.age_cmb_block_map); 1255 if (sc->age_rdata.age_cmb_block != NULL) 1256 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1257 sc->age_rdata.age_cmb_block, 1258 sc->age_cdata.age_cmb_block_map); 1259 sc->age_rdata.age_cmb_block_paddr = 0; 1260 sc->age_rdata.age_cmb_block = NULL; 1261 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1262 sc->age_cdata.age_cmb_block_tag = NULL; 1263 } 1264 /* SMB block */ 1265 if (sc->age_cdata.age_smb_block_tag != NULL) { 1266 if (sc->age_rdata.age_smb_block_paddr != 0) 1267 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1268 sc->age_cdata.age_smb_block_map); 1269 if (sc->age_rdata.age_smb_block != NULL) 1270 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1271 sc->age_rdata.age_smb_block, 1272 sc->age_cdata.age_smb_block_map); 1273 sc->age_rdata.age_smb_block_paddr = 0; 1274 sc->age_rdata.age_smb_block = NULL; 1275 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1276 sc->age_cdata.age_smb_block_tag = NULL; 1277 } 1278 1279 if (sc->age_cdata.age_buffer_tag != NULL) { 1280 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1281 sc->age_cdata.age_buffer_tag = NULL; 1282 } 1283 if (sc->age_cdata.age_parent_tag != NULL) { 1284 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1285 sc->age_cdata.age_parent_tag = NULL; 1286 } 1287 } 1288 1289 /* 1290 * Make sure the interface is stopped at reboot time. 1291 */ 1292 static int 1293 age_shutdown(device_t dev) 1294 { 1295 1296 return (age_suspend(dev)); 1297 } 1298 1299 static void 1300 age_setwol(struct age_softc *sc) 1301 { 1302 if_t ifp; 1303 struct mii_data *mii; 1304 uint32_t reg, pmcs; 1305 int aneg, i; 1306 1307 AGE_LOCK_ASSERT(sc); 1308 1309 if (!pci_has_pm(sc->age_dev)) { 1310 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1311 /* 1312 * No PME capability, PHY power down. 1313 * XXX 1314 * Due to an unknown reason powering down PHY resulted 1315 * in unexpected results such as inaccessbility of 1316 * hardware of freshly rebooted system. Disable 1317 * powering down PHY until I got more information for 1318 * Attansic/Atheros PHY hardwares. 1319 */ 1320 #ifdef notyet 1321 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1322 MII_BMCR, BMCR_PDOWN); 1323 #endif 1324 return; 1325 } 1326 1327 ifp = sc->age_ifp; 1328 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1329 /* 1330 * Note, this driver resets the link speed to 10/100Mbps with 1331 * auto-negotiation but we don't know whether that operation 1332 * would succeed or not as it have no control after powering 1333 * off. If the renegotiation fail WOL may not work. Running 1334 * at 1Gbps will draw more power than 375mA at 3.3V which is 1335 * specified in PCI specification and that would result in 1336 * complete shutdowning power to ethernet controller. 1337 * 1338 * TODO 1339 * Save current negotiated media speed/duplex/flow-control 1340 * to softc and restore the same link again after resuming. 1341 * PHY handling such as power down/resetting to 100Mbps 1342 * may be better handled in suspend method in phy driver. 1343 */ 1344 mii = device_get_softc(sc->age_miibus); 1345 mii_pollstat(mii); 1346 aneg = 0; 1347 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1348 switch IFM_SUBTYPE(mii->mii_media_active) { 1349 case IFM_10_T: 1350 case IFM_100_TX: 1351 goto got_link; 1352 case IFM_1000_T: 1353 aneg++; 1354 default: 1355 break; 1356 } 1357 } 1358 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1359 MII_100T2CR, 0); 1360 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1361 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1362 ANAR_10 | ANAR_CSMA); 1363 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1364 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1365 DELAY(1000); 1366 if (aneg != 0) { 1367 /* Poll link state until age(4) get a 10/100 link. */ 1368 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1369 mii_pollstat(mii); 1370 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1371 switch (IFM_SUBTYPE( 1372 mii->mii_media_active)) { 1373 case IFM_10_T: 1374 case IFM_100_TX: 1375 age_mac_config(sc); 1376 goto got_link; 1377 default: 1378 break; 1379 } 1380 } 1381 AGE_UNLOCK(sc); 1382 pause("agelnk", hz); 1383 AGE_LOCK(sc); 1384 } 1385 if (i == MII_ANEGTICKS_GIGE) 1386 device_printf(sc->age_dev, 1387 "establishing link failed, " 1388 "WOL may not work!"); 1389 } 1390 /* 1391 * No link, force MAC to have 100Mbps, full-duplex link. 1392 * This is the last resort and may/may not work. 1393 */ 1394 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1395 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1396 age_mac_config(sc); 1397 } 1398 1399 got_link: 1400 pmcs = 0; 1401 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1402 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1403 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1404 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1405 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1406 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1407 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1408 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1409 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1410 reg |= MAC_CFG_RX_ENB; 1411 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1412 } 1413 1414 /* Request PME. */ 1415 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1416 pci_enable_pme(sc->age_dev); 1417 #ifdef notyet 1418 /* See above for powering down PHY issues. */ 1419 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1420 /* No WOL, PHY power down. */ 1421 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1422 MII_BMCR, BMCR_PDOWN); 1423 } 1424 #endif 1425 } 1426 1427 static int 1428 age_suspend(device_t dev) 1429 { 1430 struct age_softc *sc; 1431 1432 sc = device_get_softc(dev); 1433 1434 AGE_LOCK(sc); 1435 age_stop(sc); 1436 age_setwol(sc); 1437 AGE_UNLOCK(sc); 1438 1439 return (0); 1440 } 1441 1442 static int 1443 age_resume(device_t dev) 1444 { 1445 struct age_softc *sc; 1446 if_t ifp; 1447 1448 sc = device_get_softc(dev); 1449 1450 AGE_LOCK(sc); 1451 age_phy_reset(sc); 1452 ifp = sc->age_ifp; 1453 if ((if_getflags(ifp) & IFF_UP) != 0) 1454 age_init_locked(sc); 1455 1456 AGE_UNLOCK(sc); 1457 1458 return (0); 1459 } 1460 1461 static int 1462 age_encap(struct age_softc *sc, struct mbuf **m_head) 1463 { 1464 struct age_txdesc *txd, *txd_last; 1465 struct tx_desc *desc; 1466 struct mbuf *m; 1467 struct ip *ip; 1468 struct tcphdr *tcp; 1469 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1470 bus_dmamap_t map; 1471 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1472 int error, i, nsegs, prod, si; 1473 1474 AGE_LOCK_ASSERT(sc); 1475 1476 M_ASSERTPKTHDR((*m_head)); 1477 1478 m = *m_head; 1479 ip = NULL; 1480 tcp = NULL; 1481 cflags = vtag = 0; 1482 ip_off = poff = 0; 1483 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1484 /* 1485 * L1 requires offset of TCP/UDP payload in its Tx 1486 * descriptor to perform hardware Tx checksum offload. 1487 * Additionally, TSO requires IP/TCP header size and 1488 * modification of IP/TCP header in order to make TSO 1489 * engine work. This kind of operation takes many CPU 1490 * cycles on FreeBSD so fast host CPU is needed to get 1491 * smooth TSO performance. 1492 */ 1493 struct ether_header *eh; 1494 1495 if (M_WRITABLE(m) == 0) { 1496 /* Get a writable copy. */ 1497 m = m_dup(*m_head, M_NOWAIT); 1498 /* Release original mbufs. */ 1499 m_freem(*m_head); 1500 if (m == NULL) { 1501 *m_head = NULL; 1502 return (ENOBUFS); 1503 } 1504 *m_head = m; 1505 } 1506 ip_off = sizeof(struct ether_header); 1507 m = m_pullup(m, ip_off); 1508 if (m == NULL) { 1509 *m_head = NULL; 1510 return (ENOBUFS); 1511 } 1512 eh = mtod(m, struct ether_header *); 1513 /* 1514 * Check if hardware VLAN insertion is off. 1515 * Additional check for LLC/SNAP frame? 1516 */ 1517 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1518 ip_off = sizeof(struct ether_vlan_header); 1519 m = m_pullup(m, ip_off); 1520 if (m == NULL) { 1521 *m_head = NULL; 1522 return (ENOBUFS); 1523 } 1524 } 1525 m = m_pullup(m, ip_off + sizeof(struct ip)); 1526 if (m == NULL) { 1527 *m_head = NULL; 1528 return (ENOBUFS); 1529 } 1530 ip = (struct ip *)(mtod(m, char *) + ip_off); 1531 poff = ip_off + (ip->ip_hl << 2); 1532 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1533 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1534 if (m == NULL) { 1535 *m_head = NULL; 1536 return (ENOBUFS); 1537 } 1538 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1539 m = m_pullup(m, poff + (tcp->th_off << 2)); 1540 if (m == NULL) { 1541 *m_head = NULL; 1542 return (ENOBUFS); 1543 } 1544 /* 1545 * L1 requires IP/TCP header size and offset as 1546 * well as TCP pseudo checksum which complicates 1547 * TSO configuration. I guess this comes from the 1548 * adherence to Microsoft NDIS Large Send 1549 * specification which requires insertion of 1550 * pseudo checksum by upper stack. The pseudo 1551 * checksum that NDIS refers to doesn't include 1552 * TCP payload length so age(4) should recompute 1553 * the pseudo checksum here. Hopefully this wouldn't 1554 * be much burden on modern CPUs. 1555 * Reset IP checksum and recompute TCP pseudo 1556 * checksum as NDIS specification said. 1557 */ 1558 ip = (struct ip *)(mtod(m, char *) + ip_off); 1559 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1560 ip->ip_sum = 0; 1561 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1562 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1563 } 1564 *m_head = m; 1565 } 1566 1567 si = prod = sc->age_cdata.age_tx_prod; 1568 txd = &sc->age_cdata.age_txdesc[prod]; 1569 txd_last = txd; 1570 map = txd->tx_dmamap; 1571 1572 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1573 *m_head, txsegs, &nsegs, 0); 1574 if (error == EFBIG) { 1575 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1576 if (m == NULL) { 1577 m_freem(*m_head); 1578 *m_head = NULL; 1579 return (ENOMEM); 1580 } 1581 *m_head = m; 1582 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1583 *m_head, txsegs, &nsegs, 0); 1584 if (error != 0) { 1585 m_freem(*m_head); 1586 *m_head = NULL; 1587 return (error); 1588 } 1589 } else if (error != 0) 1590 return (error); 1591 if (nsegs == 0) { 1592 m_freem(*m_head); 1593 *m_head = NULL; 1594 return (EIO); 1595 } 1596 1597 /* Check descriptor overrun. */ 1598 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1599 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1600 return (ENOBUFS); 1601 } 1602 1603 m = *m_head; 1604 /* Configure VLAN hardware tag insertion. */ 1605 if ((m->m_flags & M_VLANTAG) != 0) { 1606 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1607 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1608 cflags |= AGE_TD_INSERT_VLAN_TAG; 1609 } 1610 1611 desc = NULL; 1612 i = 0; 1613 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1614 /* Request TSO and set MSS. */ 1615 cflags |= AGE_TD_TSO_IPV4; 1616 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1617 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1618 AGE_TD_TSO_MSS_SHIFT); 1619 /* Set IP/TCP header size. */ 1620 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1621 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1622 /* 1623 * L1 requires the first buffer should only hold IP/TCP 1624 * header data. TCP payload should be handled in other 1625 * descriptors. 1626 */ 1627 hdrlen = poff + (tcp->th_off << 2); 1628 desc = &sc->age_rdata.age_tx_ring[prod]; 1629 desc->addr = htole64(txsegs[0].ds_addr); 1630 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1631 desc->flags = htole32(cflags); 1632 sc->age_cdata.age_tx_cnt++; 1633 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1634 if (m->m_len - hdrlen > 0) { 1635 /* Handle remaining payload of the 1st fragment. */ 1636 desc = &sc->age_rdata.age_tx_ring[prod]; 1637 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1638 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1639 vtag); 1640 desc->flags = htole32(cflags); 1641 sc->age_cdata.age_tx_cnt++; 1642 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1643 } 1644 /* Handle remaining fragments. */ 1645 i = 1; 1646 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1647 /* Configure Tx IP/TCP/UDP checksum offload. */ 1648 cflags |= AGE_TD_CSUM; 1649 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1650 cflags |= AGE_TD_TCPCSUM; 1651 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1652 cflags |= AGE_TD_UDPCSUM; 1653 /* Set checksum start offset. */ 1654 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1655 /* Set checksum insertion position of TCP/UDP. */ 1656 cflags |= ((poff + m->m_pkthdr.csum_data) << 1657 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1658 } 1659 for (; i < nsegs; i++) { 1660 desc = &sc->age_rdata.age_tx_ring[prod]; 1661 desc->addr = htole64(txsegs[i].ds_addr); 1662 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1663 desc->flags = htole32(cflags); 1664 sc->age_cdata.age_tx_cnt++; 1665 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1666 } 1667 /* Update producer index. */ 1668 sc->age_cdata.age_tx_prod = prod; 1669 1670 /* Set EOP on the last descriptor. */ 1671 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1672 desc = &sc->age_rdata.age_tx_ring[prod]; 1673 desc->flags |= htole32(AGE_TD_EOP); 1674 1675 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1676 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1677 desc = &sc->age_rdata.age_tx_ring[si]; 1678 desc->flags |= htole32(AGE_TD_TSO_HDR); 1679 } 1680 1681 /* Swap dmamap of the first and the last. */ 1682 txd = &sc->age_cdata.age_txdesc[prod]; 1683 map = txd_last->tx_dmamap; 1684 txd_last->tx_dmamap = txd->tx_dmamap; 1685 txd->tx_dmamap = map; 1686 txd->tx_m = m; 1687 1688 /* Sync descriptors. */ 1689 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1690 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1691 sc->age_cdata.age_tx_ring_map, 1692 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1693 1694 return (0); 1695 } 1696 1697 static void 1698 age_start(if_t ifp) 1699 { 1700 struct age_softc *sc; 1701 1702 sc = if_getsoftc(ifp); 1703 AGE_LOCK(sc); 1704 age_start_locked(ifp); 1705 AGE_UNLOCK(sc); 1706 } 1707 1708 static void 1709 age_start_locked(if_t ifp) 1710 { 1711 struct age_softc *sc; 1712 struct mbuf *m_head; 1713 int enq; 1714 1715 sc = if_getsoftc(ifp); 1716 1717 AGE_LOCK_ASSERT(sc); 1718 1719 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1720 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1721 return; 1722 1723 for (enq = 0; !if_sendq_empty(ifp); ) { 1724 m_head = if_dequeue(ifp); 1725 if (m_head == NULL) 1726 break; 1727 /* 1728 * Pack the data into the transmit ring. If we 1729 * don't have room, set the OACTIVE flag and wait 1730 * for the NIC to drain the ring. 1731 */ 1732 if (age_encap(sc, &m_head)) { 1733 if (m_head == NULL) 1734 break; 1735 if_sendq_prepend(ifp, m_head); 1736 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1737 break; 1738 } 1739 1740 enq++; 1741 /* 1742 * If there's a BPF listener, bounce a copy of this frame 1743 * to him. 1744 */ 1745 ETHER_BPF_MTAP(ifp, m_head); 1746 } 1747 1748 if (enq > 0) { 1749 /* Update mbox. */ 1750 AGE_COMMIT_MBOX(sc); 1751 /* Set a timeout in case the chip goes out to lunch. */ 1752 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1753 } 1754 } 1755 1756 static void 1757 age_watchdog(struct age_softc *sc) 1758 { 1759 if_t ifp; 1760 1761 AGE_LOCK_ASSERT(sc); 1762 1763 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1764 return; 1765 1766 ifp = sc->age_ifp; 1767 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1768 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1769 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1770 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1771 age_init_locked(sc); 1772 return; 1773 } 1774 if (sc->age_cdata.age_tx_cnt == 0) { 1775 if_printf(sc->age_ifp, 1776 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1777 if (!if_sendq_empty(ifp)) 1778 age_start_locked(ifp); 1779 return; 1780 } 1781 if_printf(sc->age_ifp, "watchdog timeout\n"); 1782 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1783 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1784 age_init_locked(sc); 1785 if (!if_sendq_empty(ifp)) 1786 age_start_locked(ifp); 1787 } 1788 1789 static int 1790 age_ioctl(if_t ifp, u_long cmd, caddr_t data) 1791 { 1792 struct age_softc *sc; 1793 struct ifreq *ifr; 1794 struct mii_data *mii; 1795 uint32_t reg; 1796 int error, mask; 1797 1798 sc = if_getsoftc(ifp); 1799 ifr = (struct ifreq *)data; 1800 error = 0; 1801 switch (cmd) { 1802 case SIOCSIFMTU: 1803 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1804 error = EINVAL; 1805 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1806 AGE_LOCK(sc); 1807 if_setmtu(ifp, ifr->ifr_mtu); 1808 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1809 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1810 age_init_locked(sc); 1811 } 1812 AGE_UNLOCK(sc); 1813 } 1814 break; 1815 case SIOCSIFFLAGS: 1816 AGE_LOCK(sc); 1817 if ((if_getflags(ifp) & IFF_UP) != 0) { 1818 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1819 if (((if_getflags(ifp) ^ sc->age_if_flags) 1820 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1821 age_rxfilter(sc); 1822 } else { 1823 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1824 age_init_locked(sc); 1825 } 1826 } else { 1827 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1828 age_stop(sc); 1829 } 1830 sc->age_if_flags = if_getflags(ifp); 1831 AGE_UNLOCK(sc); 1832 break; 1833 case SIOCADDMULTI: 1834 case SIOCDELMULTI: 1835 AGE_LOCK(sc); 1836 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1837 age_rxfilter(sc); 1838 AGE_UNLOCK(sc); 1839 break; 1840 case SIOCSIFMEDIA: 1841 case SIOCGIFMEDIA: 1842 mii = device_get_softc(sc->age_miibus); 1843 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1844 break; 1845 case SIOCSIFCAP: 1846 AGE_LOCK(sc); 1847 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1848 if ((mask & IFCAP_TXCSUM) != 0 && 1849 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1850 if_togglecapenable(ifp, IFCAP_TXCSUM); 1851 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1852 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0); 1853 else 1854 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES); 1855 } 1856 if ((mask & IFCAP_RXCSUM) != 0 && 1857 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1858 if_togglecapenable(ifp, IFCAP_RXCSUM); 1859 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1860 reg &= ~MAC_CFG_RXCSUM_ENB; 1861 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1862 reg |= MAC_CFG_RXCSUM_ENB; 1863 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1864 } 1865 if ((mask & IFCAP_TSO4) != 0 && 1866 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1867 if_togglecapenable(ifp, IFCAP_TSO4); 1868 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 1869 if_sethwassistbits(ifp, CSUM_TSO, 0); 1870 else 1871 if_sethwassistbits(ifp, 0, CSUM_TSO); 1872 } 1873 1874 if ((mask & IFCAP_WOL_MCAST) != 0 && 1875 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 1876 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 1877 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1878 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1879 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1880 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1881 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 1882 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1883 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1884 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1885 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1886 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1887 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1888 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1889 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1890 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1891 age_rxvlan(sc); 1892 } 1893 AGE_UNLOCK(sc); 1894 VLAN_CAPABILITIES(ifp); 1895 break; 1896 default: 1897 error = ether_ioctl(ifp, cmd, data); 1898 break; 1899 } 1900 1901 return (error); 1902 } 1903 1904 static void 1905 age_mac_config(struct age_softc *sc) 1906 { 1907 struct mii_data *mii; 1908 uint32_t reg; 1909 1910 AGE_LOCK_ASSERT(sc); 1911 1912 mii = device_get_softc(sc->age_miibus); 1913 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1914 reg &= ~MAC_CFG_FULL_DUPLEX; 1915 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1916 reg &= ~MAC_CFG_SPEED_MASK; 1917 /* Reprogram MAC with resolved speed/duplex. */ 1918 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1919 case IFM_10_T: 1920 case IFM_100_TX: 1921 reg |= MAC_CFG_SPEED_10_100; 1922 break; 1923 case IFM_1000_T: 1924 reg |= MAC_CFG_SPEED_1000; 1925 break; 1926 } 1927 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1928 reg |= MAC_CFG_FULL_DUPLEX; 1929 #ifdef notyet 1930 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1931 reg |= MAC_CFG_TX_FC; 1932 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1933 reg |= MAC_CFG_RX_FC; 1934 #endif 1935 } 1936 1937 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1938 } 1939 1940 static void 1941 age_link_task(void *arg, int pending) 1942 { 1943 struct age_softc *sc; 1944 struct mii_data *mii; 1945 if_t ifp; 1946 uint32_t reg; 1947 1948 sc = (struct age_softc *)arg; 1949 1950 AGE_LOCK(sc); 1951 mii = device_get_softc(sc->age_miibus); 1952 ifp = sc->age_ifp; 1953 if (mii == NULL || ifp == NULL || 1954 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1955 AGE_UNLOCK(sc); 1956 return; 1957 } 1958 1959 sc->age_flags &= ~AGE_FLAG_LINK; 1960 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1961 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1962 case IFM_10_T: 1963 case IFM_100_TX: 1964 case IFM_1000_T: 1965 sc->age_flags |= AGE_FLAG_LINK; 1966 break; 1967 default: 1968 break; 1969 } 1970 } 1971 1972 /* Stop Rx/Tx MACs. */ 1973 age_stop_rxmac(sc); 1974 age_stop_txmac(sc); 1975 1976 /* Program MACs with resolved speed/duplex/flow-control. */ 1977 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 1978 age_mac_config(sc); 1979 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1980 /* Restart DMA engine and Tx/Rx MAC. */ 1981 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 1982 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 1983 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 1984 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1985 } 1986 1987 AGE_UNLOCK(sc); 1988 } 1989 1990 static void 1991 age_stats_update(struct age_softc *sc) 1992 { 1993 struct age_stats *stat; 1994 struct smb *smb; 1995 if_t ifp; 1996 1997 AGE_LOCK_ASSERT(sc); 1998 1999 stat = &sc->age_stat; 2000 2001 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2002 sc->age_cdata.age_smb_block_map, 2003 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2004 2005 smb = sc->age_rdata.age_smb_block; 2006 if (smb->updated == 0) 2007 return; 2008 2009 ifp = sc->age_ifp; 2010 /* Rx stats. */ 2011 stat->rx_frames += smb->rx_frames; 2012 stat->rx_bcast_frames += smb->rx_bcast_frames; 2013 stat->rx_mcast_frames += smb->rx_mcast_frames; 2014 stat->rx_pause_frames += smb->rx_pause_frames; 2015 stat->rx_control_frames += smb->rx_control_frames; 2016 stat->rx_crcerrs += smb->rx_crcerrs; 2017 stat->rx_lenerrs += smb->rx_lenerrs; 2018 stat->rx_bytes += smb->rx_bytes; 2019 stat->rx_runts += smb->rx_runts; 2020 stat->rx_fragments += smb->rx_fragments; 2021 stat->rx_pkts_64 += smb->rx_pkts_64; 2022 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2023 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2024 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2025 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2026 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2027 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2028 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2029 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2030 stat->rx_desc_oflows += smb->rx_desc_oflows; 2031 stat->rx_alignerrs += smb->rx_alignerrs; 2032 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2033 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2034 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2035 2036 /* Tx stats. */ 2037 stat->tx_frames += smb->tx_frames; 2038 stat->tx_bcast_frames += smb->tx_bcast_frames; 2039 stat->tx_mcast_frames += smb->tx_mcast_frames; 2040 stat->tx_pause_frames += smb->tx_pause_frames; 2041 stat->tx_excess_defer += smb->tx_excess_defer; 2042 stat->tx_control_frames += smb->tx_control_frames; 2043 stat->tx_deferred += smb->tx_deferred; 2044 stat->tx_bytes += smb->tx_bytes; 2045 stat->tx_pkts_64 += smb->tx_pkts_64; 2046 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2047 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2048 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2049 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2050 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2051 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2052 stat->tx_single_colls += smb->tx_single_colls; 2053 stat->tx_multi_colls += smb->tx_multi_colls; 2054 stat->tx_late_colls += smb->tx_late_colls; 2055 stat->tx_excess_colls += smb->tx_excess_colls; 2056 stat->tx_underrun += smb->tx_underrun; 2057 stat->tx_desc_underrun += smb->tx_desc_underrun; 2058 stat->tx_lenerrs += smb->tx_lenerrs; 2059 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2060 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2061 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2062 2063 /* Update counters in ifnet. */ 2064 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2065 2066 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2067 smb->tx_multi_colls + smb->tx_late_colls + 2068 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2069 2070 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2071 smb->tx_late_colls + smb->tx_underrun + 2072 smb->tx_pkts_truncated); 2073 2074 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2075 2076 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2077 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2078 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2079 smb->rx_alignerrs); 2080 2081 /* Update done, clear. */ 2082 smb->updated = 0; 2083 2084 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2085 sc->age_cdata.age_smb_block_map, 2086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2087 } 2088 2089 static int 2090 age_intr(void *arg) 2091 { 2092 struct age_softc *sc; 2093 uint32_t status; 2094 2095 sc = (struct age_softc *)arg; 2096 2097 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2098 if (status == 0 || (status & AGE_INTRS) == 0) 2099 return (FILTER_STRAY); 2100 /* Disable interrupts. */ 2101 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2102 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2103 2104 return (FILTER_HANDLED); 2105 } 2106 2107 static void 2108 age_int_task(void *arg, int pending) 2109 { 2110 struct age_softc *sc; 2111 if_t ifp; 2112 struct cmb *cmb; 2113 uint32_t status; 2114 2115 sc = (struct age_softc *)arg; 2116 2117 AGE_LOCK(sc); 2118 2119 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2120 sc->age_cdata.age_cmb_block_map, 2121 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2122 cmb = sc->age_rdata.age_cmb_block; 2123 status = le32toh(cmb->intr_status); 2124 if (sc->age_morework != 0) 2125 status |= INTR_CMB_RX; 2126 if ((status & AGE_INTRS) == 0) 2127 goto done; 2128 2129 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2130 TPD_CONS_SHIFT; 2131 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2132 RRD_PROD_SHIFT; 2133 /* Let hardware know CMB was served. */ 2134 cmb->intr_status = 0; 2135 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2136 sc->age_cdata.age_cmb_block_map, 2137 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2138 2139 ifp = sc->age_ifp; 2140 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2141 if ((status & INTR_CMB_RX) != 0) 2142 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2143 sc->age_process_limit); 2144 if ((status & INTR_CMB_TX) != 0) 2145 age_txintr(sc, sc->age_tpd_cons); 2146 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2147 if ((status & INTR_DMA_RD_TO_RST) != 0) 2148 device_printf(sc->age_dev, 2149 "DMA read error! -- resetting\n"); 2150 if ((status & INTR_DMA_WR_TO_RST) != 0) 2151 device_printf(sc->age_dev, 2152 "DMA write error! -- resetting\n"); 2153 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2154 age_init_locked(sc); 2155 } 2156 if (!if_sendq_empty(ifp)) 2157 age_start_locked(ifp); 2158 if ((status & INTR_SMB) != 0) 2159 age_stats_update(sc); 2160 } 2161 2162 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2163 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2164 sc->age_cdata.age_cmb_block_map, 2165 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2166 status = le32toh(cmb->intr_status); 2167 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2168 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2169 AGE_UNLOCK(sc); 2170 return; 2171 } 2172 2173 done: 2174 /* Re-enable interrupts. */ 2175 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2176 AGE_UNLOCK(sc); 2177 } 2178 2179 static void 2180 age_txintr(struct age_softc *sc, int tpd_cons) 2181 { 2182 if_t ifp; 2183 struct age_txdesc *txd; 2184 int cons, prog; 2185 2186 AGE_LOCK_ASSERT(sc); 2187 2188 ifp = sc->age_ifp; 2189 2190 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2191 sc->age_cdata.age_tx_ring_map, 2192 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2193 2194 /* 2195 * Go through our Tx list and free mbufs for those 2196 * frames which have been transmitted. 2197 */ 2198 cons = sc->age_cdata.age_tx_cons; 2199 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2200 if (sc->age_cdata.age_tx_cnt <= 0) 2201 break; 2202 prog++; 2203 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2204 sc->age_cdata.age_tx_cnt--; 2205 txd = &sc->age_cdata.age_txdesc[cons]; 2206 /* 2207 * Clear Tx descriptors, it's not required but would 2208 * help debugging in case of Tx issues. 2209 */ 2210 txd->tx_desc->addr = 0; 2211 txd->tx_desc->len = 0; 2212 txd->tx_desc->flags = 0; 2213 2214 if (txd->tx_m == NULL) 2215 continue; 2216 /* Reclaim transmitted mbufs. */ 2217 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2218 BUS_DMASYNC_POSTWRITE); 2219 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2220 m_freem(txd->tx_m); 2221 txd->tx_m = NULL; 2222 } 2223 2224 if (prog > 0) { 2225 sc->age_cdata.age_tx_cons = cons; 2226 2227 /* 2228 * Unarm watchdog timer only when there are no pending 2229 * Tx descriptors in queue. 2230 */ 2231 if (sc->age_cdata.age_tx_cnt == 0) 2232 sc->age_watchdog_timer = 0; 2233 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2234 sc->age_cdata.age_tx_ring_map, 2235 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2236 } 2237 } 2238 2239 #ifndef __NO_STRICT_ALIGNMENT 2240 static struct mbuf * 2241 age_fixup_rx(if_t ifp, struct mbuf *m) 2242 { 2243 struct mbuf *n; 2244 int i; 2245 uint16_t *src, *dst; 2246 2247 src = mtod(m, uint16_t *); 2248 dst = src - 3; 2249 2250 if (m->m_next == NULL) { 2251 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2252 *dst++ = *src++; 2253 m->m_data -= 6; 2254 return (m); 2255 } 2256 /* 2257 * Append a new mbuf to received mbuf chain and copy ethernet 2258 * header from the mbuf chain. This can save lots of CPU 2259 * cycles for jumbo frame. 2260 */ 2261 MGETHDR(n, M_NOWAIT, MT_DATA); 2262 if (n == NULL) { 2263 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2264 m_freem(m); 2265 return (NULL); 2266 } 2267 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2268 m->m_data += ETHER_HDR_LEN; 2269 m->m_len -= ETHER_HDR_LEN; 2270 n->m_len = ETHER_HDR_LEN; 2271 M_MOVE_PKTHDR(n, m); 2272 n->m_next = m; 2273 return (n); 2274 } 2275 #endif 2276 2277 /* Receive a frame. */ 2278 static void 2279 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2280 { 2281 struct age_rxdesc *rxd; 2282 if_t ifp; 2283 struct mbuf *mp, *m; 2284 uint32_t status, index, vtag; 2285 int count, nsegs; 2286 int rx_cons; 2287 2288 AGE_LOCK_ASSERT(sc); 2289 2290 ifp = sc->age_ifp; 2291 status = le32toh(rxrd->flags); 2292 index = le32toh(rxrd->index); 2293 rx_cons = AGE_RX_CONS(index); 2294 nsegs = AGE_RX_NSEGS(index); 2295 2296 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2297 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2298 /* 2299 * We want to pass the following frames to upper 2300 * layer regardless of error status of Rx return 2301 * ring. 2302 * 2303 * o IP/TCP/UDP checksum is bad. 2304 * o frame length and protocol specific length 2305 * does not match. 2306 */ 2307 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2308 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2309 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2310 return; 2311 } 2312 2313 for (count = 0; count < nsegs; count++, 2314 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2315 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2316 mp = rxd->rx_m; 2317 /* Add a new receive buffer to the ring. */ 2318 if (age_newbuf(sc, rxd) != 0) { 2319 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2320 /* Reuse Rx buffers. */ 2321 if (sc->age_cdata.age_rxhead != NULL) 2322 m_freem(sc->age_cdata.age_rxhead); 2323 break; 2324 } 2325 2326 /* 2327 * Assume we've received a full sized frame. 2328 * Actual size is fixed when we encounter the end of 2329 * multi-segmented frame. 2330 */ 2331 mp->m_len = AGE_RX_BUF_SIZE; 2332 2333 /* Chain received mbufs. */ 2334 if (sc->age_cdata.age_rxhead == NULL) { 2335 sc->age_cdata.age_rxhead = mp; 2336 sc->age_cdata.age_rxtail = mp; 2337 } else { 2338 mp->m_flags &= ~M_PKTHDR; 2339 sc->age_cdata.age_rxprev_tail = 2340 sc->age_cdata.age_rxtail; 2341 sc->age_cdata.age_rxtail->m_next = mp; 2342 sc->age_cdata.age_rxtail = mp; 2343 } 2344 2345 if (count == nsegs - 1) { 2346 /* Last desc. for this frame. */ 2347 m = sc->age_cdata.age_rxhead; 2348 m->m_flags |= M_PKTHDR; 2349 /* 2350 * It seems that L1 controller has no way 2351 * to tell hardware to strip CRC bytes. 2352 */ 2353 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2354 ETHER_CRC_LEN; 2355 if (nsegs > 1) { 2356 /* Set last mbuf size. */ 2357 mp->m_len = sc->age_cdata.age_rxlen - 2358 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2359 /* Remove the CRC bytes in chained mbufs. */ 2360 if (mp->m_len <= ETHER_CRC_LEN) { 2361 sc->age_cdata.age_rxtail = 2362 sc->age_cdata.age_rxprev_tail; 2363 sc->age_cdata.age_rxtail->m_len -= 2364 (ETHER_CRC_LEN - mp->m_len); 2365 sc->age_cdata.age_rxtail->m_next = NULL; 2366 m_freem(mp); 2367 } else { 2368 mp->m_len -= ETHER_CRC_LEN; 2369 } 2370 } else 2371 m->m_len = m->m_pkthdr.len; 2372 m->m_pkthdr.rcvif = ifp; 2373 /* 2374 * Set checksum information. 2375 * It seems that L1 controller can compute partial 2376 * checksum. The partial checksum value can be used 2377 * to accelerate checksum computation for fragmented 2378 * TCP/UDP packets. Upper network stack already 2379 * takes advantage of the partial checksum value in 2380 * IP reassembly stage. But I'm not sure the 2381 * correctness of the partial hardware checksum 2382 * assistance due to lack of data sheet. If it is 2383 * proven to work on L1 I'll enable it. 2384 */ 2385 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2386 (status & AGE_RRD_IPV4) != 0) { 2387 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2388 m->m_pkthdr.csum_flags |= 2389 CSUM_IP_CHECKED | CSUM_IP_VALID; 2390 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2391 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2392 m->m_pkthdr.csum_flags |= 2393 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2394 m->m_pkthdr.csum_data = 0xffff; 2395 } 2396 /* 2397 * Don't mark bad checksum for TCP/UDP frames 2398 * as fragmented frames may always have set 2399 * bad checksummed bit of descriptor status. 2400 */ 2401 } 2402 2403 /* Check for VLAN tagged frames. */ 2404 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2405 (status & AGE_RRD_VLAN) != 0) { 2406 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2407 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2408 m->m_flags |= M_VLANTAG; 2409 } 2410 #ifndef __NO_STRICT_ALIGNMENT 2411 m = age_fixup_rx(ifp, m); 2412 if (m != NULL) 2413 #endif 2414 { 2415 /* Pass it on. */ 2416 AGE_UNLOCK(sc); 2417 if_input(ifp, m); 2418 AGE_LOCK(sc); 2419 } 2420 } 2421 } 2422 2423 /* Reset mbuf chains. */ 2424 AGE_RXCHAIN_RESET(sc); 2425 } 2426 2427 static int 2428 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2429 { 2430 struct rx_rdesc *rxrd; 2431 int rr_cons, nsegs, pktlen, prog; 2432 2433 AGE_LOCK_ASSERT(sc); 2434 2435 rr_cons = sc->age_cdata.age_rr_cons; 2436 if (rr_cons == rr_prod) 2437 return (0); 2438 2439 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2440 sc->age_cdata.age_rr_ring_map, 2441 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2442 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2443 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2444 2445 for (prog = 0; rr_cons != rr_prod; prog++) { 2446 if (count-- <= 0) 2447 break; 2448 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2449 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2450 if (nsegs == 0) 2451 break; 2452 /* 2453 * Check number of segments against received bytes. 2454 * Non-matching value would indicate that hardware 2455 * is still trying to update Rx return descriptors. 2456 * I'm not sure whether this check is really needed. 2457 */ 2458 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2459 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2460 break; 2461 2462 /* Received a frame. */ 2463 age_rxeof(sc, rxrd); 2464 /* Clear return ring. */ 2465 rxrd->index = 0; 2466 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2467 sc->age_cdata.age_rx_cons += nsegs; 2468 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2469 } 2470 2471 if (prog > 0) { 2472 /* Update the consumer index. */ 2473 sc->age_cdata.age_rr_cons = rr_cons; 2474 2475 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2476 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2477 /* Sync descriptors. */ 2478 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2479 sc->age_cdata.age_rr_ring_map, 2480 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2481 2482 /* Notify hardware availability of new Rx buffers. */ 2483 AGE_COMMIT_MBOX(sc); 2484 } 2485 2486 return (count > 0 ? 0 : EAGAIN); 2487 } 2488 2489 static void 2490 age_tick(void *arg) 2491 { 2492 struct age_softc *sc; 2493 struct mii_data *mii; 2494 2495 sc = (struct age_softc *)arg; 2496 2497 AGE_LOCK_ASSERT(sc); 2498 2499 mii = device_get_softc(sc->age_miibus); 2500 mii_tick(mii); 2501 age_watchdog(sc); 2502 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2503 } 2504 2505 static void 2506 age_reset(struct age_softc *sc) 2507 { 2508 uint32_t reg; 2509 int i; 2510 2511 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2512 CSR_READ_4(sc, AGE_MASTER_CFG); 2513 DELAY(1000); 2514 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2515 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2516 break; 2517 DELAY(10); 2518 } 2519 2520 if (i == 0) 2521 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2522 /* Initialize PCIe module. From Linux. */ 2523 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2524 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2525 } 2526 2527 static void 2528 age_init(void *xsc) 2529 { 2530 struct age_softc *sc; 2531 2532 sc = (struct age_softc *)xsc; 2533 AGE_LOCK(sc); 2534 age_init_locked(sc); 2535 AGE_UNLOCK(sc); 2536 } 2537 2538 static void 2539 age_init_locked(struct age_softc *sc) 2540 { 2541 if_t ifp; 2542 struct mii_data *mii; 2543 uint8_t eaddr[ETHER_ADDR_LEN]; 2544 bus_addr_t paddr; 2545 uint32_t reg, fsize; 2546 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2547 int error; 2548 2549 AGE_LOCK_ASSERT(sc); 2550 2551 ifp = sc->age_ifp; 2552 mii = device_get_softc(sc->age_miibus); 2553 2554 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2555 return; 2556 2557 /* 2558 * Cancel any pending I/O. 2559 */ 2560 age_stop(sc); 2561 2562 /* 2563 * Reset the chip to a known state. 2564 */ 2565 age_reset(sc); 2566 2567 /* Initialize descriptors. */ 2568 error = age_init_rx_ring(sc); 2569 if (error != 0) { 2570 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2571 age_stop(sc); 2572 return; 2573 } 2574 age_init_rr_ring(sc); 2575 age_init_tx_ring(sc); 2576 age_init_cmb_block(sc); 2577 age_init_smb_block(sc); 2578 2579 /* Reprogram the station address. */ 2580 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2581 CSR_WRITE_4(sc, AGE_PAR0, 2582 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2583 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2584 2585 /* Set descriptor base addresses. */ 2586 paddr = sc->age_rdata.age_tx_ring_paddr; 2587 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2588 paddr = sc->age_rdata.age_rx_ring_paddr; 2589 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2590 paddr = sc->age_rdata.age_rr_ring_paddr; 2591 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2592 paddr = sc->age_rdata.age_tx_ring_paddr; 2593 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2594 paddr = sc->age_rdata.age_cmb_block_paddr; 2595 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2596 paddr = sc->age_rdata.age_smb_block_paddr; 2597 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2598 /* Set Rx/Rx return descriptor counter. */ 2599 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2600 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2601 DESC_RRD_CNT_MASK) | 2602 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2603 /* Set Tx descriptor counter. */ 2604 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2605 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2606 2607 /* Tell hardware that we're ready to load descriptors. */ 2608 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2609 2610 /* 2611 * Initialize mailbox register. 2612 * Updated producer/consumer index information is exchanged 2613 * through this mailbox register. However Tx producer and 2614 * Rx return consumer/Rx producer are all shared such that 2615 * it's hard to separate code path between Tx and Rx without 2616 * locking. If L1 hardware have a separate mail box register 2617 * for Tx and Rx consumer/producer management we could have 2618 * independent Tx/Rx handler which in turn Rx handler could have 2619 * been run without any locking. 2620 */ 2621 AGE_COMMIT_MBOX(sc); 2622 2623 /* Configure IPG/IFG parameters. */ 2624 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2625 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2626 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2627 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2628 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2629 2630 /* Set parameters for half-duplex media. */ 2631 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2632 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2633 HDPX_CFG_LCOL_MASK) | 2634 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2635 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2636 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2637 HDPX_CFG_ABEBT_MASK) | 2638 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2639 HDPX_CFG_JAMIPG_MASK)); 2640 2641 /* Configure interrupt moderation timer. */ 2642 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2643 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2644 reg &= ~MASTER_MTIMER_ENB; 2645 if (AGE_USECS(sc->age_int_mod) == 0) 2646 reg &= ~MASTER_ITIMER_ENB; 2647 else 2648 reg |= MASTER_ITIMER_ENB; 2649 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2650 if (bootverbose) 2651 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2652 sc->age_int_mod); 2653 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2654 2655 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2656 if (if_getmtu(ifp) < ETHERMTU) 2657 sc->age_max_frame_size = ETHERMTU; 2658 else 2659 sc->age_max_frame_size = if_getmtu(ifp); 2660 sc->age_max_frame_size += ETHER_HDR_LEN + 2661 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2662 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2663 /* Configure jumbo frame. */ 2664 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2665 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2666 (((fsize / sizeof(uint64_t)) << 2667 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2668 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2669 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2670 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2671 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2672 2673 /* Configure flow-control parameters. From Linux. */ 2674 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2675 /* 2676 * Magic workaround for old-L1. 2677 * Don't know which hw revision requires this magic. 2678 */ 2679 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2680 /* 2681 * Another magic workaround for flow-control mode 2682 * change. From Linux. 2683 */ 2684 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2685 } 2686 /* 2687 * TODO 2688 * Should understand pause parameter relationships between FIFO 2689 * size and number of Rx descriptors and Rx return descriptors. 2690 * 2691 * Magic parameters came from Linux. 2692 */ 2693 switch (sc->age_chip_rev) { 2694 case 0x8001: 2695 case 0x9001: 2696 case 0x9002: 2697 case 0x9003: 2698 rxf_hi = AGE_RX_RING_CNT / 16; 2699 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2700 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2701 rrd_lo = AGE_RR_RING_CNT / 16; 2702 break; 2703 default: 2704 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2705 rxf_lo = reg / 16; 2706 if (rxf_lo < 192) 2707 rxf_lo = 192; 2708 rxf_hi = (reg * 7) / 8; 2709 if (rxf_hi < rxf_lo) 2710 rxf_hi = rxf_lo + 16; 2711 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2712 rrd_lo = reg / 8; 2713 rrd_hi = (reg * 7) / 8; 2714 if (rrd_lo < 2) 2715 rrd_lo = 2; 2716 if (rrd_hi < rrd_lo) 2717 rrd_hi = rrd_lo + 3; 2718 break; 2719 } 2720 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2721 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2722 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2723 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2724 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2725 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2726 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2727 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2728 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2729 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2730 2731 /* Configure RxQ. */ 2732 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2733 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2734 RXQ_CFG_RD_BURST_MASK) | 2735 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2736 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2737 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2738 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2739 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2740 2741 /* Configure TxQ. */ 2742 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2743 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2744 TXQ_CFG_TPD_BURST_MASK) | 2745 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2746 TXQ_CFG_TX_FIFO_BURST_MASK) | 2747 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2748 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2749 TXQ_CFG_ENB); 2750 2751 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2752 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2753 TX_JUMBO_TPD_TH_MASK) | 2754 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2755 TX_JUMBO_TPD_IPG_MASK)); 2756 /* Configure DMA parameters. */ 2757 CSR_WRITE_4(sc, AGE_DMA_CFG, 2758 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2759 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2760 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2761 2762 /* Configure CMB DMA write threshold. */ 2763 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2764 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2765 CMB_WR_THRESH_RRD_MASK) | 2766 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2767 CMB_WR_THRESH_TPD_MASK)); 2768 2769 /* Set CMB/SMB timer and enable them. */ 2770 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2771 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2772 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2773 /* Request SMB updates for every seconds. */ 2774 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2775 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2776 2777 /* 2778 * Disable all WOL bits as WOL can interfere normal Rx 2779 * operation. 2780 */ 2781 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2782 2783 /* 2784 * Configure Tx/Rx MACs. 2785 * - Auto-padding for short frames. 2786 * - Enable CRC generation. 2787 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2788 * of MAC is followed after link establishment. 2789 */ 2790 CSR_WRITE_4(sc, AGE_MAC_CFG, 2791 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2792 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2793 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2794 MAC_CFG_PREAMBLE_MASK)); 2795 /* Set up the receive filter. */ 2796 age_rxfilter(sc); 2797 age_rxvlan(sc); 2798 2799 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2800 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2801 reg |= MAC_CFG_RXCSUM_ENB; 2802 2803 /* Ack all pending interrupts and clear it. */ 2804 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2805 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2806 2807 /* Finally enable Tx/Rx MAC. */ 2808 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2809 2810 sc->age_flags &= ~AGE_FLAG_LINK; 2811 /* Switch to the current media. */ 2812 mii_mediachg(mii); 2813 2814 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2815 2816 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2817 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2818 } 2819 2820 static void 2821 age_stop(struct age_softc *sc) 2822 { 2823 if_t ifp; 2824 struct age_txdesc *txd; 2825 struct age_rxdesc *rxd; 2826 uint32_t reg; 2827 int i; 2828 2829 AGE_LOCK_ASSERT(sc); 2830 /* 2831 * Mark the interface down and cancel the watchdog timer. 2832 */ 2833 ifp = sc->age_ifp; 2834 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2835 sc->age_flags &= ~AGE_FLAG_LINK; 2836 callout_stop(&sc->age_tick_ch); 2837 sc->age_watchdog_timer = 0; 2838 2839 /* 2840 * Disable interrupts. 2841 */ 2842 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2843 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2844 /* Stop CMB/SMB updates. */ 2845 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2846 /* Stop Rx/Tx MAC. */ 2847 age_stop_rxmac(sc); 2848 age_stop_txmac(sc); 2849 /* Stop DMA. */ 2850 CSR_WRITE_4(sc, AGE_DMA_CFG, 2851 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2852 /* Stop TxQ/RxQ. */ 2853 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2854 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2855 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2856 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2857 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2858 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2859 break; 2860 DELAY(10); 2861 } 2862 if (i == 0) 2863 device_printf(sc->age_dev, 2864 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2865 2866 /* Reclaim Rx buffers that have been processed. */ 2867 if (sc->age_cdata.age_rxhead != NULL) 2868 m_freem(sc->age_cdata.age_rxhead); 2869 AGE_RXCHAIN_RESET(sc); 2870 /* 2871 * Free RX and TX mbufs still in the queues. 2872 */ 2873 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2874 rxd = &sc->age_cdata.age_rxdesc[i]; 2875 if (rxd->rx_m != NULL) { 2876 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2877 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2878 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2879 rxd->rx_dmamap); 2880 m_freem(rxd->rx_m); 2881 rxd->rx_m = NULL; 2882 } 2883 } 2884 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2885 txd = &sc->age_cdata.age_txdesc[i]; 2886 if (txd->tx_m != NULL) { 2887 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2888 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2889 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2890 txd->tx_dmamap); 2891 m_freem(txd->tx_m); 2892 txd->tx_m = NULL; 2893 } 2894 } 2895 } 2896 2897 static void 2898 age_stop_txmac(struct age_softc *sc) 2899 { 2900 uint32_t reg; 2901 int i; 2902 2903 AGE_LOCK_ASSERT(sc); 2904 2905 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2906 if ((reg & MAC_CFG_TX_ENB) != 0) { 2907 reg &= ~MAC_CFG_TX_ENB; 2908 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2909 } 2910 /* Stop Tx DMA engine. */ 2911 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2912 if ((reg & DMA_CFG_RD_ENB) != 0) { 2913 reg &= ~DMA_CFG_RD_ENB; 2914 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2915 } 2916 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2917 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2918 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2919 break; 2920 DELAY(10); 2921 } 2922 if (i == 0) 2923 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2924 } 2925 2926 static void 2927 age_stop_rxmac(struct age_softc *sc) 2928 { 2929 uint32_t reg; 2930 int i; 2931 2932 AGE_LOCK_ASSERT(sc); 2933 2934 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2935 if ((reg & MAC_CFG_RX_ENB) != 0) { 2936 reg &= ~MAC_CFG_RX_ENB; 2937 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2938 } 2939 /* Stop Rx DMA engine. */ 2940 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2941 if ((reg & DMA_CFG_WR_ENB) != 0) { 2942 reg &= ~DMA_CFG_WR_ENB; 2943 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2944 } 2945 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2946 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2947 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2948 break; 2949 DELAY(10); 2950 } 2951 if (i == 0) 2952 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2953 } 2954 2955 static void 2956 age_init_tx_ring(struct age_softc *sc) 2957 { 2958 struct age_ring_data *rd; 2959 struct age_txdesc *txd; 2960 int i; 2961 2962 AGE_LOCK_ASSERT(sc); 2963 2964 sc->age_cdata.age_tx_prod = 0; 2965 sc->age_cdata.age_tx_cons = 0; 2966 sc->age_cdata.age_tx_cnt = 0; 2967 2968 rd = &sc->age_rdata; 2969 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2970 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2971 txd = &sc->age_cdata.age_txdesc[i]; 2972 txd->tx_desc = &rd->age_tx_ring[i]; 2973 txd->tx_m = NULL; 2974 } 2975 2976 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2977 sc->age_cdata.age_tx_ring_map, 2978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2979 } 2980 2981 static int 2982 age_init_rx_ring(struct age_softc *sc) 2983 { 2984 struct age_ring_data *rd; 2985 struct age_rxdesc *rxd; 2986 int i; 2987 2988 AGE_LOCK_ASSERT(sc); 2989 2990 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2991 sc->age_morework = 0; 2992 rd = &sc->age_rdata; 2993 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2994 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2995 rxd = &sc->age_cdata.age_rxdesc[i]; 2996 rxd->rx_m = NULL; 2997 rxd->rx_desc = &rd->age_rx_ring[i]; 2998 if (age_newbuf(sc, rxd) != 0) 2999 return (ENOBUFS); 3000 } 3001 3002 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3003 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3004 3005 return (0); 3006 } 3007 3008 static void 3009 age_init_rr_ring(struct age_softc *sc) 3010 { 3011 struct age_ring_data *rd; 3012 3013 AGE_LOCK_ASSERT(sc); 3014 3015 sc->age_cdata.age_rr_cons = 0; 3016 AGE_RXCHAIN_RESET(sc); 3017 3018 rd = &sc->age_rdata; 3019 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3020 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3021 sc->age_cdata.age_rr_ring_map, 3022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3023 } 3024 3025 static void 3026 age_init_cmb_block(struct age_softc *sc) 3027 { 3028 struct age_ring_data *rd; 3029 3030 AGE_LOCK_ASSERT(sc); 3031 3032 rd = &sc->age_rdata; 3033 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3034 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3035 sc->age_cdata.age_cmb_block_map, 3036 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3037 } 3038 3039 static void 3040 age_init_smb_block(struct age_softc *sc) 3041 { 3042 struct age_ring_data *rd; 3043 3044 AGE_LOCK_ASSERT(sc); 3045 3046 rd = &sc->age_rdata; 3047 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3048 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3049 sc->age_cdata.age_smb_block_map, 3050 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3051 } 3052 3053 static int 3054 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3055 { 3056 struct rx_desc *desc; 3057 struct mbuf *m; 3058 bus_dma_segment_t segs[1]; 3059 bus_dmamap_t map; 3060 int nsegs; 3061 3062 AGE_LOCK_ASSERT(sc); 3063 3064 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3065 if (m == NULL) 3066 return (ENOBUFS); 3067 m->m_len = m->m_pkthdr.len = MCLBYTES; 3068 #ifndef __NO_STRICT_ALIGNMENT 3069 m_adj(m, AGE_RX_BUF_ALIGN); 3070 #endif 3071 3072 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3073 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3074 m_freem(m); 3075 return (ENOBUFS); 3076 } 3077 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3078 3079 if (rxd->rx_m != NULL) { 3080 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3081 BUS_DMASYNC_POSTREAD); 3082 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3083 } 3084 map = rxd->rx_dmamap; 3085 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3086 sc->age_cdata.age_rx_sparemap = map; 3087 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3088 BUS_DMASYNC_PREREAD); 3089 rxd->rx_m = m; 3090 3091 desc = rxd->rx_desc; 3092 desc->addr = htole64(segs[0].ds_addr); 3093 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3094 AGE_RD_LEN_SHIFT); 3095 return (0); 3096 } 3097 3098 static void 3099 age_rxvlan(struct age_softc *sc) 3100 { 3101 if_t ifp; 3102 uint32_t reg; 3103 3104 AGE_LOCK_ASSERT(sc); 3105 3106 ifp = sc->age_ifp; 3107 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3108 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3109 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3110 reg |= MAC_CFG_VLAN_TAG_STRIP; 3111 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3112 } 3113 3114 static u_int 3115 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3116 { 3117 uint32_t *mchash = arg; 3118 uint32_t crc; 3119 3120 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3121 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3122 3123 return (1); 3124 } 3125 3126 static void 3127 age_rxfilter(struct age_softc *sc) 3128 { 3129 if_t ifp; 3130 uint32_t mchash[2]; 3131 uint32_t rxcfg; 3132 3133 AGE_LOCK_ASSERT(sc); 3134 3135 ifp = sc->age_ifp; 3136 3137 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3138 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3139 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3140 rxcfg |= MAC_CFG_BCAST; 3141 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3142 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3143 rxcfg |= MAC_CFG_PROMISC; 3144 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3145 rxcfg |= MAC_CFG_ALLMULTI; 3146 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3147 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3148 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3149 return; 3150 } 3151 3152 /* Program new filter. */ 3153 bzero(mchash, sizeof(mchash)); 3154 if_foreach_llmaddr(ifp, age_hash_maddr, mchash); 3155 3156 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3157 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3158 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3159 } 3160 3161 static int 3162 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3163 { 3164 struct age_softc *sc; 3165 struct age_stats *stats; 3166 int error, result; 3167 3168 result = -1; 3169 error = sysctl_handle_int(oidp, &result, 0, req); 3170 3171 if (error != 0 || req->newptr == NULL) 3172 return (error); 3173 3174 if (result != 1) 3175 return (error); 3176 3177 sc = (struct age_softc *)arg1; 3178 stats = &sc->age_stat; 3179 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3180 printf("Transmit good frames : %ju\n", 3181 (uintmax_t)stats->tx_frames); 3182 printf("Transmit good broadcast frames : %ju\n", 3183 (uintmax_t)stats->tx_bcast_frames); 3184 printf("Transmit good multicast frames : %ju\n", 3185 (uintmax_t)stats->tx_mcast_frames); 3186 printf("Transmit pause control frames : %u\n", 3187 stats->tx_pause_frames); 3188 printf("Transmit control frames : %u\n", 3189 stats->tx_control_frames); 3190 printf("Transmit frames with excessive deferrals : %u\n", 3191 stats->tx_excess_defer); 3192 printf("Transmit deferrals : %u\n", 3193 stats->tx_deferred); 3194 printf("Transmit good octets : %ju\n", 3195 (uintmax_t)stats->tx_bytes); 3196 printf("Transmit good broadcast octets : %ju\n", 3197 (uintmax_t)stats->tx_bcast_bytes); 3198 printf("Transmit good multicast octets : %ju\n", 3199 (uintmax_t)stats->tx_mcast_bytes); 3200 printf("Transmit frames 64 bytes : %ju\n", 3201 (uintmax_t)stats->tx_pkts_64); 3202 printf("Transmit frames 65 to 127 bytes : %ju\n", 3203 (uintmax_t)stats->tx_pkts_65_127); 3204 printf("Transmit frames 128 to 255 bytes : %ju\n", 3205 (uintmax_t)stats->tx_pkts_128_255); 3206 printf("Transmit frames 256 to 511 bytes : %ju\n", 3207 (uintmax_t)stats->tx_pkts_256_511); 3208 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3209 (uintmax_t)stats->tx_pkts_512_1023); 3210 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3211 (uintmax_t)stats->tx_pkts_1024_1518); 3212 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3213 (uintmax_t)stats->tx_pkts_1519_max); 3214 printf("Transmit single collisions : %u\n", 3215 stats->tx_single_colls); 3216 printf("Transmit multiple collisions : %u\n", 3217 stats->tx_multi_colls); 3218 printf("Transmit late collisions : %u\n", 3219 stats->tx_late_colls); 3220 printf("Transmit abort due to excessive collisions : %u\n", 3221 stats->tx_excess_colls); 3222 printf("Transmit underruns due to FIFO underruns : %u\n", 3223 stats->tx_underrun); 3224 printf("Transmit descriptor write-back errors : %u\n", 3225 stats->tx_desc_underrun); 3226 printf("Transmit frames with length mismatched frame size : %u\n", 3227 stats->tx_lenerrs); 3228 printf("Transmit frames with truncated due to MTU size : %u\n", 3229 stats->tx_lenerrs); 3230 3231 printf("Receive good frames : %ju\n", 3232 (uintmax_t)stats->rx_frames); 3233 printf("Receive good broadcast frames : %ju\n", 3234 (uintmax_t)stats->rx_bcast_frames); 3235 printf("Receive good multicast frames : %ju\n", 3236 (uintmax_t)stats->rx_mcast_frames); 3237 printf("Receive pause control frames : %u\n", 3238 stats->rx_pause_frames); 3239 printf("Receive control frames : %u\n", 3240 stats->rx_control_frames); 3241 printf("Receive CRC errors : %u\n", 3242 stats->rx_crcerrs); 3243 printf("Receive frames with length errors : %u\n", 3244 stats->rx_lenerrs); 3245 printf("Receive good octets : %ju\n", 3246 (uintmax_t)stats->rx_bytes); 3247 printf("Receive good broadcast octets : %ju\n", 3248 (uintmax_t)stats->rx_bcast_bytes); 3249 printf("Receive good multicast octets : %ju\n", 3250 (uintmax_t)stats->rx_mcast_bytes); 3251 printf("Receive frames too short : %u\n", 3252 stats->rx_runts); 3253 printf("Receive fragmented frames : %ju\n", 3254 (uintmax_t)stats->rx_fragments); 3255 printf("Receive frames 64 bytes : %ju\n", 3256 (uintmax_t)stats->rx_pkts_64); 3257 printf("Receive frames 65 to 127 bytes : %ju\n", 3258 (uintmax_t)stats->rx_pkts_65_127); 3259 printf("Receive frames 128 to 255 bytes : %ju\n", 3260 (uintmax_t)stats->rx_pkts_128_255); 3261 printf("Receive frames 256 to 511 bytes : %ju\n", 3262 (uintmax_t)stats->rx_pkts_256_511); 3263 printf("Receive frames 512 to 1024 bytes : %ju\n", 3264 (uintmax_t)stats->rx_pkts_512_1023); 3265 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3266 (uintmax_t)stats->rx_pkts_1024_1518); 3267 printf("Receive frames 1519 to MTU bytes : %ju\n", 3268 (uintmax_t)stats->rx_pkts_1519_max); 3269 printf("Receive frames too long : %ju\n", 3270 (uint64_t)stats->rx_pkts_truncated); 3271 printf("Receive frames with FIFO overflow : %u\n", 3272 stats->rx_fifo_oflows); 3273 printf("Receive frames with return descriptor overflow : %u\n", 3274 stats->rx_desc_oflows); 3275 printf("Receive frames with alignment errors : %u\n", 3276 stats->rx_alignerrs); 3277 printf("Receive frames dropped due to address filtering : %ju\n", 3278 (uint64_t)stats->rx_pkts_filtered); 3279 3280 return (error); 3281 } 3282 3283 static int 3284 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3285 { 3286 int error, value; 3287 3288 if (arg1 == NULL) 3289 return (EINVAL); 3290 value = *(int *)arg1; 3291 error = sysctl_handle_int(oidp, &value, 0, req); 3292 if (error || req->newptr == NULL) 3293 return (error); 3294 if (value < low || value > high) 3295 return (EINVAL); 3296 *(int *)arg1 = value; 3297 3298 return (0); 3299 } 3300 3301 static int 3302 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3303 { 3304 return (sysctl_int_range(oidp, arg1, arg2, req, 3305 AGE_PROC_MIN, AGE_PROC_MAX)); 3306 } 3307 3308 static int 3309 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3310 { 3311 3312 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3313 AGE_IM_TIMER_MAX)); 3314 } 3315