1 /*- 2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 26 * 27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <machine/bus.h> 68 69 #include "miibus_if.h" 70 71 #include "if_aereg.h" 72 #include "if_aevar.h" 73 74 /* 75 * Devices supported by this driver. 76 */ 77 static struct ae_dev { 78 uint16_t vendorid; 79 uint16_t deviceid; 80 const char *name; 81 } ae_devs[] = { 82 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 83 "Attansic Technology Corp, L2 FastEthernet" }, 84 }; 85 #define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs)) 86 87 static struct resource_spec ae_res_spec_mem[] = { 88 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 89 { -1, 0, 0 } 90 }; 91 static struct resource_spec ae_res_spec_irq[] = { 92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 93 { -1, 0, 0 } 94 }; 95 static struct resource_spec ae_res_spec_msi[] = { 96 { SYS_RES_IRQ, 1, RF_ACTIVE }, 97 { -1, 0, 0 } 98 }; 99 100 static int ae_probe(device_t dev); 101 static int ae_attach(device_t dev); 102 static void ae_pcie_init(ae_softc_t *sc); 103 static void ae_phy_reset(ae_softc_t *sc); 104 static void ae_phy_init(ae_softc_t *sc); 105 static int ae_reset(ae_softc_t *sc); 106 static void ae_init(void *arg); 107 static int ae_init_locked(ae_softc_t *sc); 108 static int ae_detach(device_t dev); 109 static int ae_miibus_readreg(device_t dev, int phy, int reg); 110 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 111 static void ae_miibus_statchg(device_t dev); 112 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 113 static int ae_mediachange(struct ifnet *ifp); 114 static void ae_retrieve_address(ae_softc_t *sc); 115 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 116 int error); 117 static int ae_alloc_rings(ae_softc_t *sc); 118 static void ae_dma_free(ae_softc_t *sc); 119 static int ae_shutdown(device_t dev); 120 static int ae_suspend(device_t dev); 121 static void ae_powersave_disable(ae_softc_t *sc); 122 static void ae_powersave_enable(ae_softc_t *sc); 123 static int ae_resume(device_t dev); 124 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 125 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 126 static void ae_start(struct ifnet *ifp); 127 static void ae_link_task(void *arg, int pending); 128 static void ae_stop_rxmac(ae_softc_t *sc); 129 static void ae_stop_txmac(ae_softc_t *sc); 130 static void ae_tx_task(void *arg, int pending); 131 static void ae_mac_config(ae_softc_t *sc); 132 static int ae_intr(void *arg); 133 static void ae_int_task(void *arg, int pending); 134 static void ae_tx_intr(ae_softc_t *sc); 135 static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 136 static void ae_rx_intr(ae_softc_t *sc); 137 static void ae_watchdog(ae_softc_t *sc); 138 static void ae_tick(void *arg); 139 static void ae_rxfilter(ae_softc_t *sc); 140 static void ae_rxvlan(ae_softc_t *sc); 141 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142 static void ae_stop(ae_softc_t *sc); 143 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 144 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 145 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 146 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 147 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 148 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 149 static void ae_init_tunables(ae_softc_t *sc); 150 151 static device_method_t ae_methods[] = { 152 /* Device interface. */ 153 DEVMETHOD(device_probe, ae_probe), 154 DEVMETHOD(device_attach, ae_attach), 155 DEVMETHOD(device_detach, ae_detach), 156 DEVMETHOD(device_shutdown, ae_shutdown), 157 DEVMETHOD(device_suspend, ae_suspend), 158 DEVMETHOD(device_resume, ae_resume), 159 160 /* MII interface. */ 161 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 162 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 163 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 164 165 { NULL, NULL } 166 }; 167 static driver_t ae_driver = { 168 "ae", 169 ae_methods, 170 sizeof(ae_softc_t) 171 }; 172 static devclass_t ae_devclass; 173 174 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 175 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 176 MODULE_DEPEND(ae, pci, 1, 1, 1); 177 MODULE_DEPEND(ae, ether, 1, 1, 1); 178 MODULE_DEPEND(ae, miibus, 1, 1, 1); 179 180 /* 181 * Tunables. 182 */ 183 static int msi_disable = 0; 184 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 185 186 #define AE_READ_4(sc, reg) \ 187 bus_read_4((sc)->mem[0], (reg)) 188 #define AE_READ_2(sc, reg) \ 189 bus_read_2((sc)->mem[0], (reg)) 190 #define AE_READ_1(sc, reg) \ 191 bus_read_1((sc)->mem[0], (reg)) 192 #define AE_WRITE_4(sc, reg, val) \ 193 bus_write_4((sc)->mem[0], (reg), (val)) 194 #define AE_WRITE_2(sc, reg, val) \ 195 bus_write_2((sc)->mem[0], (reg), (val)) 196 #define AE_WRITE_1(sc, reg, val) \ 197 bus_write_1((sc)->mem[0], (reg), (val)) 198 #define AE_PHY_READ(sc, reg) \ 199 ae_miibus_readreg(sc->dev, 0, reg) 200 #define AE_PHY_WRITE(sc, reg, val) \ 201 ae_miibus_writereg(sc->dev, 0, reg, val) 202 #define AE_CHECK_EADDR_VALID(eaddr) \ 203 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 204 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 205 #define AE_RXD_VLAN(vtag) \ 206 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 207 #define AE_TXD_VLAN(vtag) \ 208 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 209 210 /* 211 * ae statistics. 212 */ 213 #define STATS_ENTRY(node, desc, field) \ 214 { node, desc, offsetof(struct ae_stats, field) } 215 struct { 216 const char *node; 217 const char *desc; 218 intptr_t offset; 219 } ae_stats_tx[] = { 220 STATS_ENTRY("bcast", "broadcast frames", tx_bcast), 221 STATS_ENTRY("mcast", "multicast frames", tx_mcast), 222 STATS_ENTRY("pause", "PAUSE frames", tx_pause), 223 STATS_ENTRY("control", "control frames", tx_ctrl), 224 STATS_ENTRY("defers", "deferrals occuried", tx_defer), 225 STATS_ENTRY("exc_defers", "excessive deferrals occuried", tx_excdefer), 226 STATS_ENTRY("singlecols", "single collisions occuried", tx_singlecol), 227 STATS_ENTRY("multicols", "multiple collisions occuried", tx_multicol), 228 STATS_ENTRY("latecols", "late collisions occuried", tx_latecol), 229 STATS_ENTRY("aborts", "transmit aborts due collisions", tx_abortcol), 230 STATS_ENTRY("underruns", "Tx FIFO underruns", tx_underrun) 231 }, ae_stats_rx[] = { 232 STATS_ENTRY("bcast", "broadcast frames", rx_bcast), 233 STATS_ENTRY("mcast", "multicast frames", rx_mcast), 234 STATS_ENTRY("pause", "PAUSE frames", rx_pause), 235 STATS_ENTRY("control", "control frames", rx_ctrl), 236 STATS_ENTRY("crc_errors", "frames with CRC errors", rx_crcerr), 237 STATS_ENTRY("code_errors", "frames with invalid opcode", rx_codeerr), 238 STATS_ENTRY("runt", "runt frames", rx_runt), 239 STATS_ENTRY("frag", "fragmented frames", rx_frag), 240 STATS_ENTRY("align_errors", "frames with alignment errors", rx_align), 241 STATS_ENTRY("truncated", "frames truncated due to Rx FIFO inderrun", 242 rx_trunc) 243 }; 244 #define AE_STATS_RX_LEN (sizeof(ae_stats_rx) / sizeof(*ae_stats_rx)) 245 #define AE_STATS_TX_LEN (sizeof(ae_stats_tx) / sizeof(*ae_stats_tx)) 246 247 static int 248 ae_probe(device_t dev) 249 { 250 uint16_t deviceid, vendorid; 251 int i; 252 253 vendorid = pci_get_vendor(dev); 254 deviceid = pci_get_device(dev); 255 256 /* 257 * Search through the list of supported devs for matching one. 258 */ 259 for (i = 0; i < AE_DEVS_COUNT; i++) { 260 if (vendorid == ae_devs[i].vendorid && 261 deviceid == ae_devs[i].deviceid) { 262 device_set_desc(dev, ae_devs[i].name); 263 return (BUS_PROBE_DEFAULT); 264 } 265 } 266 return (ENXIO); 267 } 268 269 static int 270 ae_attach(device_t dev) 271 { 272 ae_softc_t *sc; 273 struct ifnet *ifp; 274 uint8_t chiprev; 275 uint32_t pcirev; 276 int nmsi, pmc; 277 int error; 278 279 sc = device_get_softc(dev); /* Automatically allocated and zeroed 280 on attach. */ 281 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 282 sc->dev = dev; 283 284 /* 285 * Initialize mutexes and tasks. 286 */ 287 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 288 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 289 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 290 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 291 292 pci_enable_busmaster(dev); /* Enable bus mastering. */ 293 294 sc->spec_mem = ae_res_spec_mem; 295 296 /* 297 * Allocate memory-mapped registers. 298 */ 299 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 300 if (error != 0) { 301 device_printf(dev, "could not allocate memory resources.\n"); 302 sc->spec_mem = NULL; 303 goto fail; 304 } 305 306 /* 307 * Retrieve PCI and chip revisions. 308 */ 309 pcirev = pci_get_revid(dev); 310 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 311 AE_MASTER_REVNUM_MASK; 312 if (bootverbose) { 313 device_printf(dev, "pci device revision: %#04x\n", pcirev); 314 device_printf(dev, "chip id: %#02x\n", chiprev); 315 } 316 nmsi = pci_msi_count(dev); 317 if (bootverbose) 318 device_printf(dev, "MSI count: %d.\n", nmsi); 319 320 /* 321 * Allocate interrupt resources. 322 */ 323 if (msi_disable == 0 && nmsi == 1) { 324 error = pci_alloc_msi(dev, &nmsi); 325 if (error == 0) { 326 device_printf(dev, "Using MSI messages.\n"); 327 sc->spec_irq = ae_res_spec_msi; 328 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 329 if (error != 0) { 330 device_printf(dev, "MSI allocation failed.\n"); 331 sc->spec_irq = NULL; 332 pci_release_msi(dev); 333 } else { 334 sc->flags |= AE_FLAG_MSI; 335 } 336 } 337 } 338 if (sc->spec_irq == NULL) { 339 sc->spec_irq = ae_res_spec_irq; 340 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 341 if (error != 0) { 342 device_printf(dev, "could not allocate IRQ resources.\n"); 343 sc->spec_irq = NULL; 344 goto fail; 345 } 346 } 347 348 ae_init_tunables(sc); 349 350 ae_phy_reset(sc); /* Reset PHY. */ 351 error = ae_reset(sc); /* Reset the controller itself. */ 352 if (error != 0) 353 goto fail; 354 355 ae_pcie_init(sc); 356 357 ae_retrieve_address(sc); /* Load MAC address. */ 358 359 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 360 if (error != 0) 361 goto fail; 362 363 ifp = sc->ifp = if_alloc(IFT_ETHER); 364 if (ifp == NULL) { 365 device_printf(dev, "could not allocate ifnet structure.\n"); 366 error = ENXIO; 367 goto fail; 368 } 369 370 ifp->if_softc = sc; 371 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 ifp->if_ioctl = ae_ioctl; 374 ifp->if_start = ae_start; 375 ifp->if_init = ae_init; 376 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 377 ifp->if_hwassist = 0; 378 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 379 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 380 IFQ_SET_READY(&ifp->if_snd); 381 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 382 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 383 sc->flags |= AE_FLAG_PMG; 384 } 385 ifp->if_capenable = ifp->if_capabilities; 386 387 /* 388 * Configure and attach MII bus. 389 */ 390 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 391 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 392 MII_OFFSET_ANY, 0); 393 if (error != 0) { 394 device_printf(dev, "attaching PHYs failed\n"); 395 goto fail; 396 } 397 398 ether_ifattach(ifp, sc->eaddr); 399 /* Tell the upper layer(s) we support long frames. */ 400 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 401 402 /* 403 * Create and run all helper tasks. 404 */ 405 TASK_INIT(&sc->tx_task, 1, ae_tx_task, ifp); 406 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 407 taskqueue_thread_enqueue, &sc->tq); 408 if (sc->tq == NULL) { 409 device_printf(dev, "could not create taskqueue.\n"); 410 ether_ifdetach(ifp); 411 error = ENXIO; 412 goto fail; 413 } 414 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 415 device_get_nameunit(sc->dev)); 416 417 /* 418 * Configure interrupt handlers. 419 */ 420 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 421 ae_intr, NULL, sc, &sc->intrhand); 422 if (error != 0) { 423 device_printf(dev, "could not set up interrupt handler.\n"); 424 taskqueue_free(sc->tq); 425 sc->tq = NULL; 426 ether_ifdetach(ifp); 427 goto fail; 428 } 429 430 fail: 431 if (error != 0) 432 ae_detach(dev); 433 434 return (error); 435 } 436 437 static void 438 ae_init_tunables(ae_softc_t *sc) 439 { 440 struct sysctl_ctx_list *ctx; 441 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 442 struct ae_stats *ae_stats; 443 unsigned int i; 444 445 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 446 ae_stats = &sc->stats; 447 448 ctx = device_get_sysctl_ctx(sc->dev); 449 root = device_get_sysctl_tree(sc->dev); 450 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 451 CTLFLAG_RD, NULL, "ae statistics"); 452 453 /* 454 * Receiver statistcics. 455 */ 456 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 457 CTLFLAG_RD, NULL, "Rx MAC statistics"); 458 for (i = 0; i < AE_STATS_RX_LEN; i++) 459 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_rx), OID_AUTO, 460 ae_stats_rx[i].node, CTLFLAG_RD, (char *)ae_stats + 461 ae_stats_rx[i].offset, 0, ae_stats_rx[i].desc); 462 463 /* 464 * Receiver statistcics. 465 */ 466 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 467 CTLFLAG_RD, NULL, "Tx MAC statistics"); 468 for (i = 0; i < AE_STATS_TX_LEN; i++) 469 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_tx), OID_AUTO, 470 ae_stats_tx[i].node, CTLFLAG_RD, (char *)ae_stats + 471 ae_stats_tx[i].offset, 0, ae_stats_tx[i].desc); 472 } 473 474 static void 475 ae_pcie_init(ae_softc_t *sc) 476 { 477 478 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 479 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 480 } 481 482 static void 483 ae_phy_reset(ae_softc_t *sc) 484 { 485 486 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 487 DELAY(1000); /* XXX: pause(9) ? */ 488 } 489 490 static int 491 ae_reset(ae_softc_t *sc) 492 { 493 int i; 494 495 /* 496 * Issue a soft reset. 497 */ 498 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 499 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 500 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 501 502 /* 503 * Wait for reset to complete. 504 */ 505 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 506 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 507 break; 508 DELAY(10); 509 } 510 if (i == AE_RESET_TIMEOUT) { 511 device_printf(sc->dev, "reset timeout.\n"); 512 return (ENXIO); 513 } 514 515 /* 516 * Wait for everything to enter idle state. 517 */ 518 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 519 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 520 break; 521 DELAY(100); 522 } 523 if (i == AE_IDLE_TIMEOUT) { 524 device_printf(sc->dev, "could not enter idle state.\n"); 525 return (ENXIO); 526 } 527 return (0); 528 } 529 530 static void 531 ae_init(void *arg) 532 { 533 ae_softc_t *sc; 534 535 sc = (ae_softc_t *)arg; 536 AE_LOCK(sc); 537 ae_init_locked(sc); 538 AE_UNLOCK(sc); 539 } 540 541 static void 542 ae_phy_init(ae_softc_t *sc) 543 { 544 545 /* 546 * Enable link status change interrupt. 547 * XXX magic numbers. 548 */ 549 #ifdef notyet 550 AE_PHY_WRITE(sc, 18, 0xc00); 551 #endif 552 } 553 554 static int 555 ae_init_locked(ae_softc_t *sc) 556 { 557 struct ifnet *ifp; 558 struct mii_data *mii; 559 uint8_t eaddr[ETHER_ADDR_LEN]; 560 uint32_t val; 561 bus_addr_t addr; 562 563 AE_LOCK_ASSERT(sc); 564 565 ifp = sc->ifp; 566 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 567 return (0); 568 mii = device_get_softc(sc->miibus); 569 570 ae_stop(sc); 571 ae_reset(sc); 572 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 573 ae_phy_init(sc); 574 ae_powersave_disable(sc); 575 576 /* 577 * Clear and disable interrupts. 578 */ 579 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 580 581 /* 582 * Set the MAC address. 583 */ 584 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 585 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 586 AE_WRITE_4(sc, AE_EADDR0_REG, val); 587 val = eaddr[0] << 8 | eaddr[1]; 588 AE_WRITE_4(sc, AE_EADDR1_REG, val); 589 590 /* 591 * Set ring buffers base addresses. 592 */ 593 addr = sc->dma_rxd_busaddr; 594 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 595 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 596 addr = sc->dma_txd_busaddr; 597 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 598 addr = sc->dma_txs_busaddr; 599 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 600 601 /* 602 * Configure ring buffers sizes. 603 */ 604 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 605 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 606 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 607 608 /* 609 * Configure interframe gap parameters. 610 */ 611 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 612 AE_IFG_TXIPG_MASK) | 613 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 614 AE_IFG_RXIPG_MASK) | 615 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 616 AE_IFG_IPGR1_MASK) | 617 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 618 AE_IFG_IPGR2_MASK); 619 AE_WRITE_4(sc, AE_IFG_REG, val); 620 621 /* 622 * Configure half-duplex operation. 623 */ 624 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 625 AE_HDPX_LCOL_MASK) | 626 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 627 AE_HDPX_RETRY_MASK) | 628 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 629 AE_HDPX_ABEBT_MASK) | 630 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 631 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 632 AE_WRITE_4(sc, AE_HDPX_REG, val); 633 634 /* 635 * Configure interrupt moderate timer. 636 */ 637 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 638 val = AE_READ_4(sc, AE_MASTER_REG); 639 val |= AE_MASTER_IMT_EN; 640 AE_WRITE_4(sc, AE_MASTER_REG, val); 641 642 /* 643 * Configure interrupt clearing timer. 644 */ 645 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 646 647 /* 648 * Configure MTU. 649 */ 650 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 651 ETHER_CRC_LEN; 652 AE_WRITE_2(sc, AE_MTU_REG, val); 653 654 /* 655 * Configure cut-through threshold. 656 */ 657 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 658 659 /* 660 * Configure flow control. 661 */ 662 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 663 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 664 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 665 (AE_RXD_COUNT_DEFAULT / 12)); 666 667 /* 668 * Init mailboxes. 669 */ 670 sc->txd_cur = sc->rxd_cur = 0; 671 sc->txs_ack = sc->txd_ack = 0; 672 sc->rxd_cur = 0; 673 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 674 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 675 676 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 677 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 678 679 /* 680 * Enable DMA. 681 */ 682 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 683 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 684 685 /* 686 * Check if everything is OK. 687 */ 688 val = AE_READ_4(sc, AE_ISR_REG); 689 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 690 device_printf(sc->dev, "Initialization failed.\n"); 691 return (ENXIO); 692 } 693 694 /* 695 * Clear interrupt status. 696 */ 697 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 698 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 699 700 /* 701 * Enable interrupts. 702 */ 703 val = AE_READ_4(sc, AE_MASTER_REG); 704 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 705 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 706 707 /* 708 * Disable WOL. 709 */ 710 AE_WRITE_4(sc, AE_WOL_REG, 0); 711 712 /* 713 * Configure MAC. 714 */ 715 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 716 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 717 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 718 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 719 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 720 AE_MAC_PREAMBLE_MASK); 721 AE_WRITE_4(sc, AE_MAC_REG, val); 722 723 /* 724 * Configure Rx MAC. 725 */ 726 ae_rxfilter(sc); 727 ae_rxvlan(sc); 728 729 /* 730 * Enable Tx/Rx. 731 */ 732 val = AE_READ_4(sc, AE_MAC_REG); 733 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 734 735 sc->flags &= ~AE_FLAG_LINK; 736 mii_mediachg(mii); /* Switch to the current media. */ 737 738 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 739 740 ifp->if_drv_flags |= IFF_DRV_RUNNING; 741 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 742 743 #ifdef AE_DEBUG 744 device_printf(sc->dev, "Initialization complete.\n"); 745 #endif 746 747 return (0); 748 } 749 750 static int 751 ae_detach(device_t dev) 752 { 753 struct ae_softc *sc; 754 struct ifnet *ifp; 755 756 sc = device_get_softc(dev); 757 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 758 ifp = sc->ifp; 759 if (device_is_attached(dev)) { 760 AE_LOCK(sc); 761 sc->flags |= AE_FLAG_DETACH; 762 ae_stop(sc); 763 AE_UNLOCK(sc); 764 callout_drain(&sc->tick_ch); 765 taskqueue_drain(sc->tq, &sc->int_task); 766 taskqueue_drain(sc->tq, &sc->tx_task); 767 taskqueue_drain(taskqueue_swi, &sc->link_task); 768 ether_ifdetach(ifp); 769 } 770 if (sc->tq != NULL) { 771 taskqueue_drain(sc->tq, &sc->int_task); 772 taskqueue_free(sc->tq); 773 sc->tq = NULL; 774 } 775 if (sc->miibus != NULL) { 776 device_delete_child(dev, sc->miibus); 777 sc->miibus = NULL; 778 } 779 bus_generic_detach(sc->dev); 780 ae_dma_free(sc); 781 if (sc->intrhand != NULL) { 782 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 783 sc->intrhand = NULL; 784 } 785 if (ifp != NULL) { 786 if_free(ifp); 787 sc->ifp = NULL; 788 } 789 if (sc->spec_irq != NULL) 790 bus_release_resources(dev, sc->spec_irq, sc->irq); 791 if (sc->spec_mem != NULL) 792 bus_release_resources(dev, sc->spec_mem, sc->mem); 793 if ((sc->flags & AE_FLAG_MSI) != 0) 794 pci_release_msi(dev); 795 mtx_destroy(&sc->mtx); 796 797 return (0); 798 } 799 800 static int 801 ae_miibus_readreg(device_t dev, int phy, int reg) 802 { 803 ae_softc_t *sc; 804 uint32_t val; 805 int i; 806 807 sc = device_get_softc(dev); 808 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 809 810 /* 811 * Locking is done in upper layers. 812 */ 813 814 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 815 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 816 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 817 AE_WRITE_4(sc, AE_MDIO_REG, val); 818 819 /* 820 * Wait for operation to complete. 821 */ 822 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 823 DELAY(2); 824 val = AE_READ_4(sc, AE_MDIO_REG); 825 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 826 break; 827 } 828 if (i == AE_MDIO_TIMEOUT) { 829 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 830 return (0); 831 } 832 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 833 } 834 835 static int 836 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 837 { 838 ae_softc_t *sc; 839 uint32_t aereg; 840 int i; 841 842 sc = device_get_softc(dev); 843 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 844 845 /* 846 * Locking is done in upper layers. 847 */ 848 849 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 850 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 851 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 852 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 853 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 854 855 /* 856 * Wait for operation to complete. 857 */ 858 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 859 DELAY(2); 860 aereg = AE_READ_4(sc, AE_MDIO_REG); 861 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 862 break; 863 } 864 if (i == AE_MDIO_TIMEOUT) { 865 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 866 } 867 return (0); 868 } 869 870 static void 871 ae_miibus_statchg(device_t dev) 872 { 873 ae_softc_t *sc; 874 875 sc = device_get_softc(dev); 876 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 877 } 878 879 static void 880 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 881 { 882 ae_softc_t *sc; 883 struct mii_data *mii; 884 885 sc = ifp->if_softc; 886 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 887 888 AE_LOCK(sc); 889 mii = device_get_softc(sc->miibus); 890 mii_pollstat(mii); 891 ifmr->ifm_status = mii->mii_media_status; 892 ifmr->ifm_active = mii->mii_media_active; 893 AE_UNLOCK(sc); 894 } 895 896 static int 897 ae_mediachange(struct ifnet *ifp) 898 { 899 ae_softc_t *sc; 900 struct mii_data *mii; 901 struct mii_softc *mii_sc; 902 int error; 903 904 /* XXX: check IFF_UP ?? */ 905 sc = ifp->if_softc; 906 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 907 AE_LOCK(sc); 908 mii = device_get_softc(sc->miibus); 909 if (mii->mii_instance != 0) { 910 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 911 mii_phy_reset(mii_sc); 912 } 913 error = mii_mediachg(mii); 914 AE_UNLOCK(sc); 915 916 return (error); 917 } 918 919 static int 920 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 921 { 922 int error; 923 uint32_t val; 924 925 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 926 927 /* 928 * Not sure why, but Linux does this. 929 */ 930 val = AE_READ_4(sc, AE_SPICTL_REG); 931 if ((val & AE_SPICTL_VPD_EN) != 0) { 932 val &= ~AE_SPICTL_VPD_EN; 933 AE_WRITE_4(sc, AE_SPICTL_REG, val); 934 } 935 error = pci_find_extcap(sc->dev, PCIY_VPD, vpdc); 936 return (error); 937 } 938 939 static int 940 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 941 { 942 uint32_t val; 943 int i; 944 945 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 946 947 /* 948 * VPD registers start at offset 0x100. Read them. 949 */ 950 val = 0x100 + reg * 4; 951 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 952 AE_VPD_CAP_ADDR_MASK); 953 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 954 DELAY(2000); 955 val = AE_READ_4(sc, AE_VPD_CAP_REG); 956 if ((val & AE_VPD_CAP_DONE) != 0) 957 break; 958 } 959 if (i == AE_VPD_TIMEOUT) { 960 device_printf(sc->dev, "timeout reading VPD register %d.\n", 961 reg); 962 return (ETIMEDOUT); 963 } 964 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 965 return (0); 966 } 967 968 static int 969 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 970 { 971 uint32_t word, reg, val; 972 int error; 973 int found; 974 int vpdc; 975 int i; 976 977 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 978 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 979 980 /* 981 * Check for EEPROM. 982 */ 983 error = ae_check_eeprom_present(sc, &vpdc); 984 if (error != 0) 985 return (error); 986 987 /* 988 * Read the VPD configuration space. 989 * Each register is prefixed with signature, 990 * so we can check if it is valid. 991 */ 992 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 993 error = ae_vpd_read_word(sc, i, &word); 994 if (error != 0) 995 break; 996 997 /* 998 * Check signature. 999 */ 1000 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1001 break; 1002 reg = word >> AE_VPD_REG_SHIFT; 1003 i++; /* Move to the next word. */ 1004 1005 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1006 continue; 1007 1008 error = ae_vpd_read_word(sc, i, &val); 1009 if (error != 0) 1010 break; 1011 if (reg == AE_EADDR0_REG) 1012 eaddr[0] = val; 1013 else 1014 eaddr[1] = val; 1015 found++; 1016 } 1017 1018 if (found < 2) 1019 return (ENOENT); 1020 1021 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1022 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1023 if (bootverbose) 1024 device_printf(sc->dev, 1025 "VPD ethernet address registers are invalid.\n"); 1026 return (EINVAL); 1027 } 1028 return (0); 1029 } 1030 1031 static int 1032 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1033 { 1034 1035 /* 1036 * BIOS is supposed to set this. 1037 */ 1038 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1039 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1040 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1041 1042 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1043 if (bootverbose) 1044 device_printf(sc->dev, 1045 "Ethernet address registers are invalid.\n"); 1046 return (EINVAL); 1047 } 1048 return (0); 1049 } 1050 1051 static void 1052 ae_retrieve_address(ae_softc_t *sc) 1053 { 1054 uint32_t eaddr[2] = {0, 0}; 1055 int error; 1056 1057 /* 1058 *Check for EEPROM. 1059 */ 1060 error = ae_get_vpd_eaddr(sc, eaddr); 1061 if (error != 0) 1062 error = ae_get_reg_eaddr(sc, eaddr); 1063 if (error != 0) { 1064 if (bootverbose) 1065 device_printf(sc->dev, 1066 "Generating random ethernet address.\n"); 1067 eaddr[0] = arc4random(); 1068 1069 /* 1070 * Set OUI to ASUSTek COMPUTER INC. 1071 */ 1072 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1073 sc->eaddr[1] = 0x1f; 1074 sc->eaddr[2] = 0xc6; 1075 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1076 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1077 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1078 } else { 1079 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1080 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1081 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1082 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1083 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1084 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1085 } 1086 } 1087 1088 static void 1089 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1090 { 1091 bus_addr_t *addr = arg; 1092 1093 if (error != 0) 1094 return; 1095 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1096 nsegs)); 1097 *addr = segs[0].ds_addr; 1098 } 1099 1100 static int 1101 ae_alloc_rings(ae_softc_t *sc) 1102 { 1103 bus_addr_t busaddr; 1104 int error; 1105 1106 /* 1107 * Create parent DMA tag. 1108 */ 1109 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1110 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1111 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1112 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1113 &sc->dma_parent_tag); 1114 if (error != 0) { 1115 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1116 return (error); 1117 } 1118 1119 /* 1120 * Create DMA tag for TxD. 1121 */ 1122 error = bus_dma_tag_create(sc->dma_parent_tag, 1123 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1124 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1125 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1126 &sc->dma_txd_tag); 1127 if (error != 0) { 1128 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1129 return (error); 1130 } 1131 1132 /* 1133 * Create DMA tag for TxS. 1134 */ 1135 error = bus_dma_tag_create(sc->dma_parent_tag, 1136 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1137 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1138 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1139 &sc->dma_txs_tag); 1140 if (error != 0) { 1141 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1142 return (error); 1143 } 1144 1145 /* 1146 * Create DMA tag for RxD. 1147 */ 1148 error = bus_dma_tag_create(sc->dma_parent_tag, 1149 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1150 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1, 1151 AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL, 1152 &sc->dma_rxd_tag); 1153 if (error != 0) { 1154 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1155 return (error); 1156 } 1157 1158 /* 1159 * Allocate TxD DMA memory. 1160 */ 1161 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1162 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1163 &sc->dma_txd_map); 1164 if (error != 0) { 1165 device_printf(sc->dev, 1166 "could not allocate DMA memory for TxD ring.\n"); 1167 return (error); 1168 } 1169 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1170 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1171 if (error != 0 || busaddr == 0) { 1172 device_printf(sc->dev, 1173 "could not load DMA map for TxD ring.\n"); 1174 return (error); 1175 } 1176 sc->dma_txd_busaddr = busaddr; 1177 1178 /* 1179 * Allocate TxS DMA memory. 1180 */ 1181 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1182 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1183 &sc->dma_txs_map); 1184 if (error != 0) { 1185 device_printf(sc->dev, 1186 "could not allocate DMA memory for TxS ring.\n"); 1187 return (error); 1188 } 1189 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1190 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1191 if (error != 0 || busaddr == 0) { 1192 device_printf(sc->dev, 1193 "could not load DMA map for TxS ring.\n"); 1194 return (error); 1195 } 1196 sc->dma_txs_busaddr = busaddr; 1197 1198 /* 1199 * Allocate RxD DMA memory. 1200 */ 1201 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1202 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1203 &sc->dma_rxd_map); 1204 if (error != 0) { 1205 device_printf(sc->dev, 1206 "could not allocate DMA memory for RxD ring.\n"); 1207 return (error); 1208 } 1209 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1210 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb, 1211 &busaddr, BUS_DMA_NOWAIT); 1212 if (error != 0 || busaddr == 0) { 1213 device_printf(sc->dev, 1214 "could not load DMA map for RxD ring.\n"); 1215 return (error); 1216 } 1217 sc->dma_rxd_busaddr = busaddr + 120; 1218 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120); 1219 1220 return (0); 1221 } 1222 1223 static void 1224 ae_dma_free(ae_softc_t *sc) 1225 { 1226 1227 if (sc->dma_txd_tag != NULL) { 1228 if (sc->dma_txd_map != NULL) { 1229 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1230 if (sc->txd_base != NULL) 1231 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1232 sc->dma_txd_map); 1233 1234 } 1235 bus_dma_tag_destroy(sc->dma_txd_tag); 1236 sc->dma_txd_map = NULL; 1237 sc->dma_txd_tag = NULL; 1238 sc->txd_base = NULL; 1239 } 1240 if (sc->dma_txs_tag != NULL) { 1241 if (sc->dma_txs_map != NULL) { 1242 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1243 if (sc->txs_base != NULL) 1244 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1245 sc->dma_txs_map); 1246 1247 } 1248 bus_dma_tag_destroy(sc->dma_txs_tag); 1249 sc->dma_txs_map = NULL; 1250 sc->dma_txs_tag = NULL; 1251 sc->txs_base = NULL; 1252 } 1253 if (sc->dma_rxd_tag != NULL) { 1254 if (sc->dma_rxd_map != NULL) { 1255 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1256 if (sc->rxd_base_dma != NULL) 1257 bus_dmamem_free(sc->dma_rxd_tag, 1258 sc->rxd_base_dma, sc->dma_rxd_map); 1259 1260 } 1261 bus_dma_tag_destroy(sc->dma_rxd_tag); 1262 sc->dma_rxd_map = NULL; 1263 sc->dma_rxd_tag = NULL; 1264 sc->rxd_base_dma = NULL; 1265 } 1266 if (sc->dma_parent_tag != NULL) { 1267 bus_dma_tag_destroy(sc->dma_parent_tag); 1268 sc->dma_parent_tag = NULL; 1269 } 1270 } 1271 1272 static int 1273 ae_shutdown(device_t dev) 1274 { 1275 ae_softc_t *sc; 1276 int error; 1277 1278 sc = device_get_softc(dev); 1279 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1280 1281 error = ae_suspend(dev); 1282 AE_LOCK(sc); 1283 ae_powersave_enable(sc); 1284 AE_UNLOCK(sc); 1285 return (error); 1286 } 1287 1288 static void 1289 ae_powersave_disable(ae_softc_t *sc) 1290 { 1291 uint32_t val; 1292 1293 AE_LOCK_ASSERT(sc); 1294 1295 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1296 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1297 if (val & AE_PHY_DBG_POWERSAVE) { 1298 val &= ~AE_PHY_DBG_POWERSAVE; 1299 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1300 DELAY(1000); 1301 } 1302 } 1303 1304 static void 1305 ae_powersave_enable(ae_softc_t *sc) 1306 { 1307 uint32_t val; 1308 1309 AE_LOCK_ASSERT(sc); 1310 1311 /* 1312 * XXX magic numbers. 1313 */ 1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1315 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1316 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1317 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1318 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1319 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1320 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1321 } 1322 1323 static void 1324 ae_pm_init(ae_softc_t *sc) 1325 { 1326 struct ifnet *ifp; 1327 uint32_t val; 1328 uint16_t pmstat; 1329 struct mii_data *mii; 1330 int pmc; 1331 1332 AE_LOCK_ASSERT(sc); 1333 1334 ifp = sc->ifp; 1335 if ((sc->flags & AE_FLAG_PMG) == 0) { 1336 /* Disable WOL entirely. */ 1337 AE_WRITE_4(sc, AE_WOL_REG, 0); 1338 return; 1339 } 1340 1341 /* 1342 * Configure WOL if enabled. 1343 */ 1344 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1345 mii = device_get_softc(sc->miibus); 1346 mii_pollstat(mii); 1347 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1348 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1349 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1350 AE_WOL_MAGIC_PME); 1351 1352 /* 1353 * Configure MAC. 1354 */ 1355 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1356 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1357 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1358 AE_HALFBUF_MASK) | \ 1359 ((AE_MAC_PREAMBLE_DEFAULT << \ 1360 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1361 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1362 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1363 IFM_FDX) != 0) 1364 val |= AE_MAC_FULL_DUPLEX; 1365 AE_WRITE_4(sc, AE_MAC_REG, val); 1366 1367 } else { /* No link. */ 1368 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1369 AE_WOL_LNKCHG_PME); 1370 AE_WRITE_4(sc, AE_MAC_REG, 0); 1371 } 1372 } else { 1373 ae_powersave_enable(sc); 1374 } 1375 1376 /* 1377 * PCIE hacks. Magic numbers. 1378 */ 1379 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1380 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1381 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1382 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1383 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1384 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1385 1386 /* 1387 * Configure PME. 1388 */ 1389 pci_find_extcap(sc->dev, PCIY_PMG, &pmc); 1390 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1391 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1392 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1393 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1394 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1395 } 1396 1397 static int 1398 ae_suspend(device_t dev) 1399 { 1400 ae_softc_t *sc; 1401 1402 sc = device_get_softc(dev); 1403 1404 AE_LOCK(sc); 1405 ae_stop(sc); 1406 ae_pm_init(sc); 1407 AE_UNLOCK(sc); 1408 1409 return (0); 1410 } 1411 1412 static int 1413 ae_resume(device_t dev) 1414 { 1415 ae_softc_t *sc; 1416 1417 sc = device_get_softc(dev); 1418 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1419 1420 AE_LOCK(sc); 1421 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1422 if ((sc->ifp->if_flags & IFF_UP) != 0) 1423 ae_init_locked(sc); 1424 AE_UNLOCK(sc); 1425 1426 return (0); 1427 } 1428 1429 static unsigned int 1430 ae_tx_avail_size(ae_softc_t *sc) 1431 { 1432 unsigned int avail; 1433 1434 if (sc->txd_cur >= sc->txd_ack) 1435 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1436 else 1437 avail = sc->txd_ack - sc->txd_cur; 1438 1439 return (avail - 4); /* 4-byte header. */ 1440 } 1441 1442 static int 1443 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1444 { 1445 struct mbuf *m0; 1446 ae_txd_t *hdr; 1447 unsigned int to_end; 1448 uint16_t len; 1449 1450 AE_LOCK_ASSERT(sc); 1451 1452 m0 = *m_head; 1453 len = m0->m_pkthdr.len; 1454 1455 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1456 ae_tx_avail_size(sc) < len) { 1457 #ifdef AE_DEBUG 1458 if_printf(sc->ifp, "No free Tx available.\n"); 1459 #endif 1460 return ENOBUFS; 1461 } 1462 1463 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1464 bzero(hdr, sizeof(*hdr)); 1465 sc->txd_cur = (sc->txd_cur + 4) % AE_TXD_BUFSIZE_DEFAULT; /* Header 1466 size. */ 1467 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; /* Space available to 1468 * the end of the ring 1469 */ 1470 if (to_end >= len) { 1471 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1472 } else { 1473 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1474 sc->txd_cur)); 1475 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1476 } 1477 1478 /* 1479 * Set TxD flags and parameters. 1480 */ 1481 if ((m0->m_flags & M_VLANTAG) != 0) { 1482 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1483 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1484 } else { 1485 hdr->len = htole16(len); 1486 } 1487 1488 /* 1489 * Set current TxD position and round up to a 4-byte boundary. 1490 */ 1491 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1492 if (sc->txd_cur == sc->txd_ack) 1493 sc->flags &= ~AE_FLAG_TXAVAIL; 1494 #ifdef AE_DEBUG 1495 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1496 #endif 1497 1498 /* 1499 * Update TxS position and check if there are empty TxS available. 1500 */ 1501 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1502 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1503 if (sc->txs_cur == sc->txs_ack) 1504 sc->flags &= ~AE_FLAG_TXAVAIL; 1505 1506 /* 1507 * Synchronize DMA memory. 1508 */ 1509 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1510 BUS_DMASYNC_PREWRITE); 1511 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1512 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1513 1514 return (0); 1515 } 1516 1517 static void 1518 ae_start(struct ifnet *ifp) 1519 { 1520 ae_softc_t *sc; 1521 unsigned int count; 1522 struct mbuf *m0; 1523 int error; 1524 1525 sc = ifp->if_softc; 1526 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1527 AE_LOCK(sc); 1528 1529 #ifdef AE_DEBUG 1530 if_printf(ifp, "Start called.\n"); 1531 #endif 1532 1533 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1534 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) { 1535 AE_UNLOCK(sc); 1536 return; 1537 } 1538 1539 count = 0; 1540 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1541 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1542 if (m0 == NULL) 1543 break; /* Nothing to do. */ 1544 1545 error = ae_encap(sc, &m0); 1546 if (error != 0) { 1547 if (m0 != NULL) { 1548 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1549 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1550 #ifdef AE_DEBUG 1551 if_printf(ifp, "Setting OACTIVE.\n"); 1552 #endif 1553 } 1554 break; 1555 } 1556 count++; 1557 sc->tx_inproc++; 1558 1559 /* Bounce a copy of the frame to BPF. */ 1560 ETHER_BPF_MTAP(ifp, m0); 1561 1562 m_freem(m0); 1563 } 1564 1565 if (count > 0) { /* Something was dequeued. */ 1566 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1567 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1568 #ifdef AE_DEBUG 1569 if_printf(ifp, "%d packets dequeued.\n", count); 1570 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1571 #endif 1572 } 1573 AE_UNLOCK(sc); 1574 } 1575 1576 static void 1577 ae_link_task(void *arg, int pending) 1578 { 1579 ae_softc_t *sc; 1580 struct mii_data *mii; 1581 struct ifnet *ifp; 1582 uint32_t val; 1583 1584 sc = (ae_softc_t *)arg; 1585 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1586 AE_LOCK(sc); 1587 1588 ifp = sc->ifp; 1589 mii = device_get_softc(sc->miibus); 1590 if (mii == NULL || ifp == NULL || 1591 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1592 AE_UNLOCK(sc); /* XXX: could happen? */ 1593 return; 1594 } 1595 1596 sc->flags &= ~AE_FLAG_LINK; 1597 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1598 (IFM_AVALID | IFM_ACTIVE)) { 1599 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1600 case IFM_10_T: 1601 case IFM_100_TX: 1602 sc->flags |= AE_FLAG_LINK; 1603 break; 1604 default: 1605 break; 1606 } 1607 } 1608 1609 /* 1610 * Stop Rx/Tx MACs. 1611 */ 1612 ae_stop_rxmac(sc); 1613 ae_stop_txmac(sc); 1614 1615 if ((sc->flags & AE_FLAG_LINK) != 0) { 1616 ae_mac_config(sc); 1617 1618 /* 1619 * Restart DMA engines. 1620 */ 1621 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1622 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1623 1624 /* 1625 * Enable Rx and Tx MACs. 1626 */ 1627 val = AE_READ_4(sc, AE_MAC_REG); 1628 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1629 AE_WRITE_4(sc, AE_MAC_REG, val); 1630 } 1631 AE_UNLOCK(sc); 1632 } 1633 1634 static void 1635 ae_stop_rxmac(ae_softc_t *sc) 1636 { 1637 uint32_t val; 1638 int i; 1639 1640 AE_LOCK_ASSERT(sc); 1641 1642 /* 1643 * Stop Rx MAC engine. 1644 */ 1645 val = AE_READ_4(sc, AE_MAC_REG); 1646 if ((val & AE_MAC_RX_EN) != 0) { 1647 val &= ~AE_MAC_RX_EN; 1648 AE_WRITE_4(sc, AE_MAC_REG, val); 1649 } 1650 1651 /* 1652 * Stop Rx DMA engine. 1653 */ 1654 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1655 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1656 1657 /* 1658 * Wait for IDLE state. 1659 */ 1660 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1661 val = AE_READ_4(sc, AE_IDLE_REG); 1662 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1663 break; 1664 DELAY(100); 1665 } 1666 if (i == AE_IDLE_TIMEOUT) 1667 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1668 } 1669 1670 static void 1671 ae_stop_txmac(ae_softc_t *sc) 1672 { 1673 uint32_t val; 1674 int i; 1675 1676 AE_LOCK_ASSERT(sc); 1677 1678 /* 1679 * Stop Tx MAC engine. 1680 */ 1681 val = AE_READ_4(sc, AE_MAC_REG); 1682 if ((val & AE_MAC_TX_EN) != 0) { 1683 val &= ~AE_MAC_TX_EN; 1684 AE_WRITE_4(sc, AE_MAC_REG, val); 1685 } 1686 1687 /* 1688 * Stop Tx DMA engine. 1689 */ 1690 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1691 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1692 1693 /* 1694 * Wait for IDLE state. 1695 */ 1696 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1697 val = AE_READ_4(sc, AE_IDLE_REG); 1698 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1699 break; 1700 DELAY(100); 1701 } 1702 if (i == AE_IDLE_TIMEOUT) 1703 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1704 } 1705 1706 static void 1707 ae_tx_task(void *arg, int pending) 1708 { 1709 struct ifnet *ifp; 1710 1711 ifp = (struct ifnet *)arg; 1712 ae_start(ifp); 1713 } 1714 1715 static void 1716 ae_mac_config(ae_softc_t *sc) 1717 { 1718 struct mii_data *mii; 1719 uint32_t val; 1720 1721 AE_LOCK_ASSERT(sc); 1722 1723 mii = device_get_softc(sc->miibus); 1724 val = AE_READ_4(sc, AE_MAC_REG); 1725 val &= ~AE_MAC_FULL_DUPLEX; 1726 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1727 1728 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1729 val |= AE_MAC_FULL_DUPLEX; 1730 1731 AE_WRITE_4(sc, AE_MAC_REG, val); 1732 } 1733 1734 static int 1735 ae_intr(void *arg) 1736 { 1737 ae_softc_t *sc; 1738 uint32_t val; 1739 1740 sc = (ae_softc_t *)arg; 1741 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1742 1743 val = AE_READ_4(sc, AE_ISR_REG); 1744 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1745 return (FILTER_STRAY); 1746 1747 /* Disable interrupts. */ 1748 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1749 1750 /* Schedule interrupt processing. */ 1751 taskqueue_enqueue(sc->tq, &sc->int_task); 1752 1753 return (FILTER_HANDLED); 1754 } 1755 1756 static void 1757 ae_int_task(void *arg, int pending) 1758 { 1759 ae_softc_t *sc; 1760 struct ifnet *ifp; 1761 uint32_t val; 1762 1763 sc = (ae_softc_t *)arg; 1764 1765 AE_LOCK(sc); 1766 1767 ifp = sc->ifp; 1768 1769 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1770 1771 /* 1772 * Clear interrupts and disable them. 1773 */ 1774 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1775 1776 #ifdef AE_DEBUG 1777 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1778 #endif 1779 1780 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1781 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1782 AE_ISR_PHY_LINKDOWN)) != 0) { 1783 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1784 ae_init_locked(sc); 1785 AE_UNLOCK(sc); 1786 return; 1787 } 1788 if ((val & AE_ISR_TX_EVENT) != 0) 1789 ae_tx_intr(sc); 1790 if ((val & AE_ISR_RX_EVENT) != 0) 1791 ae_rx_intr(sc); 1792 } 1793 1794 /* 1795 * Re-enable interrupts. 1796 */ 1797 AE_WRITE_4(sc, AE_ISR_REG, 0); 1798 1799 AE_UNLOCK(sc); 1800 } 1801 1802 static void 1803 ae_tx_intr(ae_softc_t *sc) 1804 { 1805 struct ifnet *ifp; 1806 ae_txd_t *txd; 1807 ae_txs_t *txs; 1808 uint16_t flags; 1809 1810 AE_LOCK_ASSERT(sc); 1811 1812 ifp = sc->ifp; 1813 1814 #ifdef AE_DEBUG 1815 if_printf(ifp, "Tx interrupt occuried.\n"); 1816 #endif 1817 1818 /* 1819 * Syncronize DMA buffers. 1820 */ 1821 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1822 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1823 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1825 1826 for (;;) { 1827 txs = sc->txs_base + sc->txs_ack; 1828 flags = le16toh(txs->flags); 1829 if ((flags & AE_TXS_UPDATE) == 0) 1830 break; 1831 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1832 /* Update stats. */ 1833 ae_update_stats_tx(flags, &sc->stats); 1834 1835 /* 1836 * Update TxS position. 1837 */ 1838 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1839 sc->flags |= AE_FLAG_TXAVAIL; 1840 1841 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1842 if (txs->len != txd->len) 1843 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1844 le16toh(txs->len), le16toh(txd->len)); 1845 1846 /* 1847 * Move txd ack and align on 4-byte boundary. 1848 */ 1849 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 4 + 3) & ~3) % 1850 AE_TXD_BUFSIZE_DEFAULT; 1851 1852 if ((flags & AE_TXS_SUCCESS) != 0) 1853 ifp->if_opackets++; 1854 else 1855 ifp->if_oerrors++; 1856 1857 sc->tx_inproc--; 1858 1859 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1860 } 1861 1862 if (sc->tx_inproc < 0) { 1863 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1864 sc->tx_inproc = 0; 1865 } 1866 1867 if (sc->tx_inproc == 0) 1868 sc->wd_timer = 0; /* Unarm watchdog. */ 1869 1870 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1871 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1872 taskqueue_enqueue(sc->tq, &sc->tx_task); 1873 } 1874 1875 /* 1876 * Syncronize DMA buffers. 1877 */ 1878 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1880 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1882 } 1883 1884 static int 1885 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1886 { 1887 struct ifnet *ifp; 1888 struct mbuf *m; 1889 unsigned int size; 1890 uint16_t flags; 1891 1892 AE_LOCK_ASSERT(sc); 1893 1894 ifp = sc->ifp; 1895 flags = le16toh(rxd->flags); 1896 1897 #ifdef AE_DEBUG 1898 if_printf(ifp, "Rx interrupt occuried.\n"); 1899 #endif 1900 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1901 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1902 if_printf(ifp, "Runt frame received."); 1903 return (EIO); 1904 } 1905 1906 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1907 if (m == NULL) 1908 return (ENOBUFS); 1909 1910 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1911 (flags & AE_RXD_HAS_VLAN) != 0) { 1912 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1913 m->m_flags |= M_VLANTAG; 1914 } 1915 1916 /* 1917 * Pass it through. 1918 */ 1919 AE_UNLOCK(sc); 1920 (*ifp->if_input)(ifp, m); 1921 AE_LOCK(sc); 1922 1923 return (0); 1924 } 1925 1926 static void 1927 ae_rx_intr(ae_softc_t *sc) 1928 { 1929 ae_rxd_t *rxd; 1930 struct ifnet *ifp; 1931 uint16_t flags; 1932 int error; 1933 1934 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1935 1936 AE_LOCK_ASSERT(sc); 1937 1938 ifp = sc->ifp; 1939 1940 /* 1941 * Syncronize DMA buffers. 1942 */ 1943 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1944 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1945 1946 for (;;) { 1947 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1948 flags = le16toh(rxd->flags); 1949 if ((flags & AE_RXD_UPDATE) == 0) 1950 break; 1951 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1952 /* Update stats. */ 1953 ae_update_stats_rx(flags, &sc->stats); 1954 1955 /* 1956 * Update position index. 1957 */ 1958 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1959 1960 if ((flags & AE_RXD_SUCCESS) == 0) { 1961 ifp->if_ierrors++; 1962 continue; 1963 } 1964 error = ae_rxeof(sc, rxd); 1965 if (error != 0) { 1966 ifp->if_ierrors++; 1967 continue; 1968 } else { 1969 ifp->if_ipackets++; 1970 } 1971 } 1972 1973 /* 1974 * Update Rx index. 1975 */ 1976 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1977 } 1978 1979 static void 1980 ae_watchdog(ae_softc_t *sc) 1981 { 1982 struct ifnet *ifp; 1983 1984 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1985 AE_LOCK_ASSERT(sc); 1986 ifp = sc->ifp; 1987 1988 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1989 return; /* Noting to do. */ 1990 1991 if ((sc->flags & AE_FLAG_LINK) == 0) 1992 if_printf(ifp, "watchdog timeout (missed link).\n"); 1993 else 1994 if_printf(ifp, "watchdog timeout - resetting.\n"); 1995 1996 ifp->if_oerrors++; 1997 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1998 ae_init_locked(sc); 1999 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2000 taskqueue_enqueue(sc->tq, &sc->tx_task); 2001 } 2002 2003 static void 2004 ae_tick(void *arg) 2005 { 2006 ae_softc_t *sc; 2007 struct mii_data *mii; 2008 2009 sc = (ae_softc_t *)arg; 2010 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2011 AE_LOCK_ASSERT(sc); 2012 2013 mii = device_get_softc(sc->miibus); 2014 mii_tick(mii); 2015 ae_watchdog(sc); /* Watchdog check. */ 2016 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2017 } 2018 2019 static void 2020 ae_rxvlan(ae_softc_t *sc) 2021 { 2022 struct ifnet *ifp; 2023 uint32_t val; 2024 2025 AE_LOCK_ASSERT(sc); 2026 ifp = sc->ifp; 2027 val = AE_READ_4(sc, AE_MAC_REG); 2028 val &= ~AE_MAC_RMVLAN_EN; 2029 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2030 val |= AE_MAC_RMVLAN_EN; 2031 AE_WRITE_4(sc, AE_MAC_REG, val); 2032 } 2033 2034 static void 2035 ae_rxfilter(ae_softc_t *sc) 2036 { 2037 struct ifnet *ifp; 2038 struct ifmultiaddr *ifma; 2039 uint32_t crc; 2040 uint32_t mchash[2]; 2041 uint32_t rxcfg; 2042 2043 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2044 2045 AE_LOCK_ASSERT(sc); 2046 2047 ifp = sc->ifp; 2048 2049 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2050 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2051 2052 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2053 rxcfg |= AE_MAC_BCAST_EN; 2054 if ((ifp->if_flags & IFF_PROMISC) != 0) 2055 rxcfg |= AE_MAC_PROMISC_EN; 2056 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2057 rxcfg |= AE_MAC_MCAST_EN; 2058 2059 /* 2060 * Wipe old settings. 2061 */ 2062 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2063 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2064 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2065 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2066 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2067 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2068 return; 2069 } 2070 2071 /* 2072 * Load multicast tables. 2073 */ 2074 bzero(mchash, sizeof(mchash)); 2075 if_maddr_rlock(ifp); 2076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2077 if (ifma->ifma_addr->sa_family != AF_LINK) 2078 continue; 2079 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2080 ifma->ifma_addr), ETHER_ADDR_LEN); 2081 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2082 } 2083 if_maddr_runlock(ifp); 2084 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2085 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2086 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2087 } 2088 2089 static int 2090 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2091 { 2092 struct ae_softc *sc; 2093 struct ifreq *ifr; 2094 struct mii_data *mii; 2095 int error, mask; 2096 2097 sc = ifp->if_softc; 2098 ifr = (struct ifreq *)data; 2099 error = 0; 2100 2101 switch (cmd) { 2102 case SIOCSIFMTU: 2103 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2104 error = EINVAL; 2105 else if (ifp->if_mtu != ifr->ifr_mtu) { 2106 AE_LOCK(sc); 2107 ifp->if_mtu = ifr->ifr_mtu; 2108 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2109 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2110 ae_init_locked(sc); 2111 } 2112 AE_UNLOCK(sc); 2113 } 2114 break; 2115 case SIOCSIFFLAGS: 2116 AE_LOCK(sc); 2117 if ((ifp->if_flags & IFF_UP) != 0) { 2118 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2119 if (((ifp->if_flags ^ sc->if_flags) 2120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2121 ae_rxfilter(sc); 2122 } else { 2123 if ((sc->flags & AE_FLAG_DETACH) == 0) 2124 ae_init_locked(sc); 2125 } 2126 } else { 2127 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2128 ae_stop(sc); 2129 } 2130 sc->if_flags = ifp->if_flags; 2131 AE_UNLOCK(sc); 2132 break; 2133 case SIOCADDMULTI: 2134 case SIOCDELMULTI: 2135 AE_LOCK(sc); 2136 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2137 ae_rxfilter(sc); 2138 AE_UNLOCK(sc); 2139 break; 2140 case SIOCSIFMEDIA: 2141 case SIOCGIFMEDIA: 2142 mii = device_get_softc(sc->miibus); 2143 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2144 break; 2145 case SIOCSIFCAP: 2146 AE_LOCK(sc); 2147 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2148 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2149 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2150 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2151 ae_rxvlan(sc); 2152 } 2153 VLAN_CAPABILITIES(ifp); 2154 AE_UNLOCK(sc); 2155 break; 2156 default: 2157 error = ether_ioctl(ifp, cmd, data); 2158 break; 2159 } 2160 return (error); 2161 } 2162 2163 static void 2164 ae_stop(ae_softc_t *sc) 2165 { 2166 struct ifnet *ifp; 2167 int i; 2168 2169 AE_LOCK_ASSERT(sc); 2170 2171 ifp = sc->ifp; 2172 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2173 sc->flags &= ~AE_FLAG_LINK; 2174 sc->wd_timer = 0; /* Cancel watchdog. */ 2175 callout_stop(&sc->tick_ch); 2176 2177 /* 2178 * Clear and disable interrupts. 2179 */ 2180 AE_WRITE_4(sc, AE_IMR_REG, 0); 2181 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2182 2183 /* 2184 * Stop Rx/Tx MACs. 2185 */ 2186 ae_stop_txmac(sc); 2187 ae_stop_rxmac(sc); 2188 2189 /* 2190 * Stop DMA engines. 2191 */ 2192 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2193 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2194 2195 /* 2196 * Wait for everything to enter idle state. 2197 */ 2198 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2199 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2200 break; 2201 DELAY(100); 2202 } 2203 if (i == AE_IDLE_TIMEOUT) 2204 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2205 } 2206 2207 static void 2208 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2209 { 2210 2211 if ((flags & AE_TXS_BCAST) != 0) 2212 stats->tx_bcast++; 2213 if ((flags & AE_TXS_MCAST) != 0) 2214 stats->tx_mcast++; 2215 if ((flags & AE_TXS_PAUSE) != 0) 2216 stats->tx_pause++; 2217 if ((flags & AE_TXS_CTRL) != 0) 2218 stats->tx_ctrl++; 2219 if ((flags & AE_TXS_DEFER) != 0) 2220 stats->tx_defer++; 2221 if ((flags & AE_TXS_EXCDEFER) != 0) 2222 stats->tx_excdefer++; 2223 if ((flags & AE_TXS_SINGLECOL) != 0) 2224 stats->tx_singlecol++; 2225 if ((flags & AE_TXS_MULTICOL) != 0) 2226 stats->tx_multicol++; 2227 if ((flags & AE_TXS_LATECOL) != 0) 2228 stats->tx_latecol++; 2229 if ((flags & AE_TXS_ABORTCOL) != 0) 2230 stats->tx_abortcol++; 2231 if ((flags & AE_TXS_UNDERRUN) != 0) 2232 stats->tx_underrun++; 2233 } 2234 2235 static void 2236 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2237 { 2238 2239 if ((flags & AE_RXD_BCAST) != 0) 2240 stats->rx_bcast++; 2241 if ((flags & AE_RXD_MCAST) != 0) 2242 stats->rx_mcast++; 2243 if ((flags & AE_RXD_PAUSE) != 0) 2244 stats->rx_pause++; 2245 if ((flags & AE_RXD_CTRL) != 0) 2246 stats->rx_ctrl++; 2247 if ((flags & AE_RXD_CRCERR) != 0) 2248 stats->rx_crcerr++; 2249 if ((flags & AE_RXD_CODEERR) != 0) 2250 stats->rx_codeerr++; 2251 if ((flags & AE_RXD_RUNT) != 0) 2252 stats->rx_runt++; 2253 if ((flags & AE_RXD_FRAG) != 0) 2254 stats->rx_frag++; 2255 if ((flags & AE_RXD_TRUNC) != 0) 2256 stats->rx_trunc++; 2257 if ((flags & AE_RXD_ALIGN) != 0) 2258 stats->rx_align++; 2259 } 2260