1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 72 #include "miibus_if.h" 73 74 #include "if_aereg.h" 75 #include "if_aevar.h" 76 77 /* 78 * Devices supported by this driver. 79 */ 80 static struct ae_dev { 81 uint16_t vendorid; 82 uint16_t deviceid; 83 const char *name; 84 } ae_devs[] = { 85 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 86 "Attansic Technology Corp, L2 FastEthernet" }, 87 }; 88 #define AE_DEVS_COUNT nitems(ae_devs) 89 90 static struct resource_spec ae_res_spec_mem[] = { 91 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 92 { -1, 0, 0 } 93 }; 94 static struct resource_spec ae_res_spec_irq[] = { 95 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 96 { -1, 0, 0 } 97 }; 98 static struct resource_spec ae_res_spec_msi[] = { 99 { SYS_RES_IRQ, 1, RF_ACTIVE }, 100 { -1, 0, 0 } 101 }; 102 103 static int ae_probe(device_t dev); 104 static int ae_attach(device_t dev); 105 static void ae_pcie_init(ae_softc_t *sc); 106 static void ae_phy_reset(ae_softc_t *sc); 107 static void ae_phy_init(ae_softc_t *sc); 108 static int ae_reset(ae_softc_t *sc); 109 static void ae_init(void *arg); 110 static int ae_init_locked(ae_softc_t *sc); 111 static int ae_detach(device_t dev); 112 static int ae_miibus_readreg(device_t dev, int phy, int reg); 113 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 114 static void ae_miibus_statchg(device_t dev); 115 static void ae_mediastatus(if_t ifp, struct ifmediareq *ifmr); 116 static int ae_mediachange(if_t ifp); 117 static void ae_retrieve_address(ae_softc_t *sc); 118 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 119 int error); 120 static int ae_alloc_rings(ae_softc_t *sc); 121 static void ae_dma_free(ae_softc_t *sc); 122 static int ae_shutdown(device_t dev); 123 static int ae_suspend(device_t dev); 124 static void ae_powersave_disable(ae_softc_t *sc); 125 static void ae_powersave_enable(ae_softc_t *sc); 126 static int ae_resume(device_t dev); 127 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 128 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 129 static void ae_start(if_t ifp); 130 static void ae_start_locked(if_t ifp); 131 static void ae_link_task(void *arg, int pending); 132 static void ae_stop_rxmac(ae_softc_t *sc); 133 static void ae_stop_txmac(ae_softc_t *sc); 134 static void ae_mac_config(ae_softc_t *sc); 135 static int ae_intr(void *arg); 136 static void ae_int_task(void *arg, int pending); 137 static void ae_tx_intr(ae_softc_t *sc); 138 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 139 static void ae_rx_intr(ae_softc_t *sc); 140 static void ae_watchdog(ae_softc_t *sc); 141 static void ae_tick(void *arg); 142 static void ae_rxfilter(ae_softc_t *sc); 143 static void ae_rxvlan(ae_softc_t *sc); 144 static int ae_ioctl(if_t ifp, u_long cmd, caddr_t data); 145 static void ae_stop(ae_softc_t *sc); 146 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 147 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 148 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 149 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 150 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 151 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 152 static void ae_init_tunables(ae_softc_t *sc); 153 154 static device_method_t ae_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, ae_probe), 157 DEVMETHOD(device_attach, ae_attach), 158 DEVMETHOD(device_detach, ae_detach), 159 DEVMETHOD(device_shutdown, ae_shutdown), 160 DEVMETHOD(device_suspend, ae_suspend), 161 DEVMETHOD(device_resume, ae_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 165 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 166 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 167 { NULL, NULL } 168 }; 169 static driver_t ae_driver = { 170 "ae", 171 ae_methods, 172 sizeof(ae_softc_t) 173 }; 174 175 DRIVER_MODULE(ae, pci, ae_driver, 0, 0); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 177 nitems(ae_devs)); 178 DRIVER_MODULE(miibus, ae, miibus_driver, 0, 0); 179 MODULE_DEPEND(ae, pci, 1, 1, 1); 180 MODULE_DEPEND(ae, ether, 1, 1, 1); 181 MODULE_DEPEND(ae, miibus, 1, 1, 1); 182 183 /* 184 * Tunables. 185 */ 186 static int msi_disable = 0; 187 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 188 189 #define AE_READ_4(sc, reg) \ 190 bus_read_4((sc)->mem[0], (reg)) 191 #define AE_READ_2(sc, reg) \ 192 bus_read_2((sc)->mem[0], (reg)) 193 #define AE_READ_1(sc, reg) \ 194 bus_read_1((sc)->mem[0], (reg)) 195 #define AE_WRITE_4(sc, reg, val) \ 196 bus_write_4((sc)->mem[0], (reg), (val)) 197 #define AE_WRITE_2(sc, reg, val) \ 198 bus_write_2((sc)->mem[0], (reg), (val)) 199 #define AE_WRITE_1(sc, reg, val) \ 200 bus_write_1((sc)->mem[0], (reg), (val)) 201 #define AE_PHY_READ(sc, reg) \ 202 ae_miibus_readreg(sc->dev, 0, reg) 203 #define AE_PHY_WRITE(sc, reg, val) \ 204 ae_miibus_writereg(sc->dev, 0, reg, val) 205 #define AE_CHECK_EADDR_VALID(eaddr) \ 206 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 207 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 208 #define AE_RXD_VLAN(vtag) \ 209 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 210 #define AE_TXD_VLAN(vtag) \ 211 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 212 213 static int 214 ae_probe(device_t dev) 215 { 216 uint16_t deviceid, vendorid; 217 int i; 218 219 vendorid = pci_get_vendor(dev); 220 deviceid = pci_get_device(dev); 221 222 /* 223 * Search through the list of supported devs for matching one. 224 */ 225 for (i = 0; i < AE_DEVS_COUNT; i++) { 226 if (vendorid == ae_devs[i].vendorid && 227 deviceid == ae_devs[i].deviceid) { 228 device_set_desc(dev, ae_devs[i].name); 229 return (BUS_PROBE_DEFAULT); 230 } 231 } 232 return (ENXIO); 233 } 234 235 static int 236 ae_attach(device_t dev) 237 { 238 ae_softc_t *sc; 239 if_t ifp; 240 uint8_t chiprev; 241 uint32_t pcirev; 242 int nmsi, pmc; 243 int error; 244 245 sc = device_get_softc(dev); /* Automatically allocated and zeroed 246 on attach. */ 247 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 248 sc->dev = dev; 249 250 /* 251 * Initialize mutexes and tasks. 252 */ 253 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 254 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 255 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 256 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 257 258 pci_enable_busmaster(dev); /* Enable bus mastering. */ 259 260 sc->spec_mem = ae_res_spec_mem; 261 262 /* 263 * Allocate memory-mapped registers. 264 */ 265 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 266 if (error != 0) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 sc->spec_mem = NULL; 269 goto fail; 270 } 271 272 /* 273 * Retrieve PCI and chip revisions. 274 */ 275 pcirev = pci_get_revid(dev); 276 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 277 AE_MASTER_REVNUM_MASK; 278 if (bootverbose) { 279 device_printf(dev, "pci device revision: %#04x\n", pcirev); 280 device_printf(dev, "chip id: %#02x\n", chiprev); 281 } 282 nmsi = pci_msi_count(dev); 283 if (bootverbose) 284 device_printf(dev, "MSI count: %d.\n", nmsi); 285 286 /* 287 * Allocate interrupt resources. 288 */ 289 if (msi_disable == 0 && nmsi == 1) { 290 error = pci_alloc_msi(dev, &nmsi); 291 if (error == 0) { 292 device_printf(dev, "Using MSI messages.\n"); 293 sc->spec_irq = ae_res_spec_msi; 294 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 295 if (error != 0) { 296 device_printf(dev, "MSI allocation failed.\n"); 297 sc->spec_irq = NULL; 298 pci_release_msi(dev); 299 } else { 300 sc->flags |= AE_FLAG_MSI; 301 } 302 } 303 } 304 if (sc->spec_irq == NULL) { 305 sc->spec_irq = ae_res_spec_irq; 306 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 307 if (error != 0) { 308 device_printf(dev, "could not allocate IRQ resources.\n"); 309 sc->spec_irq = NULL; 310 goto fail; 311 } 312 } 313 314 ae_init_tunables(sc); 315 316 ae_phy_reset(sc); /* Reset PHY. */ 317 error = ae_reset(sc); /* Reset the controller itself. */ 318 if (error != 0) 319 goto fail; 320 321 ae_pcie_init(sc); 322 323 ae_retrieve_address(sc); /* Load MAC address. */ 324 325 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 326 if (error != 0) 327 goto fail; 328 329 ifp = sc->ifp = if_alloc(IFT_ETHER); 330 if (ifp == NULL) { 331 device_printf(dev, "could not allocate ifnet structure.\n"); 332 error = ENXIO; 333 goto fail; 334 } 335 336 if_setsoftc(ifp, sc); 337 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 338 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 339 if_setioctlfn(ifp, ae_ioctl); 340 if_setstartfn(ifp, ae_start); 341 if_setinitfn(ifp, ae_init); 342 if_setcapabilities(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING); 343 if_sethwassist(ifp, 0); 344 if_setsendqlen(ifp, ifqmaxlen); 345 if_setsendqready(ifp); 346 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 347 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 348 sc->flags |= AE_FLAG_PMG; 349 } 350 if_setcapenable(ifp, if_getcapabilities(ifp)); 351 352 /* 353 * Configure and attach MII bus. 354 */ 355 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 356 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 357 MII_OFFSET_ANY, 0); 358 if (error != 0) { 359 device_printf(dev, "attaching PHYs failed\n"); 360 goto fail; 361 } 362 363 ether_ifattach(ifp, sc->eaddr); 364 /* Tell the upper layer(s) we support long frames. */ 365 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 366 367 /* 368 * Create and run all helper tasks. 369 */ 370 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 371 taskqueue_thread_enqueue, &sc->tq); 372 if (sc->tq == NULL) { 373 device_printf(dev, "could not create taskqueue.\n"); 374 ether_ifdetach(ifp); 375 error = ENXIO; 376 goto fail; 377 } 378 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 379 device_get_nameunit(sc->dev)); 380 381 /* 382 * Configure interrupt handlers. 383 */ 384 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 385 ae_intr, NULL, sc, &sc->intrhand); 386 if (error != 0) { 387 device_printf(dev, "could not set up interrupt handler.\n"); 388 taskqueue_free(sc->tq); 389 sc->tq = NULL; 390 ether_ifdetach(ifp); 391 goto fail; 392 } 393 394 fail: 395 if (error != 0) 396 ae_detach(dev); 397 398 return (error); 399 } 400 401 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 402 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 403 404 static void 405 ae_init_tunables(ae_softc_t *sc) 406 { 407 struct sysctl_ctx_list *ctx; 408 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 409 struct ae_stats *ae_stats; 410 411 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 412 ae_stats = &sc->stats; 413 414 ctx = device_get_sysctl_ctx(sc->dev); 415 root = device_get_sysctl_tree(sc->dev); 416 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 417 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ae statistics"); 418 419 /* 420 * Receiver statistcics. 421 */ 422 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 423 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 425 "broadcast frames", &ae_stats->rx_bcast); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 427 "multicast frames", &ae_stats->rx_mcast); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 429 "PAUSE frames", &ae_stats->rx_pause); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 431 "control frames", &ae_stats->rx_ctrl); 432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 433 "frames with CRC errors", &ae_stats->rx_crcerr); 434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 435 "frames with invalid opcode", &ae_stats->rx_codeerr); 436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 437 "runt frames", &ae_stats->rx_runt); 438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 439 "fragmented frames", &ae_stats->rx_frag); 440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 441 "frames with alignment errors", &ae_stats->rx_align); 442 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 443 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 444 445 /* 446 * Receiver statistcics. 447 */ 448 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 449 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 451 "broadcast frames", &ae_stats->tx_bcast); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 453 "multicast frames", &ae_stats->tx_mcast); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 455 "PAUSE frames", &ae_stats->tx_pause); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 457 "control frames", &ae_stats->tx_ctrl); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 459 "deferrals occuried", &ae_stats->tx_defer); 460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 461 "excessive deferrals occuried", &ae_stats->tx_excdefer); 462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 463 "single collisions occuried", &ae_stats->tx_singlecol); 464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 465 "multiple collisions occuried", &ae_stats->tx_multicol); 466 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 467 "late collisions occuried", &ae_stats->tx_latecol); 468 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 469 "transmit aborts due collisions", &ae_stats->tx_abortcol); 470 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 471 "Tx FIFO underruns", &ae_stats->tx_underrun); 472 } 473 474 static void 475 ae_pcie_init(ae_softc_t *sc) 476 { 477 478 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 479 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 480 } 481 482 static void 483 ae_phy_reset(ae_softc_t *sc) 484 { 485 486 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 487 DELAY(1000); /* XXX: pause(9) ? */ 488 } 489 490 static int 491 ae_reset(ae_softc_t *sc) 492 { 493 int i; 494 495 /* 496 * Issue a soft reset. 497 */ 498 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 499 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 500 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 501 502 /* 503 * Wait for reset to complete. 504 */ 505 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 506 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 507 break; 508 DELAY(10); 509 } 510 if (i == AE_RESET_TIMEOUT) { 511 device_printf(sc->dev, "reset timeout.\n"); 512 return (ENXIO); 513 } 514 515 /* 516 * Wait for everything to enter idle state. 517 */ 518 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 519 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 520 break; 521 DELAY(100); 522 } 523 if (i == AE_IDLE_TIMEOUT) { 524 device_printf(sc->dev, "could not enter idle state.\n"); 525 return (ENXIO); 526 } 527 return (0); 528 } 529 530 static void 531 ae_init(void *arg) 532 { 533 ae_softc_t *sc; 534 535 sc = (ae_softc_t *)arg; 536 AE_LOCK(sc); 537 ae_init_locked(sc); 538 AE_UNLOCK(sc); 539 } 540 541 static void 542 ae_phy_init(ae_softc_t *sc) 543 { 544 545 /* 546 * Enable link status change interrupt. 547 * XXX magic numbers. 548 */ 549 #ifdef notyet 550 AE_PHY_WRITE(sc, 18, 0xc00); 551 #endif 552 } 553 554 static int 555 ae_init_locked(ae_softc_t *sc) 556 { 557 if_t ifp; 558 struct mii_data *mii; 559 uint8_t eaddr[ETHER_ADDR_LEN]; 560 uint32_t val; 561 bus_addr_t addr; 562 563 AE_LOCK_ASSERT(sc); 564 565 ifp = sc->ifp; 566 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 567 return (0); 568 mii = device_get_softc(sc->miibus); 569 570 ae_stop(sc); 571 ae_reset(sc); 572 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 573 ae_phy_init(sc); 574 ae_powersave_disable(sc); 575 576 /* 577 * Clear and disable interrupts. 578 */ 579 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 580 581 /* 582 * Set the MAC address. 583 */ 584 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 585 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 586 AE_WRITE_4(sc, AE_EADDR0_REG, val); 587 val = eaddr[0] << 8 | eaddr[1]; 588 AE_WRITE_4(sc, AE_EADDR1_REG, val); 589 590 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 591 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 592 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 593 /* 594 * Set ring buffers base addresses. 595 */ 596 addr = sc->dma_rxd_busaddr; 597 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 598 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 599 addr = sc->dma_txd_busaddr; 600 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 601 addr = sc->dma_txs_busaddr; 602 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 603 604 /* 605 * Configure ring buffers sizes. 606 */ 607 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 608 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 609 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 610 611 /* 612 * Configure interframe gap parameters. 613 */ 614 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 615 AE_IFG_TXIPG_MASK) | 616 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 617 AE_IFG_RXIPG_MASK) | 618 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 619 AE_IFG_IPGR1_MASK) | 620 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 621 AE_IFG_IPGR2_MASK); 622 AE_WRITE_4(sc, AE_IFG_REG, val); 623 624 /* 625 * Configure half-duplex operation. 626 */ 627 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 628 AE_HDPX_LCOL_MASK) | 629 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 630 AE_HDPX_RETRY_MASK) | 631 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 632 AE_HDPX_ABEBT_MASK) | 633 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 634 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 635 AE_WRITE_4(sc, AE_HDPX_REG, val); 636 637 /* 638 * Configure interrupt moderate timer. 639 */ 640 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 641 val = AE_READ_4(sc, AE_MASTER_REG); 642 val |= AE_MASTER_IMT_EN; 643 AE_WRITE_4(sc, AE_MASTER_REG, val); 644 645 /* 646 * Configure interrupt clearing timer. 647 */ 648 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 649 650 /* 651 * Configure MTU. 652 */ 653 val = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 654 ETHER_CRC_LEN; 655 AE_WRITE_2(sc, AE_MTU_REG, val); 656 657 /* 658 * Configure cut-through threshold. 659 */ 660 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 661 662 /* 663 * Configure flow control. 664 */ 665 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 666 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 667 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 668 (AE_RXD_COUNT_DEFAULT / 12)); 669 670 /* 671 * Init mailboxes. 672 */ 673 sc->txd_cur = sc->rxd_cur = 0; 674 sc->txs_ack = sc->txd_ack = 0; 675 sc->rxd_cur = 0; 676 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 677 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 678 679 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 680 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 681 682 /* 683 * Enable DMA. 684 */ 685 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 686 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 687 688 /* 689 * Check if everything is OK. 690 */ 691 val = AE_READ_4(sc, AE_ISR_REG); 692 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 693 device_printf(sc->dev, "Initialization failed.\n"); 694 return (ENXIO); 695 } 696 697 /* 698 * Clear interrupt status. 699 */ 700 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 701 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 702 703 /* 704 * Enable interrupts. 705 */ 706 val = AE_READ_4(sc, AE_MASTER_REG); 707 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 708 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 709 710 /* 711 * Disable WOL. 712 */ 713 AE_WRITE_4(sc, AE_WOL_REG, 0); 714 715 /* 716 * Configure MAC. 717 */ 718 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 719 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 720 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 721 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 722 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 723 AE_MAC_PREAMBLE_MASK); 724 AE_WRITE_4(sc, AE_MAC_REG, val); 725 726 /* 727 * Configure Rx MAC. 728 */ 729 ae_rxfilter(sc); 730 ae_rxvlan(sc); 731 732 /* 733 * Enable Tx/Rx. 734 */ 735 val = AE_READ_4(sc, AE_MAC_REG); 736 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 737 738 sc->flags &= ~AE_FLAG_LINK; 739 mii_mediachg(mii); /* Switch to the current media. */ 740 741 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 742 743 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 744 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 745 746 #ifdef AE_DEBUG 747 device_printf(sc->dev, "Initialization complete.\n"); 748 #endif 749 750 return (0); 751 } 752 753 static int 754 ae_detach(device_t dev) 755 { 756 struct ae_softc *sc; 757 if_t ifp; 758 759 sc = device_get_softc(dev); 760 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 761 ifp = sc->ifp; 762 if (device_is_attached(dev)) { 763 AE_LOCK(sc); 764 sc->flags |= AE_FLAG_DETACH; 765 ae_stop(sc); 766 AE_UNLOCK(sc); 767 callout_drain(&sc->tick_ch); 768 taskqueue_drain(sc->tq, &sc->int_task); 769 taskqueue_drain(taskqueue_swi, &sc->link_task); 770 ether_ifdetach(ifp); 771 } 772 if (sc->tq != NULL) { 773 taskqueue_drain(sc->tq, &sc->int_task); 774 taskqueue_free(sc->tq); 775 sc->tq = NULL; 776 } 777 if (sc->miibus != NULL) { 778 device_delete_child(dev, sc->miibus); 779 sc->miibus = NULL; 780 } 781 bus_generic_detach(sc->dev); 782 ae_dma_free(sc); 783 if (sc->intrhand != NULL) { 784 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 785 sc->intrhand = NULL; 786 } 787 if (ifp != NULL) { 788 if_free(ifp); 789 sc->ifp = NULL; 790 } 791 if (sc->spec_irq != NULL) 792 bus_release_resources(dev, sc->spec_irq, sc->irq); 793 if (sc->spec_mem != NULL) 794 bus_release_resources(dev, sc->spec_mem, sc->mem); 795 if ((sc->flags & AE_FLAG_MSI) != 0) 796 pci_release_msi(dev); 797 mtx_destroy(&sc->mtx); 798 799 return (0); 800 } 801 802 static int 803 ae_miibus_readreg(device_t dev, int phy, int reg) 804 { 805 ae_softc_t *sc; 806 uint32_t val; 807 int i; 808 809 sc = device_get_softc(dev); 810 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 811 812 /* 813 * Locking is done in upper layers. 814 */ 815 816 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 817 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 818 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 819 AE_WRITE_4(sc, AE_MDIO_REG, val); 820 821 /* 822 * Wait for operation to complete. 823 */ 824 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 825 DELAY(2); 826 val = AE_READ_4(sc, AE_MDIO_REG); 827 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 828 break; 829 } 830 if (i == AE_MDIO_TIMEOUT) { 831 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 832 return (0); 833 } 834 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 835 } 836 837 static int 838 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 839 { 840 ae_softc_t *sc; 841 uint32_t aereg; 842 int i; 843 844 sc = device_get_softc(dev); 845 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 846 847 /* 848 * Locking is done in upper layers. 849 */ 850 851 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 852 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 853 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 854 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 855 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 856 857 /* 858 * Wait for operation to complete. 859 */ 860 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 861 DELAY(2); 862 aereg = AE_READ_4(sc, AE_MDIO_REG); 863 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 864 break; 865 } 866 if (i == AE_MDIO_TIMEOUT) { 867 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 868 } 869 return (0); 870 } 871 872 static void 873 ae_miibus_statchg(device_t dev) 874 { 875 ae_softc_t *sc; 876 877 sc = device_get_softc(dev); 878 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 879 } 880 881 static void 882 ae_mediastatus(if_t ifp, struct ifmediareq *ifmr) 883 { 884 ae_softc_t *sc; 885 struct mii_data *mii; 886 887 sc = if_getsoftc(ifp); 888 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 889 890 AE_LOCK(sc); 891 mii = device_get_softc(sc->miibus); 892 mii_pollstat(mii); 893 ifmr->ifm_status = mii->mii_media_status; 894 ifmr->ifm_active = mii->mii_media_active; 895 AE_UNLOCK(sc); 896 } 897 898 static int 899 ae_mediachange(if_t ifp) 900 { 901 ae_softc_t *sc; 902 struct mii_data *mii; 903 struct mii_softc *mii_sc; 904 int error; 905 906 /* XXX: check IFF_UP ?? */ 907 sc = if_getsoftc(ifp); 908 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 909 AE_LOCK(sc); 910 mii = device_get_softc(sc->miibus); 911 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 912 PHY_RESET(mii_sc); 913 error = mii_mediachg(mii); 914 AE_UNLOCK(sc); 915 916 return (error); 917 } 918 919 static int 920 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 921 { 922 int error; 923 uint32_t val; 924 925 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 926 927 /* 928 * Not sure why, but Linux does this. 929 */ 930 val = AE_READ_4(sc, AE_SPICTL_REG); 931 if ((val & AE_SPICTL_VPD_EN) != 0) { 932 val &= ~AE_SPICTL_VPD_EN; 933 AE_WRITE_4(sc, AE_SPICTL_REG, val); 934 } 935 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 936 return (error); 937 } 938 939 static int 940 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 941 { 942 uint32_t val; 943 int i; 944 945 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 946 947 /* 948 * VPD registers start at offset 0x100. Read them. 949 */ 950 val = 0x100 + reg * 4; 951 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 952 AE_VPD_CAP_ADDR_MASK); 953 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 954 DELAY(2000); 955 val = AE_READ_4(sc, AE_VPD_CAP_REG); 956 if ((val & AE_VPD_CAP_DONE) != 0) 957 break; 958 } 959 if (i == AE_VPD_TIMEOUT) { 960 device_printf(sc->dev, "timeout reading VPD register %d.\n", 961 reg); 962 return (ETIMEDOUT); 963 } 964 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 965 return (0); 966 } 967 968 static int 969 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 970 { 971 uint32_t word, reg, val; 972 int error; 973 int found; 974 int vpdc; 975 int i; 976 977 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 978 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 979 980 /* 981 * Check for EEPROM. 982 */ 983 error = ae_check_eeprom_present(sc, &vpdc); 984 if (error != 0) 985 return (error); 986 987 /* 988 * Read the VPD configuration space. 989 * Each register is prefixed with signature, 990 * so we can check if it is valid. 991 */ 992 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 993 error = ae_vpd_read_word(sc, i, &word); 994 if (error != 0) 995 break; 996 997 /* 998 * Check signature. 999 */ 1000 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1001 break; 1002 reg = word >> AE_VPD_REG_SHIFT; 1003 i++; /* Move to the next word. */ 1004 1005 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1006 continue; 1007 1008 error = ae_vpd_read_word(sc, i, &val); 1009 if (error != 0) 1010 break; 1011 if (reg == AE_EADDR0_REG) 1012 eaddr[0] = val; 1013 else 1014 eaddr[1] = val; 1015 found++; 1016 } 1017 1018 if (found < 2) 1019 return (ENOENT); 1020 1021 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1022 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1023 if (bootverbose) 1024 device_printf(sc->dev, 1025 "VPD ethernet address registers are invalid.\n"); 1026 return (EINVAL); 1027 } 1028 return (0); 1029 } 1030 1031 static int 1032 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1033 { 1034 1035 /* 1036 * BIOS is supposed to set this. 1037 */ 1038 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1039 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1040 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1041 1042 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1043 if (bootverbose) 1044 device_printf(sc->dev, 1045 "Ethernet address registers are invalid.\n"); 1046 return (EINVAL); 1047 } 1048 return (0); 1049 } 1050 1051 static void 1052 ae_retrieve_address(ae_softc_t *sc) 1053 { 1054 uint32_t eaddr[2] = {0, 0}; 1055 int error; 1056 1057 /* 1058 *Check for EEPROM. 1059 */ 1060 error = ae_get_vpd_eaddr(sc, eaddr); 1061 if (error != 0) 1062 error = ae_get_reg_eaddr(sc, eaddr); 1063 if (error != 0) { 1064 if (bootverbose) 1065 device_printf(sc->dev, 1066 "Generating random ethernet address.\n"); 1067 eaddr[0] = arc4random(); 1068 1069 /* 1070 * Set OUI to ASUSTek COMPUTER INC. 1071 */ 1072 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1073 sc->eaddr[1] = 0x1f; 1074 sc->eaddr[2] = 0xc6; 1075 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1076 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1077 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1078 } else { 1079 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1080 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1081 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1082 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1083 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1084 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1085 } 1086 } 1087 1088 static void 1089 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1090 { 1091 bus_addr_t *addr = arg; 1092 1093 if (error != 0) 1094 return; 1095 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1096 nsegs)); 1097 *addr = segs[0].ds_addr; 1098 } 1099 1100 static int 1101 ae_alloc_rings(ae_softc_t *sc) 1102 { 1103 bus_addr_t busaddr; 1104 int error; 1105 1106 /* 1107 * Create parent DMA tag. 1108 */ 1109 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1110 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1111 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1112 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1113 &sc->dma_parent_tag); 1114 if (error != 0) { 1115 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1116 return (error); 1117 } 1118 1119 /* 1120 * Create DMA tag for TxD. 1121 */ 1122 error = bus_dma_tag_create(sc->dma_parent_tag, 1123 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1124 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1125 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1126 &sc->dma_txd_tag); 1127 if (error != 0) { 1128 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1129 return (error); 1130 } 1131 1132 /* 1133 * Create DMA tag for TxS. 1134 */ 1135 error = bus_dma_tag_create(sc->dma_parent_tag, 1136 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1137 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1138 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1139 &sc->dma_txs_tag); 1140 if (error != 0) { 1141 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1142 return (error); 1143 } 1144 1145 /* 1146 * Create DMA tag for RxD. 1147 */ 1148 error = bus_dma_tag_create(sc->dma_parent_tag, 1149 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1150 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1151 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1152 &sc->dma_rxd_tag); 1153 if (error != 0) { 1154 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1155 return (error); 1156 } 1157 1158 /* 1159 * Allocate TxD DMA memory. 1160 */ 1161 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1162 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1163 &sc->dma_txd_map); 1164 if (error != 0) { 1165 device_printf(sc->dev, 1166 "could not allocate DMA memory for TxD ring.\n"); 1167 return (error); 1168 } 1169 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1170 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1171 if (error != 0 || busaddr == 0) { 1172 device_printf(sc->dev, 1173 "could not load DMA map for TxD ring.\n"); 1174 return (error); 1175 } 1176 sc->dma_txd_busaddr = busaddr; 1177 1178 /* 1179 * Allocate TxS DMA memory. 1180 */ 1181 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1182 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1183 &sc->dma_txs_map); 1184 if (error != 0) { 1185 device_printf(sc->dev, 1186 "could not allocate DMA memory for TxS ring.\n"); 1187 return (error); 1188 } 1189 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1190 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1191 if (error != 0 || busaddr == 0) { 1192 device_printf(sc->dev, 1193 "could not load DMA map for TxS ring.\n"); 1194 return (error); 1195 } 1196 sc->dma_txs_busaddr = busaddr; 1197 1198 /* 1199 * Allocate RxD DMA memory. 1200 */ 1201 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1202 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1203 &sc->dma_rxd_map); 1204 if (error != 0) { 1205 device_printf(sc->dev, 1206 "could not allocate DMA memory for RxD ring.\n"); 1207 return (error); 1208 } 1209 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1210 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1211 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1212 if (error != 0 || busaddr == 0) { 1213 device_printf(sc->dev, 1214 "could not load DMA map for RxD ring.\n"); 1215 return (error); 1216 } 1217 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1218 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1219 1220 return (0); 1221 } 1222 1223 static void 1224 ae_dma_free(ae_softc_t *sc) 1225 { 1226 1227 if (sc->dma_txd_tag != NULL) { 1228 if (sc->dma_txd_busaddr != 0) 1229 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1230 if (sc->txd_base != NULL) 1231 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1232 sc->dma_txd_map); 1233 bus_dma_tag_destroy(sc->dma_txd_tag); 1234 sc->dma_txd_tag = NULL; 1235 sc->txd_base = NULL; 1236 sc->dma_txd_busaddr = 0; 1237 } 1238 if (sc->dma_txs_tag != NULL) { 1239 if (sc->dma_txs_busaddr != 0) 1240 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1241 if (sc->txs_base != NULL) 1242 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1243 sc->dma_txs_map); 1244 bus_dma_tag_destroy(sc->dma_txs_tag); 1245 sc->dma_txs_tag = NULL; 1246 sc->txs_base = NULL; 1247 sc->dma_txs_busaddr = 0; 1248 } 1249 if (sc->dma_rxd_tag != NULL) { 1250 if (sc->dma_rxd_busaddr != 0) 1251 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1252 if (sc->rxd_base_dma != NULL) 1253 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1254 sc->dma_rxd_map); 1255 bus_dma_tag_destroy(sc->dma_rxd_tag); 1256 sc->dma_rxd_tag = NULL; 1257 sc->rxd_base_dma = NULL; 1258 sc->dma_rxd_busaddr = 0; 1259 } 1260 if (sc->dma_parent_tag != NULL) { 1261 bus_dma_tag_destroy(sc->dma_parent_tag); 1262 sc->dma_parent_tag = NULL; 1263 } 1264 } 1265 1266 static int 1267 ae_shutdown(device_t dev) 1268 { 1269 ae_softc_t *sc; 1270 int error; 1271 1272 sc = device_get_softc(dev); 1273 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1274 1275 error = ae_suspend(dev); 1276 AE_LOCK(sc); 1277 ae_powersave_enable(sc); 1278 AE_UNLOCK(sc); 1279 return (error); 1280 } 1281 1282 static void 1283 ae_powersave_disable(ae_softc_t *sc) 1284 { 1285 uint32_t val; 1286 1287 AE_LOCK_ASSERT(sc); 1288 1289 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1290 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1291 if (val & AE_PHY_DBG_POWERSAVE) { 1292 val &= ~AE_PHY_DBG_POWERSAVE; 1293 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1294 DELAY(1000); 1295 } 1296 } 1297 1298 static void 1299 ae_powersave_enable(ae_softc_t *sc) 1300 { 1301 uint32_t val; 1302 1303 AE_LOCK_ASSERT(sc); 1304 1305 /* 1306 * XXX magic numbers. 1307 */ 1308 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1309 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1310 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1312 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1313 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1314 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1315 } 1316 1317 static void 1318 ae_pm_init(ae_softc_t *sc) 1319 { 1320 if_t ifp; 1321 uint32_t val; 1322 uint16_t pmstat; 1323 struct mii_data *mii; 1324 int pmc; 1325 1326 AE_LOCK_ASSERT(sc); 1327 1328 ifp = sc->ifp; 1329 if ((sc->flags & AE_FLAG_PMG) == 0) { 1330 /* Disable WOL entirely. */ 1331 AE_WRITE_4(sc, AE_WOL_REG, 0); 1332 return; 1333 } 1334 1335 /* 1336 * Configure WOL if enabled. 1337 */ 1338 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1339 mii = device_get_softc(sc->miibus); 1340 mii_pollstat(mii); 1341 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1342 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1343 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1344 AE_WOL_MAGIC_PME); 1345 1346 /* 1347 * Configure MAC. 1348 */ 1349 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1350 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1351 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1352 AE_HALFBUF_MASK) | \ 1353 ((AE_MAC_PREAMBLE_DEFAULT << \ 1354 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1355 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1356 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1357 IFM_FDX) != 0) 1358 val |= AE_MAC_FULL_DUPLEX; 1359 AE_WRITE_4(sc, AE_MAC_REG, val); 1360 1361 } else { /* No link. */ 1362 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1363 AE_WOL_LNKCHG_PME); 1364 AE_WRITE_4(sc, AE_MAC_REG, 0); 1365 } 1366 } else { 1367 ae_powersave_enable(sc); 1368 } 1369 1370 /* 1371 * PCIE hacks. Magic numbers. 1372 */ 1373 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1374 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1375 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1376 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1377 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1378 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1379 1380 /* 1381 * Configure PME. 1382 */ 1383 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1384 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1385 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1386 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1387 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1388 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1389 } 1390 } 1391 1392 static int 1393 ae_suspend(device_t dev) 1394 { 1395 ae_softc_t *sc; 1396 1397 sc = device_get_softc(dev); 1398 1399 AE_LOCK(sc); 1400 ae_stop(sc); 1401 ae_pm_init(sc); 1402 AE_UNLOCK(sc); 1403 1404 return (0); 1405 } 1406 1407 static int 1408 ae_resume(device_t dev) 1409 { 1410 ae_softc_t *sc; 1411 1412 sc = device_get_softc(dev); 1413 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1414 1415 AE_LOCK(sc); 1416 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1417 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 1418 ae_init_locked(sc); 1419 AE_UNLOCK(sc); 1420 1421 return (0); 1422 } 1423 1424 static unsigned int 1425 ae_tx_avail_size(ae_softc_t *sc) 1426 { 1427 unsigned int avail; 1428 1429 if (sc->txd_cur >= sc->txd_ack) 1430 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1431 else 1432 avail = sc->txd_ack - sc->txd_cur; 1433 1434 return (avail); 1435 } 1436 1437 static int 1438 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1439 { 1440 struct mbuf *m0; 1441 ae_txd_t *hdr; 1442 unsigned int to_end; 1443 uint16_t len; 1444 1445 AE_LOCK_ASSERT(sc); 1446 1447 m0 = *m_head; 1448 len = m0->m_pkthdr.len; 1449 1450 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1451 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1452 #ifdef AE_DEBUG 1453 if_printf(sc->ifp, "No free Tx available.\n"); 1454 #endif 1455 return ENOBUFS; 1456 } 1457 1458 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1459 bzero(hdr, sizeof(*hdr)); 1460 /* Skip header size. */ 1461 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1462 /* Space available to the end of the ring */ 1463 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1464 if (to_end >= len) { 1465 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1466 } else { 1467 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1468 sc->txd_cur)); 1469 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1470 } 1471 1472 /* 1473 * Set TxD flags and parameters. 1474 */ 1475 if ((m0->m_flags & M_VLANTAG) != 0) { 1476 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1477 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1478 } else { 1479 hdr->len = htole16(len); 1480 } 1481 1482 /* 1483 * Set current TxD position and round up to a 4-byte boundary. 1484 */ 1485 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1486 if (sc->txd_cur == sc->txd_ack) 1487 sc->flags &= ~AE_FLAG_TXAVAIL; 1488 #ifdef AE_DEBUG 1489 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1490 #endif 1491 1492 /* 1493 * Update TxS position and check if there are empty TxS available. 1494 */ 1495 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1496 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1497 if (sc->txs_cur == sc->txs_ack) 1498 sc->flags &= ~AE_FLAG_TXAVAIL; 1499 1500 /* 1501 * Synchronize DMA memory. 1502 */ 1503 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1504 BUS_DMASYNC_PREWRITE); 1505 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1506 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1507 1508 return (0); 1509 } 1510 1511 static void 1512 ae_start(if_t ifp) 1513 { 1514 ae_softc_t *sc; 1515 1516 sc = if_getsoftc(ifp); 1517 AE_LOCK(sc); 1518 ae_start_locked(ifp); 1519 AE_UNLOCK(sc); 1520 } 1521 1522 static void 1523 ae_start_locked(if_t ifp) 1524 { 1525 ae_softc_t *sc; 1526 unsigned int count; 1527 struct mbuf *m0; 1528 int error; 1529 1530 sc = if_getsoftc(ifp); 1531 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1532 AE_LOCK_ASSERT(sc); 1533 1534 #ifdef AE_DEBUG 1535 if_printf(ifp, "Start called.\n"); 1536 #endif 1537 1538 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1539 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1540 return; 1541 1542 count = 0; 1543 while (!if_sendq_empty(ifp)) { 1544 m0 = if_dequeue(ifp); 1545 if (m0 == NULL) 1546 break; /* Nothing to do. */ 1547 1548 error = ae_encap(sc, &m0); 1549 if (error != 0) { 1550 if (m0 != NULL) { 1551 if_sendq_prepend(ifp, m0); 1552 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1553 #ifdef AE_DEBUG 1554 if_printf(ifp, "Setting OACTIVE.\n"); 1555 #endif 1556 } 1557 break; 1558 } 1559 count++; 1560 sc->tx_inproc++; 1561 1562 /* Bounce a copy of the frame to BPF. */ 1563 ETHER_BPF_MTAP(ifp, m0); 1564 1565 m_freem(m0); 1566 } 1567 1568 if (count > 0) { /* Something was dequeued. */ 1569 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1570 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1571 #ifdef AE_DEBUG 1572 if_printf(ifp, "%d packets dequeued.\n", count); 1573 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1574 #endif 1575 } 1576 } 1577 1578 static void 1579 ae_link_task(void *arg, int pending) 1580 { 1581 ae_softc_t *sc; 1582 struct mii_data *mii; 1583 if_t ifp; 1584 uint32_t val; 1585 1586 sc = (ae_softc_t *)arg; 1587 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1588 AE_LOCK(sc); 1589 1590 ifp = sc->ifp; 1591 mii = device_get_softc(sc->miibus); 1592 if (mii == NULL || ifp == NULL || 1593 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1594 AE_UNLOCK(sc); /* XXX: could happen? */ 1595 return; 1596 } 1597 1598 sc->flags &= ~AE_FLAG_LINK; 1599 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1600 (IFM_AVALID | IFM_ACTIVE)) { 1601 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1602 case IFM_10_T: 1603 case IFM_100_TX: 1604 sc->flags |= AE_FLAG_LINK; 1605 break; 1606 default: 1607 break; 1608 } 1609 } 1610 1611 /* 1612 * Stop Rx/Tx MACs. 1613 */ 1614 ae_stop_rxmac(sc); 1615 ae_stop_txmac(sc); 1616 1617 if ((sc->flags & AE_FLAG_LINK) != 0) { 1618 ae_mac_config(sc); 1619 1620 /* 1621 * Restart DMA engines. 1622 */ 1623 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1624 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1625 1626 /* 1627 * Enable Rx and Tx MACs. 1628 */ 1629 val = AE_READ_4(sc, AE_MAC_REG); 1630 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1631 AE_WRITE_4(sc, AE_MAC_REG, val); 1632 } 1633 AE_UNLOCK(sc); 1634 } 1635 1636 static void 1637 ae_stop_rxmac(ae_softc_t *sc) 1638 { 1639 uint32_t val; 1640 int i; 1641 1642 AE_LOCK_ASSERT(sc); 1643 1644 /* 1645 * Stop Rx MAC engine. 1646 */ 1647 val = AE_READ_4(sc, AE_MAC_REG); 1648 if ((val & AE_MAC_RX_EN) != 0) { 1649 val &= ~AE_MAC_RX_EN; 1650 AE_WRITE_4(sc, AE_MAC_REG, val); 1651 } 1652 1653 /* 1654 * Stop Rx DMA engine. 1655 */ 1656 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1657 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1658 1659 /* 1660 * Wait for IDLE state. 1661 */ 1662 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1663 val = AE_READ_4(sc, AE_IDLE_REG); 1664 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1665 break; 1666 DELAY(100); 1667 } 1668 if (i == AE_IDLE_TIMEOUT) 1669 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1670 } 1671 1672 static void 1673 ae_stop_txmac(ae_softc_t *sc) 1674 { 1675 uint32_t val; 1676 int i; 1677 1678 AE_LOCK_ASSERT(sc); 1679 1680 /* 1681 * Stop Tx MAC engine. 1682 */ 1683 val = AE_READ_4(sc, AE_MAC_REG); 1684 if ((val & AE_MAC_TX_EN) != 0) { 1685 val &= ~AE_MAC_TX_EN; 1686 AE_WRITE_4(sc, AE_MAC_REG, val); 1687 } 1688 1689 /* 1690 * Stop Tx DMA engine. 1691 */ 1692 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1693 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1694 1695 /* 1696 * Wait for IDLE state. 1697 */ 1698 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1699 val = AE_READ_4(sc, AE_IDLE_REG); 1700 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1701 break; 1702 DELAY(100); 1703 } 1704 if (i == AE_IDLE_TIMEOUT) 1705 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1706 } 1707 1708 static void 1709 ae_mac_config(ae_softc_t *sc) 1710 { 1711 struct mii_data *mii; 1712 uint32_t val; 1713 1714 AE_LOCK_ASSERT(sc); 1715 1716 mii = device_get_softc(sc->miibus); 1717 val = AE_READ_4(sc, AE_MAC_REG); 1718 val &= ~AE_MAC_FULL_DUPLEX; 1719 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1720 1721 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1722 val |= AE_MAC_FULL_DUPLEX; 1723 1724 AE_WRITE_4(sc, AE_MAC_REG, val); 1725 } 1726 1727 static int 1728 ae_intr(void *arg) 1729 { 1730 ae_softc_t *sc; 1731 uint32_t val; 1732 1733 sc = (ae_softc_t *)arg; 1734 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1735 1736 val = AE_READ_4(sc, AE_ISR_REG); 1737 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1738 return (FILTER_STRAY); 1739 1740 /* Disable interrupts. */ 1741 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1742 1743 /* Schedule interrupt processing. */ 1744 taskqueue_enqueue(sc->tq, &sc->int_task); 1745 1746 return (FILTER_HANDLED); 1747 } 1748 1749 static void 1750 ae_int_task(void *arg, int pending) 1751 { 1752 ae_softc_t *sc; 1753 if_t ifp; 1754 uint32_t val; 1755 1756 sc = (ae_softc_t *)arg; 1757 1758 AE_LOCK(sc); 1759 1760 ifp = sc->ifp; 1761 1762 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1763 if (val == 0) { 1764 AE_UNLOCK(sc); 1765 return; 1766 } 1767 1768 /* 1769 * Clear interrupts and disable them. 1770 */ 1771 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1772 1773 #ifdef AE_DEBUG 1774 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1775 #endif 1776 1777 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1778 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1779 AE_ISR_PHY_LINKDOWN)) != 0) { 1780 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1781 ae_init_locked(sc); 1782 AE_UNLOCK(sc); 1783 return; 1784 } 1785 if ((val & AE_ISR_TX_EVENT) != 0) 1786 ae_tx_intr(sc); 1787 if ((val & AE_ISR_RX_EVENT) != 0) 1788 ae_rx_intr(sc); 1789 /* 1790 * Re-enable interrupts. 1791 */ 1792 AE_WRITE_4(sc, AE_ISR_REG, 0); 1793 1794 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1795 if (!if_sendq_empty(ifp)) 1796 ae_start_locked(ifp); 1797 } 1798 } 1799 1800 AE_UNLOCK(sc); 1801 } 1802 1803 static void 1804 ae_tx_intr(ae_softc_t *sc) 1805 { 1806 if_t ifp; 1807 ae_txd_t *txd; 1808 ae_txs_t *txs; 1809 uint16_t flags; 1810 1811 AE_LOCK_ASSERT(sc); 1812 1813 ifp = sc->ifp; 1814 1815 #ifdef AE_DEBUG 1816 if_printf(ifp, "Tx interrupt occuried.\n"); 1817 #endif 1818 1819 /* 1820 * Syncronize DMA buffers. 1821 */ 1822 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1823 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1824 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1826 1827 for (;;) { 1828 txs = sc->txs_base + sc->txs_ack; 1829 flags = le16toh(txs->flags); 1830 if ((flags & AE_TXS_UPDATE) == 0) 1831 break; 1832 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1833 /* Update stats. */ 1834 ae_update_stats_tx(flags, &sc->stats); 1835 1836 /* 1837 * Update TxS position. 1838 */ 1839 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1840 sc->flags |= AE_FLAG_TXAVAIL; 1841 1842 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1843 if (txs->len != txd->len) 1844 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1845 le16toh(txs->len), le16toh(txd->len)); 1846 1847 /* 1848 * Move txd ack and align on 4-byte boundary. 1849 */ 1850 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1851 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1852 1853 if ((flags & AE_TXS_SUCCESS) != 0) 1854 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1855 else 1856 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1857 1858 sc->tx_inproc--; 1859 } 1860 1861 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1862 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1863 if (sc->tx_inproc < 0) { 1864 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1865 sc->tx_inproc = 0; 1866 } 1867 1868 if (sc->tx_inproc == 0) 1869 sc->wd_timer = 0; /* Unarm watchdog. */ 1870 1871 /* 1872 * Syncronize DMA buffers. 1873 */ 1874 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1875 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1876 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878 } 1879 1880 static void 1881 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1882 { 1883 if_t ifp; 1884 struct mbuf *m; 1885 unsigned int size; 1886 uint16_t flags; 1887 1888 AE_LOCK_ASSERT(sc); 1889 1890 ifp = sc->ifp; 1891 flags = le16toh(rxd->flags); 1892 1893 #ifdef AE_DEBUG 1894 if_printf(ifp, "Rx interrupt occuried.\n"); 1895 #endif 1896 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1897 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1898 if_printf(ifp, "Runt frame received."); 1899 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1900 return; 1901 } 1902 1903 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1904 if (m == NULL) { 1905 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1906 return; 1907 } 1908 1909 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1910 (flags & AE_RXD_HAS_VLAN) != 0) { 1911 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1912 m->m_flags |= M_VLANTAG; 1913 } 1914 1915 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1916 /* 1917 * Pass it through. 1918 */ 1919 AE_UNLOCK(sc); 1920 if_input(ifp, m); 1921 AE_LOCK(sc); 1922 } 1923 1924 static void 1925 ae_rx_intr(ae_softc_t *sc) 1926 { 1927 ae_rxd_t *rxd; 1928 if_t ifp; 1929 uint16_t flags; 1930 int count; 1931 1932 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1933 1934 AE_LOCK_ASSERT(sc); 1935 1936 ifp = sc->ifp; 1937 1938 /* 1939 * Syncronize DMA buffers. 1940 */ 1941 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1942 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1943 1944 for (count = 0;; count++) { 1945 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1946 flags = le16toh(rxd->flags); 1947 if ((flags & AE_RXD_UPDATE) == 0) 1948 break; 1949 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1950 /* Update stats. */ 1951 ae_update_stats_rx(flags, &sc->stats); 1952 1953 /* 1954 * Update position index. 1955 */ 1956 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1957 1958 if ((flags & AE_RXD_SUCCESS) != 0) 1959 ae_rxeof(sc, rxd); 1960 else 1961 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1962 } 1963 1964 if (count > 0) { 1965 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1967 /* 1968 * Update Rx index. 1969 */ 1970 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1971 } 1972 } 1973 1974 static void 1975 ae_watchdog(ae_softc_t *sc) 1976 { 1977 if_t ifp; 1978 1979 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1980 AE_LOCK_ASSERT(sc); 1981 ifp = sc->ifp; 1982 1983 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1984 return; /* Noting to do. */ 1985 1986 if ((sc->flags & AE_FLAG_LINK) == 0) 1987 if_printf(ifp, "watchdog timeout (missed link).\n"); 1988 else 1989 if_printf(ifp, "watchdog timeout - resetting.\n"); 1990 1991 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1992 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1993 ae_init_locked(sc); 1994 if (!if_sendq_empty(ifp)) 1995 ae_start_locked(ifp); 1996 } 1997 1998 static void 1999 ae_tick(void *arg) 2000 { 2001 ae_softc_t *sc; 2002 struct mii_data *mii; 2003 2004 sc = (ae_softc_t *)arg; 2005 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2006 AE_LOCK_ASSERT(sc); 2007 2008 mii = device_get_softc(sc->miibus); 2009 mii_tick(mii); 2010 ae_watchdog(sc); /* Watchdog check. */ 2011 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2012 } 2013 2014 static void 2015 ae_rxvlan(ae_softc_t *sc) 2016 { 2017 if_t ifp; 2018 uint32_t val; 2019 2020 AE_LOCK_ASSERT(sc); 2021 ifp = sc->ifp; 2022 val = AE_READ_4(sc, AE_MAC_REG); 2023 val &= ~AE_MAC_RMVLAN_EN; 2024 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2025 val |= AE_MAC_RMVLAN_EN; 2026 AE_WRITE_4(sc, AE_MAC_REG, val); 2027 } 2028 2029 static u_int 2030 ae_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2031 { 2032 uint32_t crc, *mchash = arg; 2033 2034 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2035 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2036 2037 return (1); 2038 } 2039 2040 static void 2041 ae_rxfilter(ae_softc_t *sc) 2042 { 2043 if_t ifp; 2044 uint32_t mchash[2]; 2045 uint32_t rxcfg; 2046 2047 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2048 2049 AE_LOCK_ASSERT(sc); 2050 2051 ifp = sc->ifp; 2052 2053 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2054 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2055 2056 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2057 rxcfg |= AE_MAC_BCAST_EN; 2058 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2059 rxcfg |= AE_MAC_PROMISC_EN; 2060 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2061 rxcfg |= AE_MAC_MCAST_EN; 2062 2063 /* 2064 * Wipe old settings. 2065 */ 2066 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2067 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2068 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2069 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2070 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2071 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2072 return; 2073 } 2074 2075 /* 2076 * Load multicast tables. 2077 */ 2078 bzero(mchash, sizeof(mchash)); 2079 if_foreach_llmaddr(ifp, ae_hash_maddr, &mchash); 2080 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2081 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2082 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2083 } 2084 2085 static int 2086 ae_ioctl(if_t ifp, u_long cmd, caddr_t data) 2087 { 2088 struct ae_softc *sc; 2089 struct ifreq *ifr; 2090 struct mii_data *mii; 2091 int error, mask; 2092 2093 sc = if_getsoftc(ifp); 2094 ifr = (struct ifreq *)data; 2095 error = 0; 2096 2097 switch (cmd) { 2098 case SIOCSIFMTU: 2099 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2100 error = EINVAL; 2101 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2102 AE_LOCK(sc); 2103 if_setmtu(ifp, ifr->ifr_mtu); 2104 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2105 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2106 ae_init_locked(sc); 2107 } 2108 AE_UNLOCK(sc); 2109 } 2110 break; 2111 case SIOCSIFFLAGS: 2112 AE_LOCK(sc); 2113 if ((if_getflags(ifp) & IFF_UP) != 0) { 2114 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2115 if (((if_getflags(ifp) ^ sc->if_flags) 2116 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2117 ae_rxfilter(sc); 2118 } else { 2119 if ((sc->flags & AE_FLAG_DETACH) == 0) 2120 ae_init_locked(sc); 2121 } 2122 } else { 2123 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2124 ae_stop(sc); 2125 } 2126 sc->if_flags = if_getflags(ifp); 2127 AE_UNLOCK(sc); 2128 break; 2129 case SIOCADDMULTI: 2130 case SIOCDELMULTI: 2131 AE_LOCK(sc); 2132 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2133 ae_rxfilter(sc); 2134 AE_UNLOCK(sc); 2135 break; 2136 case SIOCSIFMEDIA: 2137 case SIOCGIFMEDIA: 2138 mii = device_get_softc(sc->miibus); 2139 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2140 break; 2141 case SIOCSIFCAP: 2142 AE_LOCK(sc); 2143 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2144 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2145 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2146 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2147 ae_rxvlan(sc); 2148 } 2149 VLAN_CAPABILITIES(ifp); 2150 AE_UNLOCK(sc); 2151 break; 2152 default: 2153 error = ether_ioctl(ifp, cmd, data); 2154 break; 2155 } 2156 return (error); 2157 } 2158 2159 static void 2160 ae_stop(ae_softc_t *sc) 2161 { 2162 if_t ifp; 2163 int i; 2164 2165 AE_LOCK_ASSERT(sc); 2166 2167 ifp = sc->ifp; 2168 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2169 sc->flags &= ~AE_FLAG_LINK; 2170 sc->wd_timer = 0; /* Cancel watchdog. */ 2171 callout_stop(&sc->tick_ch); 2172 2173 /* 2174 * Clear and disable interrupts. 2175 */ 2176 AE_WRITE_4(sc, AE_IMR_REG, 0); 2177 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2178 2179 /* 2180 * Stop Rx/Tx MACs. 2181 */ 2182 ae_stop_txmac(sc); 2183 ae_stop_rxmac(sc); 2184 2185 /* 2186 * Stop DMA engines. 2187 */ 2188 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2189 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2190 2191 /* 2192 * Wait for everything to enter idle state. 2193 */ 2194 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2195 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2196 break; 2197 DELAY(100); 2198 } 2199 if (i == AE_IDLE_TIMEOUT) 2200 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2201 } 2202 2203 static void 2204 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2205 { 2206 2207 if ((flags & AE_TXS_BCAST) != 0) 2208 stats->tx_bcast++; 2209 if ((flags & AE_TXS_MCAST) != 0) 2210 stats->tx_mcast++; 2211 if ((flags & AE_TXS_PAUSE) != 0) 2212 stats->tx_pause++; 2213 if ((flags & AE_TXS_CTRL) != 0) 2214 stats->tx_ctrl++; 2215 if ((flags & AE_TXS_DEFER) != 0) 2216 stats->tx_defer++; 2217 if ((flags & AE_TXS_EXCDEFER) != 0) 2218 stats->tx_excdefer++; 2219 if ((flags & AE_TXS_SINGLECOL) != 0) 2220 stats->tx_singlecol++; 2221 if ((flags & AE_TXS_MULTICOL) != 0) 2222 stats->tx_multicol++; 2223 if ((flags & AE_TXS_LATECOL) != 0) 2224 stats->tx_latecol++; 2225 if ((flags & AE_TXS_ABORTCOL) != 0) 2226 stats->tx_abortcol++; 2227 if ((flags & AE_TXS_UNDERRUN) != 0) 2228 stats->tx_underrun++; 2229 } 2230 2231 static void 2232 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2233 { 2234 2235 if ((flags & AE_RXD_BCAST) != 0) 2236 stats->rx_bcast++; 2237 if ((flags & AE_RXD_MCAST) != 0) 2238 stats->rx_mcast++; 2239 if ((flags & AE_RXD_PAUSE) != 0) 2240 stats->rx_pause++; 2241 if ((flags & AE_RXD_CTRL) != 0) 2242 stats->rx_ctrl++; 2243 if ((flags & AE_RXD_CRCERR) != 0) 2244 stats->rx_crcerr++; 2245 if ((flags & AE_RXD_CODEERR) != 0) 2246 stats->rx_codeerr++; 2247 if ((flags & AE_RXD_RUNT) != 0) 2248 stats->rx_runt++; 2249 if ((flags & AE_RXD_FRAG) != 0) 2250 stats->rx_frag++; 2251 if ((flags & AE_RXD_TRUNC) != 0) 2252 stats->rx_trunc++; 2253 if ((flags & AE_RXD_ALIGN) != 0) 2254 stats->rx_align++; 2255 } 2256