1 /*- 2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 26 * 27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 72 #include "miibus_if.h" 73 74 #include "if_aereg.h" 75 #include "if_aevar.h" 76 77 /* 78 * Devices supported by this driver. 79 */ 80 static struct ae_dev { 81 uint16_t vendorid; 82 uint16_t deviceid; 83 const char *name; 84 } ae_devs[] = { 85 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 86 "Attansic Technology Corp, L2 FastEthernet" }, 87 }; 88 #define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs)) 89 90 static struct resource_spec ae_res_spec_mem[] = { 91 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 92 { -1, 0, 0 } 93 }; 94 static struct resource_spec ae_res_spec_irq[] = { 95 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 96 { -1, 0, 0 } 97 }; 98 static struct resource_spec ae_res_spec_msi[] = { 99 { SYS_RES_IRQ, 1, RF_ACTIVE }, 100 { -1, 0, 0 } 101 }; 102 103 static int ae_probe(device_t dev); 104 static int ae_attach(device_t dev); 105 static void ae_pcie_init(ae_softc_t *sc); 106 static void ae_phy_reset(ae_softc_t *sc); 107 static void ae_phy_init(ae_softc_t *sc); 108 static int ae_reset(ae_softc_t *sc); 109 static void ae_init(void *arg); 110 static int ae_init_locked(ae_softc_t *sc); 111 static int ae_detach(device_t dev); 112 static int ae_miibus_readreg(device_t dev, int phy, int reg); 113 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 114 static void ae_miibus_statchg(device_t dev); 115 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 116 static int ae_mediachange(struct ifnet *ifp); 117 static void ae_retrieve_address(ae_softc_t *sc); 118 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 119 int error); 120 static int ae_alloc_rings(ae_softc_t *sc); 121 static void ae_dma_free(ae_softc_t *sc); 122 static int ae_shutdown(device_t dev); 123 static int ae_suspend(device_t dev); 124 static void ae_powersave_disable(ae_softc_t *sc); 125 static void ae_powersave_enable(ae_softc_t *sc); 126 static int ae_resume(device_t dev); 127 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 128 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 129 static void ae_start(struct ifnet *ifp); 130 static void ae_start_locked(struct ifnet *ifp); 131 static void ae_link_task(void *arg, int pending); 132 static void ae_stop_rxmac(ae_softc_t *sc); 133 static void ae_stop_txmac(ae_softc_t *sc); 134 static void ae_mac_config(ae_softc_t *sc); 135 static int ae_intr(void *arg); 136 static void ae_int_task(void *arg, int pending); 137 static void ae_tx_intr(ae_softc_t *sc); 138 static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 139 static void ae_rx_intr(ae_softc_t *sc); 140 static void ae_watchdog(ae_softc_t *sc); 141 static void ae_tick(void *arg); 142 static void ae_rxfilter(ae_softc_t *sc); 143 static void ae_rxvlan(ae_softc_t *sc); 144 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 145 static void ae_stop(ae_softc_t *sc); 146 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 147 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 148 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 149 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 150 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 151 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 152 static void ae_init_tunables(ae_softc_t *sc); 153 154 static device_method_t ae_methods[] = { 155 /* Device interface. */ 156 DEVMETHOD(device_probe, ae_probe), 157 DEVMETHOD(device_attach, ae_attach), 158 DEVMETHOD(device_detach, ae_detach), 159 DEVMETHOD(device_shutdown, ae_shutdown), 160 DEVMETHOD(device_suspend, ae_suspend), 161 DEVMETHOD(device_resume, ae_resume), 162 163 /* MII interface. */ 164 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 165 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 166 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 167 168 { NULL, NULL } 169 }; 170 static driver_t ae_driver = { 171 "ae", 172 ae_methods, 173 sizeof(ae_softc_t) 174 }; 175 static devclass_t ae_devclass; 176 177 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0); 178 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 179 MODULE_DEPEND(ae, pci, 1, 1, 1); 180 MODULE_DEPEND(ae, ether, 1, 1, 1); 181 MODULE_DEPEND(ae, miibus, 1, 1, 1); 182 183 /* 184 * Tunables. 185 */ 186 static int msi_disable = 0; 187 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 188 189 #define AE_READ_4(sc, reg) \ 190 bus_read_4((sc)->mem[0], (reg)) 191 #define AE_READ_2(sc, reg) \ 192 bus_read_2((sc)->mem[0], (reg)) 193 #define AE_READ_1(sc, reg) \ 194 bus_read_1((sc)->mem[0], (reg)) 195 #define AE_WRITE_4(sc, reg, val) \ 196 bus_write_4((sc)->mem[0], (reg), (val)) 197 #define AE_WRITE_2(sc, reg, val) \ 198 bus_write_2((sc)->mem[0], (reg), (val)) 199 #define AE_WRITE_1(sc, reg, val) \ 200 bus_write_1((sc)->mem[0], (reg), (val)) 201 #define AE_PHY_READ(sc, reg) \ 202 ae_miibus_readreg(sc->dev, 0, reg) 203 #define AE_PHY_WRITE(sc, reg, val) \ 204 ae_miibus_writereg(sc->dev, 0, reg, val) 205 #define AE_CHECK_EADDR_VALID(eaddr) \ 206 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 207 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 208 #define AE_RXD_VLAN(vtag) \ 209 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 210 #define AE_TXD_VLAN(vtag) \ 211 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 212 213 static int 214 ae_probe(device_t dev) 215 { 216 uint16_t deviceid, vendorid; 217 int i; 218 219 vendorid = pci_get_vendor(dev); 220 deviceid = pci_get_device(dev); 221 222 /* 223 * Search through the list of supported devs for matching one. 224 */ 225 for (i = 0; i < AE_DEVS_COUNT; i++) { 226 if (vendorid == ae_devs[i].vendorid && 227 deviceid == ae_devs[i].deviceid) { 228 device_set_desc(dev, ae_devs[i].name); 229 return (BUS_PROBE_DEFAULT); 230 } 231 } 232 return (ENXIO); 233 } 234 235 static int 236 ae_attach(device_t dev) 237 { 238 ae_softc_t *sc; 239 struct ifnet *ifp; 240 uint8_t chiprev; 241 uint32_t pcirev; 242 int nmsi, pmc; 243 int error; 244 245 sc = device_get_softc(dev); /* Automatically allocated and zeroed 246 on attach. */ 247 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 248 sc->dev = dev; 249 250 /* 251 * Initialize mutexes and tasks. 252 */ 253 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 254 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 255 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 256 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 257 258 pci_enable_busmaster(dev); /* Enable bus mastering. */ 259 260 sc->spec_mem = ae_res_spec_mem; 261 262 /* 263 * Allocate memory-mapped registers. 264 */ 265 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 266 if (error != 0) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 sc->spec_mem = NULL; 269 goto fail; 270 } 271 272 /* 273 * Retrieve PCI and chip revisions. 274 */ 275 pcirev = pci_get_revid(dev); 276 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 277 AE_MASTER_REVNUM_MASK; 278 if (bootverbose) { 279 device_printf(dev, "pci device revision: %#04x\n", pcirev); 280 device_printf(dev, "chip id: %#02x\n", chiprev); 281 } 282 nmsi = pci_msi_count(dev); 283 if (bootverbose) 284 device_printf(dev, "MSI count: %d.\n", nmsi); 285 286 /* 287 * Allocate interrupt resources. 288 */ 289 if (msi_disable == 0 && nmsi == 1) { 290 error = pci_alloc_msi(dev, &nmsi); 291 if (error == 0) { 292 device_printf(dev, "Using MSI messages.\n"); 293 sc->spec_irq = ae_res_spec_msi; 294 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 295 if (error != 0) { 296 device_printf(dev, "MSI allocation failed.\n"); 297 sc->spec_irq = NULL; 298 pci_release_msi(dev); 299 } else { 300 sc->flags |= AE_FLAG_MSI; 301 } 302 } 303 } 304 if (sc->spec_irq == NULL) { 305 sc->spec_irq = ae_res_spec_irq; 306 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 307 if (error != 0) { 308 device_printf(dev, "could not allocate IRQ resources.\n"); 309 sc->spec_irq = NULL; 310 goto fail; 311 } 312 } 313 314 ae_init_tunables(sc); 315 316 ae_phy_reset(sc); /* Reset PHY. */ 317 error = ae_reset(sc); /* Reset the controller itself. */ 318 if (error != 0) 319 goto fail; 320 321 ae_pcie_init(sc); 322 323 ae_retrieve_address(sc); /* Load MAC address. */ 324 325 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 326 if (error != 0) 327 goto fail; 328 329 ifp = sc->ifp = if_alloc(IFT_ETHER); 330 if (ifp == NULL) { 331 device_printf(dev, "could not allocate ifnet structure.\n"); 332 error = ENXIO; 333 goto fail; 334 } 335 336 ifp->if_softc = sc; 337 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 339 ifp->if_ioctl = ae_ioctl; 340 ifp->if_start = ae_start; 341 ifp->if_init = ae_init; 342 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 343 ifp->if_hwassist = 0; 344 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 345 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 346 IFQ_SET_READY(&ifp->if_snd); 347 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 348 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 349 sc->flags |= AE_FLAG_PMG; 350 } 351 ifp->if_capenable = ifp->if_capabilities; 352 353 /* 354 * Configure and attach MII bus. 355 */ 356 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 357 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 358 MII_OFFSET_ANY, 0); 359 if (error != 0) { 360 device_printf(dev, "attaching PHYs failed\n"); 361 goto fail; 362 } 363 364 ether_ifattach(ifp, sc->eaddr); 365 /* Tell the upper layer(s) we support long frames. */ 366 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 367 368 /* 369 * Create and run all helper tasks. 370 */ 371 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 372 taskqueue_thread_enqueue, &sc->tq); 373 if (sc->tq == NULL) { 374 device_printf(dev, "could not create taskqueue.\n"); 375 ether_ifdetach(ifp); 376 error = ENXIO; 377 goto fail; 378 } 379 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 380 device_get_nameunit(sc->dev)); 381 382 /* 383 * Configure interrupt handlers. 384 */ 385 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 386 ae_intr, NULL, sc, &sc->intrhand); 387 if (error != 0) { 388 device_printf(dev, "could not set up interrupt handler.\n"); 389 taskqueue_free(sc->tq); 390 sc->tq = NULL; 391 ether_ifdetach(ifp); 392 goto fail; 393 } 394 395 fail: 396 if (error != 0) 397 ae_detach(dev); 398 399 return (error); 400 } 401 402 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 403 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 404 405 static void 406 ae_init_tunables(ae_softc_t *sc) 407 { 408 struct sysctl_ctx_list *ctx; 409 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 410 struct ae_stats *ae_stats; 411 412 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 413 ae_stats = &sc->stats; 414 415 ctx = device_get_sysctl_ctx(sc->dev); 416 root = device_get_sysctl_tree(sc->dev); 417 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 418 CTLFLAG_RD, NULL, "ae statistics"); 419 420 /* 421 * Receiver statistcics. 422 */ 423 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 424 CTLFLAG_RD, NULL, "Rx MAC statistics"); 425 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 426 "broadcast frames", &ae_stats->rx_bcast); 427 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 428 "multicast frames", &ae_stats->rx_mcast); 429 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 430 "PAUSE frames", &ae_stats->rx_pause); 431 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 432 "control frames", &ae_stats->rx_ctrl); 433 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 434 "frames with CRC errors", &ae_stats->rx_crcerr); 435 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 436 "frames with invalid opcode", &ae_stats->rx_codeerr); 437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 438 "runt frames", &ae_stats->rx_runt); 439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 440 "fragmented frames", &ae_stats->rx_frag); 441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 442 "frames with alignment errors", &ae_stats->rx_align); 443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 444 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 445 446 /* 447 * Receiver statistcics. 448 */ 449 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 450 CTLFLAG_RD, NULL, "Tx MAC statistics"); 451 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 452 "broadcast frames", &ae_stats->tx_bcast); 453 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 454 "multicast frames", &ae_stats->tx_mcast); 455 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 456 "PAUSE frames", &ae_stats->tx_pause); 457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 458 "control frames", &ae_stats->tx_ctrl); 459 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 460 "deferrals occuried", &ae_stats->tx_defer); 461 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 462 "excessive deferrals occuried", &ae_stats->tx_excdefer); 463 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 464 "single collisions occuried", &ae_stats->tx_singlecol); 465 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 466 "multiple collisions occuried", &ae_stats->tx_multicol); 467 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 468 "late collisions occuried", &ae_stats->tx_latecol); 469 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 470 "transmit aborts due collisions", &ae_stats->tx_abortcol); 471 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 472 "Tx FIFO underruns", &ae_stats->tx_underrun); 473 } 474 475 static void 476 ae_pcie_init(ae_softc_t *sc) 477 { 478 479 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 480 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 481 } 482 483 static void 484 ae_phy_reset(ae_softc_t *sc) 485 { 486 487 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 488 DELAY(1000); /* XXX: pause(9) ? */ 489 } 490 491 static int 492 ae_reset(ae_softc_t *sc) 493 { 494 int i; 495 496 /* 497 * Issue a soft reset. 498 */ 499 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 500 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 501 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 502 503 /* 504 * Wait for reset to complete. 505 */ 506 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 507 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 508 break; 509 DELAY(10); 510 } 511 if (i == AE_RESET_TIMEOUT) { 512 device_printf(sc->dev, "reset timeout.\n"); 513 return (ENXIO); 514 } 515 516 /* 517 * Wait for everything to enter idle state. 518 */ 519 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 520 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 521 break; 522 DELAY(100); 523 } 524 if (i == AE_IDLE_TIMEOUT) { 525 device_printf(sc->dev, "could not enter idle state.\n"); 526 return (ENXIO); 527 } 528 return (0); 529 } 530 531 static void 532 ae_init(void *arg) 533 { 534 ae_softc_t *sc; 535 536 sc = (ae_softc_t *)arg; 537 AE_LOCK(sc); 538 ae_init_locked(sc); 539 AE_UNLOCK(sc); 540 } 541 542 static void 543 ae_phy_init(ae_softc_t *sc) 544 { 545 546 /* 547 * Enable link status change interrupt. 548 * XXX magic numbers. 549 */ 550 #ifdef notyet 551 AE_PHY_WRITE(sc, 18, 0xc00); 552 #endif 553 } 554 555 static int 556 ae_init_locked(ae_softc_t *sc) 557 { 558 struct ifnet *ifp; 559 struct mii_data *mii; 560 uint8_t eaddr[ETHER_ADDR_LEN]; 561 uint32_t val; 562 bus_addr_t addr; 563 564 AE_LOCK_ASSERT(sc); 565 566 ifp = sc->ifp; 567 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 568 return (0); 569 mii = device_get_softc(sc->miibus); 570 571 ae_stop(sc); 572 ae_reset(sc); 573 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 574 ae_phy_init(sc); 575 ae_powersave_disable(sc); 576 577 /* 578 * Clear and disable interrupts. 579 */ 580 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 581 582 /* 583 * Set the MAC address. 584 */ 585 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 586 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 587 AE_WRITE_4(sc, AE_EADDR0_REG, val); 588 val = eaddr[0] << 8 | eaddr[1]; 589 AE_WRITE_4(sc, AE_EADDR1_REG, val); 590 591 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 592 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 593 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 594 /* 595 * Set ring buffers base addresses. 596 */ 597 addr = sc->dma_rxd_busaddr; 598 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 599 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 600 addr = sc->dma_txd_busaddr; 601 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 602 addr = sc->dma_txs_busaddr; 603 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 604 605 /* 606 * Configure ring buffers sizes. 607 */ 608 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 609 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 610 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 611 612 /* 613 * Configure interframe gap parameters. 614 */ 615 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 616 AE_IFG_TXIPG_MASK) | 617 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 618 AE_IFG_RXIPG_MASK) | 619 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 620 AE_IFG_IPGR1_MASK) | 621 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 622 AE_IFG_IPGR2_MASK); 623 AE_WRITE_4(sc, AE_IFG_REG, val); 624 625 /* 626 * Configure half-duplex operation. 627 */ 628 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 629 AE_HDPX_LCOL_MASK) | 630 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 631 AE_HDPX_RETRY_MASK) | 632 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 633 AE_HDPX_ABEBT_MASK) | 634 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 635 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 636 AE_WRITE_4(sc, AE_HDPX_REG, val); 637 638 /* 639 * Configure interrupt moderate timer. 640 */ 641 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 642 val = AE_READ_4(sc, AE_MASTER_REG); 643 val |= AE_MASTER_IMT_EN; 644 AE_WRITE_4(sc, AE_MASTER_REG, val); 645 646 /* 647 * Configure interrupt clearing timer. 648 */ 649 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 650 651 /* 652 * Configure MTU. 653 */ 654 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 655 ETHER_CRC_LEN; 656 AE_WRITE_2(sc, AE_MTU_REG, val); 657 658 /* 659 * Configure cut-through threshold. 660 */ 661 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 662 663 /* 664 * Configure flow control. 665 */ 666 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 667 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 668 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 669 (AE_RXD_COUNT_DEFAULT / 12)); 670 671 /* 672 * Init mailboxes. 673 */ 674 sc->txd_cur = sc->rxd_cur = 0; 675 sc->txs_ack = sc->txd_ack = 0; 676 sc->rxd_cur = 0; 677 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 678 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 679 680 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 681 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 682 683 /* 684 * Enable DMA. 685 */ 686 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 687 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 688 689 /* 690 * Check if everything is OK. 691 */ 692 val = AE_READ_4(sc, AE_ISR_REG); 693 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 694 device_printf(sc->dev, "Initialization failed.\n"); 695 return (ENXIO); 696 } 697 698 /* 699 * Clear interrupt status. 700 */ 701 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 702 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 703 704 /* 705 * Enable interrupts. 706 */ 707 val = AE_READ_4(sc, AE_MASTER_REG); 708 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 709 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 710 711 /* 712 * Disable WOL. 713 */ 714 AE_WRITE_4(sc, AE_WOL_REG, 0); 715 716 /* 717 * Configure MAC. 718 */ 719 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 720 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 721 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 722 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 723 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 724 AE_MAC_PREAMBLE_MASK); 725 AE_WRITE_4(sc, AE_MAC_REG, val); 726 727 /* 728 * Configure Rx MAC. 729 */ 730 ae_rxfilter(sc); 731 ae_rxvlan(sc); 732 733 /* 734 * Enable Tx/Rx. 735 */ 736 val = AE_READ_4(sc, AE_MAC_REG); 737 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 738 739 sc->flags &= ~AE_FLAG_LINK; 740 mii_mediachg(mii); /* Switch to the current media. */ 741 742 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 743 744 ifp->if_drv_flags |= IFF_DRV_RUNNING; 745 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 746 747 #ifdef AE_DEBUG 748 device_printf(sc->dev, "Initialization complete.\n"); 749 #endif 750 751 return (0); 752 } 753 754 static int 755 ae_detach(device_t dev) 756 { 757 struct ae_softc *sc; 758 struct ifnet *ifp; 759 760 sc = device_get_softc(dev); 761 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 762 ifp = sc->ifp; 763 if (device_is_attached(dev)) { 764 AE_LOCK(sc); 765 sc->flags |= AE_FLAG_DETACH; 766 ae_stop(sc); 767 AE_UNLOCK(sc); 768 callout_drain(&sc->tick_ch); 769 taskqueue_drain(sc->tq, &sc->int_task); 770 taskqueue_drain(taskqueue_swi, &sc->link_task); 771 ether_ifdetach(ifp); 772 } 773 if (sc->tq != NULL) { 774 taskqueue_drain(sc->tq, &sc->int_task); 775 taskqueue_free(sc->tq); 776 sc->tq = NULL; 777 } 778 if (sc->miibus != NULL) { 779 device_delete_child(dev, sc->miibus); 780 sc->miibus = NULL; 781 } 782 bus_generic_detach(sc->dev); 783 ae_dma_free(sc); 784 if (sc->intrhand != NULL) { 785 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 786 sc->intrhand = NULL; 787 } 788 if (ifp != NULL) { 789 if_free(ifp); 790 sc->ifp = NULL; 791 } 792 if (sc->spec_irq != NULL) 793 bus_release_resources(dev, sc->spec_irq, sc->irq); 794 if (sc->spec_mem != NULL) 795 bus_release_resources(dev, sc->spec_mem, sc->mem); 796 if ((sc->flags & AE_FLAG_MSI) != 0) 797 pci_release_msi(dev); 798 mtx_destroy(&sc->mtx); 799 800 return (0); 801 } 802 803 static int 804 ae_miibus_readreg(device_t dev, int phy, int reg) 805 { 806 ae_softc_t *sc; 807 uint32_t val; 808 int i; 809 810 sc = device_get_softc(dev); 811 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 812 813 /* 814 * Locking is done in upper layers. 815 */ 816 817 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 818 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 819 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 820 AE_WRITE_4(sc, AE_MDIO_REG, val); 821 822 /* 823 * Wait for operation to complete. 824 */ 825 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 826 DELAY(2); 827 val = AE_READ_4(sc, AE_MDIO_REG); 828 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 829 break; 830 } 831 if (i == AE_MDIO_TIMEOUT) { 832 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 833 return (0); 834 } 835 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 836 } 837 838 static int 839 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 840 { 841 ae_softc_t *sc; 842 uint32_t aereg; 843 int i; 844 845 sc = device_get_softc(dev); 846 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 847 848 /* 849 * Locking is done in upper layers. 850 */ 851 852 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 853 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 854 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 855 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 856 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 857 858 /* 859 * Wait for operation to complete. 860 */ 861 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 862 DELAY(2); 863 aereg = AE_READ_4(sc, AE_MDIO_REG); 864 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 865 break; 866 } 867 if (i == AE_MDIO_TIMEOUT) { 868 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 869 } 870 return (0); 871 } 872 873 static void 874 ae_miibus_statchg(device_t dev) 875 { 876 ae_softc_t *sc; 877 878 sc = device_get_softc(dev); 879 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 880 } 881 882 static void 883 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 884 { 885 ae_softc_t *sc; 886 struct mii_data *mii; 887 888 sc = ifp->if_softc; 889 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 890 891 AE_LOCK(sc); 892 mii = device_get_softc(sc->miibus); 893 mii_pollstat(mii); 894 ifmr->ifm_status = mii->mii_media_status; 895 ifmr->ifm_active = mii->mii_media_active; 896 AE_UNLOCK(sc); 897 } 898 899 static int 900 ae_mediachange(struct ifnet *ifp) 901 { 902 ae_softc_t *sc; 903 struct mii_data *mii; 904 struct mii_softc *mii_sc; 905 int error; 906 907 /* XXX: check IFF_UP ?? */ 908 sc = ifp->if_softc; 909 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 910 AE_LOCK(sc); 911 mii = device_get_softc(sc->miibus); 912 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 913 PHY_RESET(mii_sc); 914 error = mii_mediachg(mii); 915 AE_UNLOCK(sc); 916 917 return (error); 918 } 919 920 static int 921 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 922 { 923 int error; 924 uint32_t val; 925 926 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 927 928 /* 929 * Not sure why, but Linux does this. 930 */ 931 val = AE_READ_4(sc, AE_SPICTL_REG); 932 if ((val & AE_SPICTL_VPD_EN) != 0) { 933 val &= ~AE_SPICTL_VPD_EN; 934 AE_WRITE_4(sc, AE_SPICTL_REG, val); 935 } 936 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 937 return (error); 938 } 939 940 static int 941 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 942 { 943 uint32_t val; 944 int i; 945 946 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 947 948 /* 949 * VPD registers start at offset 0x100. Read them. 950 */ 951 val = 0x100 + reg * 4; 952 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 953 AE_VPD_CAP_ADDR_MASK); 954 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 955 DELAY(2000); 956 val = AE_READ_4(sc, AE_VPD_CAP_REG); 957 if ((val & AE_VPD_CAP_DONE) != 0) 958 break; 959 } 960 if (i == AE_VPD_TIMEOUT) { 961 device_printf(sc->dev, "timeout reading VPD register %d.\n", 962 reg); 963 return (ETIMEDOUT); 964 } 965 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 966 return (0); 967 } 968 969 static int 970 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 971 { 972 uint32_t word, reg, val; 973 int error; 974 int found; 975 int vpdc; 976 int i; 977 978 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 979 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 980 981 /* 982 * Check for EEPROM. 983 */ 984 error = ae_check_eeprom_present(sc, &vpdc); 985 if (error != 0) 986 return (error); 987 988 /* 989 * Read the VPD configuration space. 990 * Each register is prefixed with signature, 991 * so we can check if it is valid. 992 */ 993 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 994 error = ae_vpd_read_word(sc, i, &word); 995 if (error != 0) 996 break; 997 998 /* 999 * Check signature. 1000 */ 1001 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1002 break; 1003 reg = word >> AE_VPD_REG_SHIFT; 1004 i++; /* Move to the next word. */ 1005 1006 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1007 continue; 1008 1009 error = ae_vpd_read_word(sc, i, &val); 1010 if (error != 0) 1011 break; 1012 if (reg == AE_EADDR0_REG) 1013 eaddr[0] = val; 1014 else 1015 eaddr[1] = val; 1016 found++; 1017 } 1018 1019 if (found < 2) 1020 return (ENOENT); 1021 1022 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1023 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1024 if (bootverbose) 1025 device_printf(sc->dev, 1026 "VPD ethernet address registers are invalid.\n"); 1027 return (EINVAL); 1028 } 1029 return (0); 1030 } 1031 1032 static int 1033 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1034 { 1035 1036 /* 1037 * BIOS is supposed to set this. 1038 */ 1039 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1040 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1041 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1042 1043 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1044 if (bootverbose) 1045 device_printf(sc->dev, 1046 "Ethernet address registers are invalid.\n"); 1047 return (EINVAL); 1048 } 1049 return (0); 1050 } 1051 1052 static void 1053 ae_retrieve_address(ae_softc_t *sc) 1054 { 1055 uint32_t eaddr[2] = {0, 0}; 1056 int error; 1057 1058 /* 1059 *Check for EEPROM. 1060 */ 1061 error = ae_get_vpd_eaddr(sc, eaddr); 1062 if (error != 0) 1063 error = ae_get_reg_eaddr(sc, eaddr); 1064 if (error != 0) { 1065 if (bootverbose) 1066 device_printf(sc->dev, 1067 "Generating random ethernet address.\n"); 1068 eaddr[0] = arc4random(); 1069 1070 /* 1071 * Set OUI to ASUSTek COMPUTER INC. 1072 */ 1073 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1074 sc->eaddr[1] = 0x1f; 1075 sc->eaddr[2] = 0xc6; 1076 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1077 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1078 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1079 } else { 1080 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1081 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1082 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1083 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1084 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1085 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1086 } 1087 } 1088 1089 static void 1090 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1091 { 1092 bus_addr_t *addr = arg; 1093 1094 if (error != 0) 1095 return; 1096 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1097 nsegs)); 1098 *addr = segs[0].ds_addr; 1099 } 1100 1101 static int 1102 ae_alloc_rings(ae_softc_t *sc) 1103 { 1104 bus_addr_t busaddr; 1105 int error; 1106 1107 /* 1108 * Create parent DMA tag. 1109 */ 1110 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1111 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1112 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1113 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1114 &sc->dma_parent_tag); 1115 if (error != 0) { 1116 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1117 return (error); 1118 } 1119 1120 /* 1121 * Create DMA tag for TxD. 1122 */ 1123 error = bus_dma_tag_create(sc->dma_parent_tag, 1124 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1125 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1126 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1127 &sc->dma_txd_tag); 1128 if (error != 0) { 1129 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1130 return (error); 1131 } 1132 1133 /* 1134 * Create DMA tag for TxS. 1135 */ 1136 error = bus_dma_tag_create(sc->dma_parent_tag, 1137 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1138 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1139 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1140 &sc->dma_txs_tag); 1141 if (error != 0) { 1142 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1143 return (error); 1144 } 1145 1146 /* 1147 * Create DMA tag for RxD. 1148 */ 1149 error = bus_dma_tag_create(sc->dma_parent_tag, 1150 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1151 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1152 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1153 &sc->dma_rxd_tag); 1154 if (error != 0) { 1155 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1156 return (error); 1157 } 1158 1159 /* 1160 * Allocate TxD DMA memory. 1161 */ 1162 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1164 &sc->dma_txd_map); 1165 if (error != 0) { 1166 device_printf(sc->dev, 1167 "could not allocate DMA memory for TxD ring.\n"); 1168 return (error); 1169 } 1170 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1171 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1172 if (error != 0 || busaddr == 0) { 1173 device_printf(sc->dev, 1174 "could not load DMA map for TxD ring.\n"); 1175 return (error); 1176 } 1177 sc->dma_txd_busaddr = busaddr; 1178 1179 /* 1180 * Allocate TxS DMA memory. 1181 */ 1182 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1183 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1184 &sc->dma_txs_map); 1185 if (error != 0) { 1186 device_printf(sc->dev, 1187 "could not allocate DMA memory for TxS ring.\n"); 1188 return (error); 1189 } 1190 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1191 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1192 if (error != 0 || busaddr == 0) { 1193 device_printf(sc->dev, 1194 "could not load DMA map for TxS ring.\n"); 1195 return (error); 1196 } 1197 sc->dma_txs_busaddr = busaddr; 1198 1199 /* 1200 * Allocate RxD DMA memory. 1201 */ 1202 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1203 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1204 &sc->dma_rxd_map); 1205 if (error != 0) { 1206 device_printf(sc->dev, 1207 "could not allocate DMA memory for RxD ring.\n"); 1208 return (error); 1209 } 1210 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1211 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1212 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1213 if (error != 0 || busaddr == 0) { 1214 device_printf(sc->dev, 1215 "could not load DMA map for RxD ring.\n"); 1216 return (error); 1217 } 1218 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1219 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1220 1221 return (0); 1222 } 1223 1224 static void 1225 ae_dma_free(ae_softc_t *sc) 1226 { 1227 1228 if (sc->dma_txd_tag != NULL) { 1229 if (sc->dma_txd_map != NULL) { 1230 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1231 if (sc->txd_base != NULL) 1232 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1233 sc->dma_txd_map); 1234 1235 } 1236 bus_dma_tag_destroy(sc->dma_txd_tag); 1237 sc->dma_txd_map = NULL; 1238 sc->dma_txd_tag = NULL; 1239 sc->txd_base = NULL; 1240 } 1241 if (sc->dma_txs_tag != NULL) { 1242 if (sc->dma_txs_map != NULL) { 1243 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1244 if (sc->txs_base != NULL) 1245 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1246 sc->dma_txs_map); 1247 1248 } 1249 bus_dma_tag_destroy(sc->dma_txs_tag); 1250 sc->dma_txs_map = NULL; 1251 sc->dma_txs_tag = NULL; 1252 sc->txs_base = NULL; 1253 } 1254 if (sc->dma_rxd_tag != NULL) { 1255 if (sc->dma_rxd_map != NULL) { 1256 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1257 if (sc->rxd_base_dma != NULL) 1258 bus_dmamem_free(sc->dma_rxd_tag, 1259 sc->rxd_base_dma, sc->dma_rxd_map); 1260 1261 } 1262 bus_dma_tag_destroy(sc->dma_rxd_tag); 1263 sc->dma_rxd_map = NULL; 1264 sc->dma_rxd_tag = NULL; 1265 sc->rxd_base_dma = NULL; 1266 } 1267 if (sc->dma_parent_tag != NULL) { 1268 bus_dma_tag_destroy(sc->dma_parent_tag); 1269 sc->dma_parent_tag = NULL; 1270 } 1271 } 1272 1273 static int 1274 ae_shutdown(device_t dev) 1275 { 1276 ae_softc_t *sc; 1277 int error; 1278 1279 sc = device_get_softc(dev); 1280 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1281 1282 error = ae_suspend(dev); 1283 AE_LOCK(sc); 1284 ae_powersave_enable(sc); 1285 AE_UNLOCK(sc); 1286 return (error); 1287 } 1288 1289 static void 1290 ae_powersave_disable(ae_softc_t *sc) 1291 { 1292 uint32_t val; 1293 1294 AE_LOCK_ASSERT(sc); 1295 1296 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1297 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1298 if (val & AE_PHY_DBG_POWERSAVE) { 1299 val &= ~AE_PHY_DBG_POWERSAVE; 1300 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1301 DELAY(1000); 1302 } 1303 } 1304 1305 static void 1306 ae_powersave_enable(ae_softc_t *sc) 1307 { 1308 uint32_t val; 1309 1310 AE_LOCK_ASSERT(sc); 1311 1312 /* 1313 * XXX magic numbers. 1314 */ 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1316 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1317 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1318 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1319 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1320 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1321 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1322 } 1323 1324 static void 1325 ae_pm_init(ae_softc_t *sc) 1326 { 1327 struct ifnet *ifp; 1328 uint32_t val; 1329 uint16_t pmstat; 1330 struct mii_data *mii; 1331 int pmc; 1332 1333 AE_LOCK_ASSERT(sc); 1334 1335 ifp = sc->ifp; 1336 if ((sc->flags & AE_FLAG_PMG) == 0) { 1337 /* Disable WOL entirely. */ 1338 AE_WRITE_4(sc, AE_WOL_REG, 0); 1339 return; 1340 } 1341 1342 /* 1343 * Configure WOL if enabled. 1344 */ 1345 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1346 mii = device_get_softc(sc->miibus); 1347 mii_pollstat(mii); 1348 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1349 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1350 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1351 AE_WOL_MAGIC_PME); 1352 1353 /* 1354 * Configure MAC. 1355 */ 1356 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1357 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1358 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1359 AE_HALFBUF_MASK) | \ 1360 ((AE_MAC_PREAMBLE_DEFAULT << \ 1361 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1362 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1363 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1364 IFM_FDX) != 0) 1365 val |= AE_MAC_FULL_DUPLEX; 1366 AE_WRITE_4(sc, AE_MAC_REG, val); 1367 1368 } else { /* No link. */ 1369 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1370 AE_WOL_LNKCHG_PME); 1371 AE_WRITE_4(sc, AE_MAC_REG, 0); 1372 } 1373 } else { 1374 ae_powersave_enable(sc); 1375 } 1376 1377 /* 1378 * PCIE hacks. Magic numbers. 1379 */ 1380 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1381 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1382 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1383 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1384 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1385 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1386 1387 /* 1388 * Configure PME. 1389 */ 1390 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1391 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1392 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1393 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1394 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1395 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1396 } 1397 } 1398 1399 static int 1400 ae_suspend(device_t dev) 1401 { 1402 ae_softc_t *sc; 1403 1404 sc = device_get_softc(dev); 1405 1406 AE_LOCK(sc); 1407 ae_stop(sc); 1408 ae_pm_init(sc); 1409 AE_UNLOCK(sc); 1410 1411 return (0); 1412 } 1413 1414 static int 1415 ae_resume(device_t dev) 1416 { 1417 ae_softc_t *sc; 1418 1419 sc = device_get_softc(dev); 1420 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1421 1422 AE_LOCK(sc); 1423 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1424 if ((sc->ifp->if_flags & IFF_UP) != 0) 1425 ae_init_locked(sc); 1426 AE_UNLOCK(sc); 1427 1428 return (0); 1429 } 1430 1431 static unsigned int 1432 ae_tx_avail_size(ae_softc_t *sc) 1433 { 1434 unsigned int avail; 1435 1436 if (sc->txd_cur >= sc->txd_ack) 1437 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1438 else 1439 avail = sc->txd_ack - sc->txd_cur; 1440 1441 return (avail); 1442 } 1443 1444 static int 1445 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1446 { 1447 struct mbuf *m0; 1448 ae_txd_t *hdr; 1449 unsigned int to_end; 1450 uint16_t len; 1451 1452 AE_LOCK_ASSERT(sc); 1453 1454 m0 = *m_head; 1455 len = m0->m_pkthdr.len; 1456 1457 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1458 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1459 #ifdef AE_DEBUG 1460 if_printf(sc->ifp, "No free Tx available.\n"); 1461 #endif 1462 return ENOBUFS; 1463 } 1464 1465 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1466 bzero(hdr, sizeof(*hdr)); 1467 /* Skip header size. */ 1468 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1469 /* Space available to the end of the ring */ 1470 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1471 if (to_end >= len) { 1472 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1473 } else { 1474 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1475 sc->txd_cur)); 1476 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1477 } 1478 1479 /* 1480 * Set TxD flags and parameters. 1481 */ 1482 if ((m0->m_flags & M_VLANTAG) != 0) { 1483 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1484 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1485 } else { 1486 hdr->len = htole16(len); 1487 } 1488 1489 /* 1490 * Set current TxD position and round up to a 4-byte boundary. 1491 */ 1492 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1493 if (sc->txd_cur == sc->txd_ack) 1494 sc->flags &= ~AE_FLAG_TXAVAIL; 1495 #ifdef AE_DEBUG 1496 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1497 #endif 1498 1499 /* 1500 * Update TxS position and check if there are empty TxS available. 1501 */ 1502 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1503 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1504 if (sc->txs_cur == sc->txs_ack) 1505 sc->flags &= ~AE_FLAG_TXAVAIL; 1506 1507 /* 1508 * Synchronize DMA memory. 1509 */ 1510 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1511 BUS_DMASYNC_PREWRITE); 1512 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1513 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1514 1515 return (0); 1516 } 1517 1518 static void 1519 ae_start(struct ifnet *ifp) 1520 { 1521 ae_softc_t *sc; 1522 1523 sc = ifp->if_softc; 1524 AE_LOCK(sc); 1525 ae_start_locked(ifp); 1526 AE_UNLOCK(sc); 1527 } 1528 1529 static void 1530 ae_start_locked(struct ifnet *ifp) 1531 { 1532 ae_softc_t *sc; 1533 unsigned int count; 1534 struct mbuf *m0; 1535 int error; 1536 1537 sc = ifp->if_softc; 1538 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1539 AE_LOCK_ASSERT(sc); 1540 1541 #ifdef AE_DEBUG 1542 if_printf(ifp, "Start called.\n"); 1543 #endif 1544 1545 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1546 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1547 return; 1548 1549 count = 0; 1550 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1551 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1552 if (m0 == NULL) 1553 break; /* Nothing to do. */ 1554 1555 error = ae_encap(sc, &m0); 1556 if (error != 0) { 1557 if (m0 != NULL) { 1558 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1559 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1560 #ifdef AE_DEBUG 1561 if_printf(ifp, "Setting OACTIVE.\n"); 1562 #endif 1563 } 1564 break; 1565 } 1566 count++; 1567 sc->tx_inproc++; 1568 1569 /* Bounce a copy of the frame to BPF. */ 1570 ETHER_BPF_MTAP(ifp, m0); 1571 1572 m_freem(m0); 1573 } 1574 1575 if (count > 0) { /* Something was dequeued. */ 1576 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1577 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1578 #ifdef AE_DEBUG 1579 if_printf(ifp, "%d packets dequeued.\n", count); 1580 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1581 #endif 1582 } 1583 } 1584 1585 static void 1586 ae_link_task(void *arg, int pending) 1587 { 1588 ae_softc_t *sc; 1589 struct mii_data *mii; 1590 struct ifnet *ifp; 1591 uint32_t val; 1592 1593 sc = (ae_softc_t *)arg; 1594 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1595 AE_LOCK(sc); 1596 1597 ifp = sc->ifp; 1598 mii = device_get_softc(sc->miibus); 1599 if (mii == NULL || ifp == NULL || 1600 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1601 AE_UNLOCK(sc); /* XXX: could happen? */ 1602 return; 1603 } 1604 1605 sc->flags &= ~AE_FLAG_LINK; 1606 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1607 (IFM_AVALID | IFM_ACTIVE)) { 1608 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1609 case IFM_10_T: 1610 case IFM_100_TX: 1611 sc->flags |= AE_FLAG_LINK; 1612 break; 1613 default: 1614 break; 1615 } 1616 } 1617 1618 /* 1619 * Stop Rx/Tx MACs. 1620 */ 1621 ae_stop_rxmac(sc); 1622 ae_stop_txmac(sc); 1623 1624 if ((sc->flags & AE_FLAG_LINK) != 0) { 1625 ae_mac_config(sc); 1626 1627 /* 1628 * Restart DMA engines. 1629 */ 1630 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1631 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1632 1633 /* 1634 * Enable Rx and Tx MACs. 1635 */ 1636 val = AE_READ_4(sc, AE_MAC_REG); 1637 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1638 AE_WRITE_4(sc, AE_MAC_REG, val); 1639 } 1640 AE_UNLOCK(sc); 1641 } 1642 1643 static void 1644 ae_stop_rxmac(ae_softc_t *sc) 1645 { 1646 uint32_t val; 1647 int i; 1648 1649 AE_LOCK_ASSERT(sc); 1650 1651 /* 1652 * Stop Rx MAC engine. 1653 */ 1654 val = AE_READ_4(sc, AE_MAC_REG); 1655 if ((val & AE_MAC_RX_EN) != 0) { 1656 val &= ~AE_MAC_RX_EN; 1657 AE_WRITE_4(sc, AE_MAC_REG, val); 1658 } 1659 1660 /* 1661 * Stop Rx DMA engine. 1662 */ 1663 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1664 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1665 1666 /* 1667 * Wait for IDLE state. 1668 */ 1669 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1670 val = AE_READ_4(sc, AE_IDLE_REG); 1671 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1672 break; 1673 DELAY(100); 1674 } 1675 if (i == AE_IDLE_TIMEOUT) 1676 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1677 } 1678 1679 static void 1680 ae_stop_txmac(ae_softc_t *sc) 1681 { 1682 uint32_t val; 1683 int i; 1684 1685 AE_LOCK_ASSERT(sc); 1686 1687 /* 1688 * Stop Tx MAC engine. 1689 */ 1690 val = AE_READ_4(sc, AE_MAC_REG); 1691 if ((val & AE_MAC_TX_EN) != 0) { 1692 val &= ~AE_MAC_TX_EN; 1693 AE_WRITE_4(sc, AE_MAC_REG, val); 1694 } 1695 1696 /* 1697 * Stop Tx DMA engine. 1698 */ 1699 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1700 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1701 1702 /* 1703 * Wait for IDLE state. 1704 */ 1705 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 1706 val = AE_READ_4(sc, AE_IDLE_REG); 1707 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1708 break; 1709 DELAY(100); 1710 } 1711 if (i == AE_IDLE_TIMEOUT) 1712 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1713 } 1714 1715 static void 1716 ae_mac_config(ae_softc_t *sc) 1717 { 1718 struct mii_data *mii; 1719 uint32_t val; 1720 1721 AE_LOCK_ASSERT(sc); 1722 1723 mii = device_get_softc(sc->miibus); 1724 val = AE_READ_4(sc, AE_MAC_REG); 1725 val &= ~AE_MAC_FULL_DUPLEX; 1726 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1727 1728 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1729 val |= AE_MAC_FULL_DUPLEX; 1730 1731 AE_WRITE_4(sc, AE_MAC_REG, val); 1732 } 1733 1734 static int 1735 ae_intr(void *arg) 1736 { 1737 ae_softc_t *sc; 1738 uint32_t val; 1739 1740 sc = (ae_softc_t *)arg; 1741 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1742 1743 val = AE_READ_4(sc, AE_ISR_REG); 1744 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1745 return (FILTER_STRAY); 1746 1747 /* Disable interrupts. */ 1748 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1749 1750 /* Schedule interrupt processing. */ 1751 taskqueue_enqueue(sc->tq, &sc->int_task); 1752 1753 return (FILTER_HANDLED); 1754 } 1755 1756 static void 1757 ae_int_task(void *arg, int pending) 1758 { 1759 ae_softc_t *sc; 1760 struct ifnet *ifp; 1761 uint32_t val; 1762 1763 sc = (ae_softc_t *)arg; 1764 1765 AE_LOCK(sc); 1766 1767 ifp = sc->ifp; 1768 1769 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1770 if (val == 0) { 1771 AE_UNLOCK(sc); 1772 return; 1773 } 1774 1775 /* 1776 * Clear interrupts and disable them. 1777 */ 1778 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1779 1780 #ifdef AE_DEBUG 1781 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1782 #endif 1783 1784 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1785 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1786 AE_ISR_PHY_LINKDOWN)) != 0) { 1787 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1788 ae_init_locked(sc); 1789 AE_UNLOCK(sc); 1790 return; 1791 } 1792 if ((val & AE_ISR_TX_EVENT) != 0) 1793 ae_tx_intr(sc); 1794 if ((val & AE_ISR_RX_EVENT) != 0) 1795 ae_rx_intr(sc); 1796 /* 1797 * Re-enable interrupts. 1798 */ 1799 AE_WRITE_4(sc, AE_ISR_REG, 0); 1800 1801 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1803 ae_start_locked(ifp); 1804 } 1805 } 1806 1807 AE_UNLOCK(sc); 1808 } 1809 1810 static void 1811 ae_tx_intr(ae_softc_t *sc) 1812 { 1813 struct ifnet *ifp; 1814 ae_txd_t *txd; 1815 ae_txs_t *txs; 1816 uint16_t flags; 1817 1818 AE_LOCK_ASSERT(sc); 1819 1820 ifp = sc->ifp; 1821 1822 #ifdef AE_DEBUG 1823 if_printf(ifp, "Tx interrupt occuried.\n"); 1824 #endif 1825 1826 /* 1827 * Syncronize DMA buffers. 1828 */ 1829 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1830 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1831 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1832 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1833 1834 for (;;) { 1835 txs = sc->txs_base + sc->txs_ack; 1836 flags = le16toh(txs->flags); 1837 if ((flags & AE_TXS_UPDATE) == 0) 1838 break; 1839 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1840 /* Update stats. */ 1841 ae_update_stats_tx(flags, &sc->stats); 1842 1843 /* 1844 * Update TxS position. 1845 */ 1846 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1847 sc->flags |= AE_FLAG_TXAVAIL; 1848 1849 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1850 if (txs->len != txd->len) 1851 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1852 le16toh(txs->len), le16toh(txd->len)); 1853 1854 /* 1855 * Move txd ack and align on 4-byte boundary. 1856 */ 1857 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1858 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1859 1860 if ((flags & AE_TXS_SUCCESS) != 0) 1861 ifp->if_opackets++; 1862 else 1863 ifp->if_oerrors++; 1864 1865 sc->tx_inproc--; 1866 } 1867 1868 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1869 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1870 if (sc->tx_inproc < 0) { 1871 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1872 sc->tx_inproc = 0; 1873 } 1874 1875 if (sc->tx_inproc == 0) 1876 sc->wd_timer = 0; /* Unarm watchdog. */ 1877 1878 /* 1879 * Syncronize DMA buffers. 1880 */ 1881 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1883 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1884 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1885 } 1886 1887 static int 1888 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1889 { 1890 struct ifnet *ifp; 1891 struct mbuf *m; 1892 unsigned int size; 1893 uint16_t flags; 1894 1895 AE_LOCK_ASSERT(sc); 1896 1897 ifp = sc->ifp; 1898 flags = le16toh(rxd->flags); 1899 1900 #ifdef AE_DEBUG 1901 if_printf(ifp, "Rx interrupt occuried.\n"); 1902 #endif 1903 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1904 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1905 if_printf(ifp, "Runt frame received."); 1906 return (EIO); 1907 } 1908 1909 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1910 if (m == NULL) 1911 return (ENOBUFS); 1912 1913 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 1914 (flags & AE_RXD_HAS_VLAN) != 0) { 1915 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1916 m->m_flags |= M_VLANTAG; 1917 } 1918 1919 /* 1920 * Pass it through. 1921 */ 1922 AE_UNLOCK(sc); 1923 (*ifp->if_input)(ifp, m); 1924 AE_LOCK(sc); 1925 1926 return (0); 1927 } 1928 1929 static void 1930 ae_rx_intr(ae_softc_t *sc) 1931 { 1932 ae_rxd_t *rxd; 1933 struct ifnet *ifp; 1934 uint16_t flags; 1935 int count, error; 1936 1937 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1938 1939 AE_LOCK_ASSERT(sc); 1940 1941 ifp = sc->ifp; 1942 1943 /* 1944 * Syncronize DMA buffers. 1945 */ 1946 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1948 1949 for (count = 0;; count++) { 1950 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1951 flags = le16toh(rxd->flags); 1952 if ((flags & AE_RXD_UPDATE) == 0) 1953 break; 1954 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1955 /* Update stats. */ 1956 ae_update_stats_rx(flags, &sc->stats); 1957 1958 /* 1959 * Update position index. 1960 */ 1961 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1962 1963 if ((flags & AE_RXD_SUCCESS) == 0) { 1964 ifp->if_ierrors++; 1965 continue; 1966 } 1967 error = ae_rxeof(sc, rxd); 1968 if (error != 0) { 1969 ifp->if_ierrors++; 1970 continue; 1971 } else { 1972 ifp->if_ipackets++; 1973 } 1974 } 1975 1976 if (count > 0) { 1977 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1979 /* 1980 * Update Rx index. 1981 */ 1982 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1983 } 1984 } 1985 1986 static void 1987 ae_watchdog(ae_softc_t *sc) 1988 { 1989 struct ifnet *ifp; 1990 1991 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1992 AE_LOCK_ASSERT(sc); 1993 ifp = sc->ifp; 1994 1995 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1996 return; /* Noting to do. */ 1997 1998 if ((sc->flags & AE_FLAG_LINK) == 0) 1999 if_printf(ifp, "watchdog timeout (missed link).\n"); 2000 else 2001 if_printf(ifp, "watchdog timeout - resetting.\n"); 2002 2003 ifp->if_oerrors++; 2004 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2005 ae_init_locked(sc); 2006 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2007 ae_start_locked(ifp); 2008 } 2009 2010 static void 2011 ae_tick(void *arg) 2012 { 2013 ae_softc_t *sc; 2014 struct mii_data *mii; 2015 2016 sc = (ae_softc_t *)arg; 2017 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2018 AE_LOCK_ASSERT(sc); 2019 2020 mii = device_get_softc(sc->miibus); 2021 mii_tick(mii); 2022 ae_watchdog(sc); /* Watchdog check. */ 2023 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2024 } 2025 2026 static void 2027 ae_rxvlan(ae_softc_t *sc) 2028 { 2029 struct ifnet *ifp; 2030 uint32_t val; 2031 2032 AE_LOCK_ASSERT(sc); 2033 ifp = sc->ifp; 2034 val = AE_READ_4(sc, AE_MAC_REG); 2035 val &= ~AE_MAC_RMVLAN_EN; 2036 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2037 val |= AE_MAC_RMVLAN_EN; 2038 AE_WRITE_4(sc, AE_MAC_REG, val); 2039 } 2040 2041 static void 2042 ae_rxfilter(ae_softc_t *sc) 2043 { 2044 struct ifnet *ifp; 2045 struct ifmultiaddr *ifma; 2046 uint32_t crc; 2047 uint32_t mchash[2]; 2048 uint32_t rxcfg; 2049 2050 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2051 2052 AE_LOCK_ASSERT(sc); 2053 2054 ifp = sc->ifp; 2055 2056 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2057 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2058 2059 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2060 rxcfg |= AE_MAC_BCAST_EN; 2061 if ((ifp->if_flags & IFF_PROMISC) != 0) 2062 rxcfg |= AE_MAC_PROMISC_EN; 2063 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2064 rxcfg |= AE_MAC_MCAST_EN; 2065 2066 /* 2067 * Wipe old settings. 2068 */ 2069 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2070 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2071 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2072 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2073 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2074 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2075 return; 2076 } 2077 2078 /* 2079 * Load multicast tables. 2080 */ 2081 bzero(mchash, sizeof(mchash)); 2082 if_maddr_rlock(ifp); 2083 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2084 if (ifma->ifma_addr->sa_family != AF_LINK) 2085 continue; 2086 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 2087 ifma->ifma_addr), ETHER_ADDR_LEN); 2088 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2089 } 2090 if_maddr_runlock(ifp); 2091 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2092 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2093 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2094 } 2095 2096 static int 2097 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2098 { 2099 struct ae_softc *sc; 2100 struct ifreq *ifr; 2101 struct mii_data *mii; 2102 int error, mask; 2103 2104 sc = ifp->if_softc; 2105 ifr = (struct ifreq *)data; 2106 error = 0; 2107 2108 switch (cmd) { 2109 case SIOCSIFMTU: 2110 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2111 error = EINVAL; 2112 else if (ifp->if_mtu != ifr->ifr_mtu) { 2113 AE_LOCK(sc); 2114 ifp->if_mtu = ifr->ifr_mtu; 2115 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2116 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2117 ae_init_locked(sc); 2118 } 2119 AE_UNLOCK(sc); 2120 } 2121 break; 2122 case SIOCSIFFLAGS: 2123 AE_LOCK(sc); 2124 if ((ifp->if_flags & IFF_UP) != 0) { 2125 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2126 if (((ifp->if_flags ^ sc->if_flags) 2127 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2128 ae_rxfilter(sc); 2129 } else { 2130 if ((sc->flags & AE_FLAG_DETACH) == 0) 2131 ae_init_locked(sc); 2132 } 2133 } else { 2134 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2135 ae_stop(sc); 2136 } 2137 sc->if_flags = ifp->if_flags; 2138 AE_UNLOCK(sc); 2139 break; 2140 case SIOCADDMULTI: 2141 case SIOCDELMULTI: 2142 AE_LOCK(sc); 2143 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2144 ae_rxfilter(sc); 2145 AE_UNLOCK(sc); 2146 break; 2147 case SIOCSIFMEDIA: 2148 case SIOCGIFMEDIA: 2149 mii = device_get_softc(sc->miibus); 2150 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2151 break; 2152 case SIOCSIFCAP: 2153 AE_LOCK(sc); 2154 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2155 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2156 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2157 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2158 ae_rxvlan(sc); 2159 } 2160 VLAN_CAPABILITIES(ifp); 2161 AE_UNLOCK(sc); 2162 break; 2163 default: 2164 error = ether_ioctl(ifp, cmd, data); 2165 break; 2166 } 2167 return (error); 2168 } 2169 2170 static void 2171 ae_stop(ae_softc_t *sc) 2172 { 2173 struct ifnet *ifp; 2174 int i; 2175 2176 AE_LOCK_ASSERT(sc); 2177 2178 ifp = sc->ifp; 2179 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2180 sc->flags &= ~AE_FLAG_LINK; 2181 sc->wd_timer = 0; /* Cancel watchdog. */ 2182 callout_stop(&sc->tick_ch); 2183 2184 /* 2185 * Clear and disable interrupts. 2186 */ 2187 AE_WRITE_4(sc, AE_IMR_REG, 0); 2188 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2189 2190 /* 2191 * Stop Rx/Tx MACs. 2192 */ 2193 ae_stop_txmac(sc); 2194 ae_stop_rxmac(sc); 2195 2196 /* 2197 * Stop DMA engines. 2198 */ 2199 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2200 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2201 2202 /* 2203 * Wait for everything to enter idle state. 2204 */ 2205 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2206 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2207 break; 2208 DELAY(100); 2209 } 2210 if (i == AE_IDLE_TIMEOUT) 2211 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2212 } 2213 2214 static void 2215 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2216 { 2217 2218 if ((flags & AE_TXS_BCAST) != 0) 2219 stats->tx_bcast++; 2220 if ((flags & AE_TXS_MCAST) != 0) 2221 stats->tx_mcast++; 2222 if ((flags & AE_TXS_PAUSE) != 0) 2223 stats->tx_pause++; 2224 if ((flags & AE_TXS_CTRL) != 0) 2225 stats->tx_ctrl++; 2226 if ((flags & AE_TXS_DEFER) != 0) 2227 stats->tx_defer++; 2228 if ((flags & AE_TXS_EXCDEFER) != 0) 2229 stats->tx_excdefer++; 2230 if ((flags & AE_TXS_SINGLECOL) != 0) 2231 stats->tx_singlecol++; 2232 if ((flags & AE_TXS_MULTICOL) != 0) 2233 stats->tx_multicol++; 2234 if ((flags & AE_TXS_LATECOL) != 0) 2235 stats->tx_latecol++; 2236 if ((flags & AE_TXS_ABORTCOL) != 0) 2237 stats->tx_abortcol++; 2238 if ((flags & AE_TXS_UNDERRUN) != 0) 2239 stats->tx_underrun++; 2240 } 2241 2242 static void 2243 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2244 { 2245 2246 if ((flags & AE_RXD_BCAST) != 0) 2247 stats->rx_bcast++; 2248 if ((flags & AE_RXD_MCAST) != 0) 2249 stats->rx_mcast++; 2250 if ((flags & AE_RXD_PAUSE) != 0) 2251 stats->rx_pause++; 2252 if ((flags & AE_RXD_CTRL) != 0) 2253 stats->rx_ctrl++; 2254 if ((flags & AE_RXD_CRCERR) != 0) 2255 stats->rx_crcerr++; 2256 if ((flags & AE_RXD_CODEERR) != 0) 2257 stats->rx_codeerr++; 2258 if ((flags & AE_RXD_RUNT) != 0) 2259 stats->rx_runt++; 2260 if ((flags & AE_RXD_FRAG) != 0) 2261 stats->rx_frag++; 2262 if ((flags & AE_RXD_TRUNC) != 0) 2263 stats->rx_trunc++; 2264 if ((flags & AE_RXD_ALIGN) != 0) 2265 stats->rx_align++; 2266 } 2267