1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/module.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 71 #include "miibus_if.h" 72 73 #include "if_aereg.h" 74 #include "if_aevar.h" 75 76 /* 77 * Devices supported by this driver. 78 */ 79 static struct ae_dev { 80 uint16_t vendorid; 81 uint16_t deviceid; 82 const char *name; 83 } ae_devs[] = { 84 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 85 "Attansic Technology Corp, L2 FastEthernet" }, 86 }; 87 #define AE_DEVS_COUNT nitems(ae_devs) 88 89 static struct resource_spec ae_res_spec_mem[] = { 90 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 91 { -1, 0, 0 } 92 }; 93 static struct resource_spec ae_res_spec_irq[] = { 94 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 95 { -1, 0, 0 } 96 }; 97 static struct resource_spec ae_res_spec_msi[] = { 98 { SYS_RES_IRQ, 1, RF_ACTIVE }, 99 { -1, 0, 0 } 100 }; 101 102 static int ae_probe(device_t dev); 103 static int ae_attach(device_t dev); 104 static void ae_pcie_init(ae_softc_t *sc); 105 static void ae_phy_reset(ae_softc_t *sc); 106 static void ae_phy_init(ae_softc_t *sc); 107 static int ae_reset(ae_softc_t *sc); 108 static void ae_init(void *arg); 109 static int ae_init_locked(ae_softc_t *sc); 110 static int ae_detach(device_t dev); 111 static int ae_miibus_readreg(device_t dev, int phy, int reg); 112 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 113 static void ae_miibus_statchg(device_t dev); 114 static void ae_mediastatus(if_t ifp, struct ifmediareq *ifmr); 115 static int ae_mediachange(if_t ifp); 116 static void ae_retrieve_address(ae_softc_t *sc); 117 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 118 int error); 119 static int ae_alloc_rings(ae_softc_t *sc); 120 static void ae_dma_free(ae_softc_t *sc); 121 static int ae_shutdown(device_t dev); 122 static int ae_suspend(device_t dev); 123 static void ae_powersave_disable(ae_softc_t *sc); 124 static void ae_powersave_enable(ae_softc_t *sc); 125 static int ae_resume(device_t dev); 126 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 127 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 128 static void ae_start(if_t ifp); 129 static void ae_start_locked(if_t ifp); 130 static void ae_link_task(void *arg, int pending); 131 static void ae_stop_rxmac(ae_softc_t *sc); 132 static void ae_stop_txmac(ae_softc_t *sc); 133 static void ae_mac_config(ae_softc_t *sc); 134 static int ae_intr(void *arg); 135 static void ae_int_task(void *arg, int pending); 136 static void ae_tx_intr(ae_softc_t *sc); 137 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 138 static void ae_rx_intr(ae_softc_t *sc); 139 static void ae_watchdog(ae_softc_t *sc); 140 static void ae_tick(void *arg); 141 static void ae_rxfilter(ae_softc_t *sc); 142 static void ae_rxvlan(ae_softc_t *sc); 143 static int ae_ioctl(if_t ifp, u_long cmd, caddr_t data); 144 static void ae_stop(ae_softc_t *sc); 145 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 146 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 147 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 148 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 149 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 150 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 151 static void ae_init_tunables(ae_softc_t *sc); 152 153 static device_method_t ae_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ae_probe), 156 DEVMETHOD(device_attach, ae_attach), 157 DEVMETHOD(device_detach, ae_detach), 158 DEVMETHOD(device_shutdown, ae_shutdown), 159 DEVMETHOD(device_suspend, ae_suspend), 160 DEVMETHOD(device_resume, ae_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 166 { NULL, NULL } 167 }; 168 static driver_t ae_driver = { 169 "ae", 170 ae_methods, 171 sizeof(ae_softc_t) 172 }; 173 174 DRIVER_MODULE(ae, pci, ae_driver, 0, 0); 175 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 176 nitems(ae_devs)); 177 DRIVER_MODULE(miibus, ae, miibus_driver, 0, 0); 178 MODULE_DEPEND(ae, pci, 1, 1, 1); 179 MODULE_DEPEND(ae, ether, 1, 1, 1); 180 MODULE_DEPEND(ae, miibus, 1, 1, 1); 181 182 /* 183 * Tunables. 184 */ 185 static int msi_disable = 0; 186 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 187 188 #define AE_READ_4(sc, reg) \ 189 bus_read_4((sc)->mem[0], (reg)) 190 #define AE_READ_2(sc, reg) \ 191 bus_read_2((sc)->mem[0], (reg)) 192 #define AE_READ_1(sc, reg) \ 193 bus_read_1((sc)->mem[0], (reg)) 194 #define AE_WRITE_4(sc, reg, val) \ 195 bus_write_4((sc)->mem[0], (reg), (val)) 196 #define AE_WRITE_2(sc, reg, val) \ 197 bus_write_2((sc)->mem[0], (reg), (val)) 198 #define AE_WRITE_1(sc, reg, val) \ 199 bus_write_1((sc)->mem[0], (reg), (val)) 200 #define AE_PHY_READ(sc, reg) \ 201 ae_miibus_readreg(sc->dev, 0, reg) 202 #define AE_PHY_WRITE(sc, reg, val) \ 203 ae_miibus_writereg(sc->dev, 0, reg, val) 204 #define AE_CHECK_EADDR_VALID(eaddr) \ 205 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 206 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 207 #define AE_RXD_VLAN(vtag) \ 208 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 209 #define AE_TXD_VLAN(vtag) \ 210 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 211 212 static int 213 ae_probe(device_t dev) 214 { 215 uint16_t deviceid, vendorid; 216 int i; 217 218 vendorid = pci_get_vendor(dev); 219 deviceid = pci_get_device(dev); 220 221 /* 222 * Search through the list of supported devs for matching one. 223 */ 224 for (i = 0; i < AE_DEVS_COUNT; i++) { 225 if (vendorid == ae_devs[i].vendorid && 226 deviceid == ae_devs[i].deviceid) { 227 device_set_desc(dev, ae_devs[i].name); 228 return (BUS_PROBE_DEFAULT); 229 } 230 } 231 return (ENXIO); 232 } 233 234 static int 235 ae_attach(device_t dev) 236 { 237 ae_softc_t *sc; 238 if_t ifp; 239 uint8_t chiprev; 240 uint32_t pcirev; 241 int nmsi, pmc; 242 int error; 243 244 sc = device_get_softc(dev); /* Automatically allocated and zeroed 245 on attach. */ 246 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 247 sc->dev = dev; 248 249 /* 250 * Initialize mutexes and tasks. 251 */ 252 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 253 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 254 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 255 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 256 257 pci_enable_busmaster(dev); /* Enable bus mastering. */ 258 259 sc->spec_mem = ae_res_spec_mem; 260 261 /* 262 * Allocate memory-mapped registers. 263 */ 264 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 265 if (error != 0) { 266 device_printf(dev, "could not allocate memory resources.\n"); 267 sc->spec_mem = NULL; 268 goto fail; 269 } 270 271 /* 272 * Retrieve PCI and chip revisions. 273 */ 274 pcirev = pci_get_revid(dev); 275 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 276 AE_MASTER_REVNUM_MASK; 277 if (bootverbose) { 278 device_printf(dev, "pci device revision: %#04x\n", pcirev); 279 device_printf(dev, "chip id: %#02x\n", chiprev); 280 } 281 nmsi = pci_msi_count(dev); 282 if (bootverbose) 283 device_printf(dev, "MSI count: %d.\n", nmsi); 284 285 /* 286 * Allocate interrupt resources. 287 */ 288 if (msi_disable == 0 && nmsi == 1) { 289 error = pci_alloc_msi(dev, &nmsi); 290 if (error == 0) { 291 device_printf(dev, "Using MSI messages.\n"); 292 sc->spec_irq = ae_res_spec_msi; 293 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 294 if (error != 0) { 295 device_printf(dev, "MSI allocation failed.\n"); 296 sc->spec_irq = NULL; 297 pci_release_msi(dev); 298 } else { 299 sc->flags |= AE_FLAG_MSI; 300 } 301 } 302 } 303 if (sc->spec_irq == NULL) { 304 sc->spec_irq = ae_res_spec_irq; 305 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 306 if (error != 0) { 307 device_printf(dev, "could not allocate IRQ resources.\n"); 308 sc->spec_irq = NULL; 309 goto fail; 310 } 311 } 312 313 ae_init_tunables(sc); 314 315 ae_phy_reset(sc); /* Reset PHY. */ 316 error = ae_reset(sc); /* Reset the controller itself. */ 317 if (error != 0) 318 goto fail; 319 320 ae_pcie_init(sc); 321 322 ae_retrieve_address(sc); /* Load MAC address. */ 323 324 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 325 if (error != 0) 326 goto fail; 327 328 ifp = sc->ifp = if_alloc(IFT_ETHER); 329 if_setsoftc(ifp, sc); 330 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 331 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 332 if_setioctlfn(ifp, ae_ioctl); 333 if_setstartfn(ifp, ae_start); 334 if_setinitfn(ifp, ae_init); 335 if_setcapabilities(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING); 336 if_sethwassist(ifp, 0); 337 if_setsendqlen(ifp, ifqmaxlen); 338 if_setsendqready(ifp); 339 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 340 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 341 sc->flags |= AE_FLAG_PMG; 342 } 343 if_setcapenable(ifp, if_getcapabilities(ifp)); 344 345 /* 346 * Configure and attach MII bus. 347 */ 348 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 349 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 350 MII_OFFSET_ANY, 0); 351 if (error != 0) { 352 device_printf(dev, "attaching PHYs failed\n"); 353 goto fail; 354 } 355 356 ether_ifattach(ifp, sc->eaddr); 357 /* Tell the upper layer(s) we support long frames. */ 358 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 359 360 /* 361 * Create and run all helper tasks. 362 */ 363 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 364 taskqueue_thread_enqueue, &sc->tq); 365 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 366 device_get_nameunit(sc->dev)); 367 368 /* 369 * Configure interrupt handlers. 370 */ 371 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 372 ae_intr, NULL, sc, &sc->intrhand); 373 if (error != 0) { 374 device_printf(dev, "could not set up interrupt handler.\n"); 375 taskqueue_free(sc->tq); 376 sc->tq = NULL; 377 ether_ifdetach(ifp); 378 goto fail; 379 } 380 381 fail: 382 if (error != 0) 383 ae_detach(dev); 384 385 return (error); 386 } 387 388 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 389 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 390 391 static void 392 ae_init_tunables(ae_softc_t *sc) 393 { 394 struct sysctl_ctx_list *ctx; 395 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 396 struct ae_stats *ae_stats; 397 398 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 399 ae_stats = &sc->stats; 400 401 ctx = device_get_sysctl_ctx(sc->dev); 402 root = device_get_sysctl_tree(sc->dev); 403 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 404 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ae statistics"); 405 406 /* 407 * Receiver statistcics. 408 */ 409 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 410 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 411 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 412 "broadcast frames", &ae_stats->rx_bcast); 413 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 414 "multicast frames", &ae_stats->rx_mcast); 415 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 416 "PAUSE frames", &ae_stats->rx_pause); 417 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 418 "control frames", &ae_stats->rx_ctrl); 419 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 420 "frames with CRC errors", &ae_stats->rx_crcerr); 421 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 422 "frames with invalid opcode", &ae_stats->rx_codeerr); 423 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 424 "runt frames", &ae_stats->rx_runt); 425 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 426 "fragmented frames", &ae_stats->rx_frag); 427 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 428 "frames with alignment errors", &ae_stats->rx_align); 429 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 430 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 431 432 /* 433 * Receiver statistcics. 434 */ 435 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 436 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 438 "broadcast frames", &ae_stats->tx_bcast); 439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 440 "multicast frames", &ae_stats->tx_mcast); 441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 442 "PAUSE frames", &ae_stats->tx_pause); 443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 444 "control frames", &ae_stats->tx_ctrl); 445 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 446 "deferrals occuried", &ae_stats->tx_defer); 447 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 448 "excessive deferrals occuried", &ae_stats->tx_excdefer); 449 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 450 "single collisions occuried", &ae_stats->tx_singlecol); 451 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 452 "multiple collisions occuried", &ae_stats->tx_multicol); 453 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 454 "late collisions occuried", &ae_stats->tx_latecol); 455 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 456 "transmit aborts due collisions", &ae_stats->tx_abortcol); 457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 458 "Tx FIFO underruns", &ae_stats->tx_underrun); 459 } 460 461 static void 462 ae_pcie_init(ae_softc_t *sc) 463 { 464 465 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 466 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 467 } 468 469 static void 470 ae_phy_reset(ae_softc_t *sc) 471 { 472 473 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 474 DELAY(1000); /* XXX: pause(9) ? */ 475 } 476 477 static int 478 ae_reset(ae_softc_t *sc) 479 { 480 int i; 481 482 /* 483 * Issue a soft reset. 484 */ 485 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 486 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 487 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 488 489 /* 490 * Wait for reset to complete. 491 */ 492 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 493 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 494 break; 495 DELAY(10); 496 } 497 if (i == AE_RESET_TIMEOUT) { 498 device_printf(sc->dev, "reset timeout.\n"); 499 return (ENXIO); 500 } 501 502 /* 503 * Wait for everything to enter idle state. 504 */ 505 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 506 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 507 break; 508 DELAY(100); 509 } 510 if (i == AE_IDLE_TIMEOUT) { 511 device_printf(sc->dev, "could not enter idle state.\n"); 512 return (ENXIO); 513 } 514 return (0); 515 } 516 517 static void 518 ae_init(void *arg) 519 { 520 ae_softc_t *sc; 521 522 sc = (ae_softc_t *)arg; 523 AE_LOCK(sc); 524 ae_init_locked(sc); 525 AE_UNLOCK(sc); 526 } 527 528 static void 529 ae_phy_init(ae_softc_t *sc) 530 { 531 532 /* 533 * Enable link status change interrupt. 534 * XXX magic numbers. 535 */ 536 #ifdef notyet 537 AE_PHY_WRITE(sc, 18, 0xc00); 538 #endif 539 } 540 541 static int 542 ae_init_locked(ae_softc_t *sc) 543 { 544 if_t ifp; 545 struct mii_data *mii; 546 uint8_t eaddr[ETHER_ADDR_LEN]; 547 uint32_t val; 548 bus_addr_t addr; 549 550 AE_LOCK_ASSERT(sc); 551 552 ifp = sc->ifp; 553 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 554 return (0); 555 mii = device_get_softc(sc->miibus); 556 557 ae_stop(sc); 558 ae_reset(sc); 559 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 560 ae_phy_init(sc); 561 ae_powersave_disable(sc); 562 563 /* 564 * Clear and disable interrupts. 565 */ 566 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 567 568 /* 569 * Set the MAC address. 570 */ 571 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 572 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 573 AE_WRITE_4(sc, AE_EADDR0_REG, val); 574 val = eaddr[0] << 8 | eaddr[1]; 575 AE_WRITE_4(sc, AE_EADDR1_REG, val); 576 577 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 578 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 579 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 580 /* 581 * Set ring buffers base addresses. 582 */ 583 addr = sc->dma_rxd_busaddr; 584 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 585 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 586 addr = sc->dma_txd_busaddr; 587 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 588 addr = sc->dma_txs_busaddr; 589 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 590 591 /* 592 * Configure ring buffers sizes. 593 */ 594 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 595 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 596 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 597 598 /* 599 * Configure interframe gap parameters. 600 */ 601 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 602 AE_IFG_TXIPG_MASK) | 603 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 604 AE_IFG_RXIPG_MASK) | 605 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 606 AE_IFG_IPGR1_MASK) | 607 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 608 AE_IFG_IPGR2_MASK); 609 AE_WRITE_4(sc, AE_IFG_REG, val); 610 611 /* 612 * Configure half-duplex operation. 613 */ 614 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 615 AE_HDPX_LCOL_MASK) | 616 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 617 AE_HDPX_RETRY_MASK) | 618 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 619 AE_HDPX_ABEBT_MASK) | 620 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 621 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 622 AE_WRITE_4(sc, AE_HDPX_REG, val); 623 624 /* 625 * Configure interrupt moderate timer. 626 */ 627 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 628 val = AE_READ_4(sc, AE_MASTER_REG); 629 val |= AE_MASTER_IMT_EN; 630 AE_WRITE_4(sc, AE_MASTER_REG, val); 631 632 /* 633 * Configure interrupt clearing timer. 634 */ 635 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 636 637 /* 638 * Configure MTU. 639 */ 640 val = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 641 ETHER_CRC_LEN; 642 AE_WRITE_2(sc, AE_MTU_REG, val); 643 644 /* 645 * Configure cut-through threshold. 646 */ 647 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 648 649 /* 650 * Configure flow control. 651 */ 652 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 653 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 654 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 655 (AE_RXD_COUNT_DEFAULT / 12)); 656 657 /* 658 * Init mailboxes. 659 */ 660 sc->txd_cur = sc->rxd_cur = 0; 661 sc->txs_ack = sc->txd_ack = 0; 662 sc->rxd_cur = 0; 663 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 664 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 665 666 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 667 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 668 669 /* 670 * Enable DMA. 671 */ 672 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 673 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 674 675 /* 676 * Check if everything is OK. 677 */ 678 val = AE_READ_4(sc, AE_ISR_REG); 679 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 680 device_printf(sc->dev, "Initialization failed.\n"); 681 return (ENXIO); 682 } 683 684 /* 685 * Clear interrupt status. 686 */ 687 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 688 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 689 690 /* 691 * Enable interrupts. 692 */ 693 val = AE_READ_4(sc, AE_MASTER_REG); 694 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 695 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 696 697 /* 698 * Disable WOL. 699 */ 700 AE_WRITE_4(sc, AE_WOL_REG, 0); 701 702 /* 703 * Configure MAC. 704 */ 705 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 706 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 707 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 708 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 709 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 710 AE_MAC_PREAMBLE_MASK); 711 AE_WRITE_4(sc, AE_MAC_REG, val); 712 713 /* 714 * Configure Rx MAC. 715 */ 716 ae_rxfilter(sc); 717 ae_rxvlan(sc); 718 719 /* 720 * Enable Tx/Rx. 721 */ 722 val = AE_READ_4(sc, AE_MAC_REG); 723 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 724 725 sc->flags &= ~AE_FLAG_LINK; 726 mii_mediachg(mii); /* Switch to the current media. */ 727 728 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 729 730 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 731 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 732 733 #ifdef AE_DEBUG 734 device_printf(sc->dev, "Initialization complete.\n"); 735 #endif 736 737 return (0); 738 } 739 740 static int 741 ae_detach(device_t dev) 742 { 743 struct ae_softc *sc; 744 if_t ifp; 745 746 sc = device_get_softc(dev); 747 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 748 ifp = sc->ifp; 749 if (device_is_attached(dev)) { 750 AE_LOCK(sc); 751 sc->flags |= AE_FLAG_DETACH; 752 ae_stop(sc); 753 AE_UNLOCK(sc); 754 callout_drain(&sc->tick_ch); 755 taskqueue_drain(sc->tq, &sc->int_task); 756 taskqueue_drain(taskqueue_swi, &sc->link_task); 757 ether_ifdetach(ifp); 758 } 759 if (sc->tq != NULL) { 760 taskqueue_drain(sc->tq, &sc->int_task); 761 taskqueue_free(sc->tq); 762 sc->tq = NULL; 763 } 764 if (sc->miibus != NULL) { 765 device_delete_child(dev, sc->miibus); 766 sc->miibus = NULL; 767 } 768 bus_generic_detach(sc->dev); 769 ae_dma_free(sc); 770 if (sc->intrhand != NULL) { 771 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 772 sc->intrhand = NULL; 773 } 774 if (ifp != NULL) { 775 if_free(ifp); 776 sc->ifp = NULL; 777 } 778 if (sc->spec_irq != NULL) 779 bus_release_resources(dev, sc->spec_irq, sc->irq); 780 if (sc->spec_mem != NULL) 781 bus_release_resources(dev, sc->spec_mem, sc->mem); 782 if ((sc->flags & AE_FLAG_MSI) != 0) 783 pci_release_msi(dev); 784 mtx_destroy(&sc->mtx); 785 786 return (0); 787 } 788 789 static int 790 ae_miibus_readreg(device_t dev, int phy, int reg) 791 { 792 ae_softc_t *sc; 793 uint32_t val; 794 int i; 795 796 sc = device_get_softc(dev); 797 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 798 799 /* 800 * Locking is done in upper layers. 801 */ 802 803 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 804 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 805 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 806 AE_WRITE_4(sc, AE_MDIO_REG, val); 807 808 /* 809 * Wait for operation to complete. 810 */ 811 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 812 DELAY(2); 813 val = AE_READ_4(sc, AE_MDIO_REG); 814 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 815 break; 816 } 817 if (i == AE_MDIO_TIMEOUT) { 818 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 819 return (0); 820 } 821 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 822 } 823 824 static int 825 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 826 { 827 ae_softc_t *sc; 828 uint32_t aereg; 829 int i; 830 831 sc = device_get_softc(dev); 832 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 833 834 /* 835 * Locking is done in upper layers. 836 */ 837 838 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 839 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 840 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 841 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 842 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 843 844 /* 845 * Wait for operation to complete. 846 */ 847 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 848 DELAY(2); 849 aereg = AE_READ_4(sc, AE_MDIO_REG); 850 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 851 break; 852 } 853 if (i == AE_MDIO_TIMEOUT) { 854 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 855 } 856 return (0); 857 } 858 859 static void 860 ae_miibus_statchg(device_t dev) 861 { 862 ae_softc_t *sc; 863 864 sc = device_get_softc(dev); 865 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 866 } 867 868 static void 869 ae_mediastatus(if_t ifp, struct ifmediareq *ifmr) 870 { 871 ae_softc_t *sc; 872 struct mii_data *mii; 873 874 sc = if_getsoftc(ifp); 875 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 876 877 AE_LOCK(sc); 878 mii = device_get_softc(sc->miibus); 879 mii_pollstat(mii); 880 ifmr->ifm_status = mii->mii_media_status; 881 ifmr->ifm_active = mii->mii_media_active; 882 AE_UNLOCK(sc); 883 } 884 885 static int 886 ae_mediachange(if_t ifp) 887 { 888 ae_softc_t *sc; 889 struct mii_data *mii; 890 struct mii_softc *mii_sc; 891 int error; 892 893 /* XXX: check IFF_UP ?? */ 894 sc = if_getsoftc(ifp); 895 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 896 AE_LOCK(sc); 897 mii = device_get_softc(sc->miibus); 898 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 899 PHY_RESET(mii_sc); 900 error = mii_mediachg(mii); 901 AE_UNLOCK(sc); 902 903 return (error); 904 } 905 906 static int 907 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 908 { 909 int error; 910 uint32_t val; 911 912 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 913 914 /* 915 * Not sure why, but Linux does this. 916 */ 917 val = AE_READ_4(sc, AE_SPICTL_REG); 918 if ((val & AE_SPICTL_VPD_EN) != 0) { 919 val &= ~AE_SPICTL_VPD_EN; 920 AE_WRITE_4(sc, AE_SPICTL_REG, val); 921 } 922 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 923 return (error); 924 } 925 926 static int 927 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 928 { 929 uint32_t val; 930 int i; 931 932 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 933 934 /* 935 * VPD registers start at offset 0x100. Read them. 936 */ 937 val = 0x100 + reg * 4; 938 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 939 AE_VPD_CAP_ADDR_MASK); 940 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 941 DELAY(2000); 942 val = AE_READ_4(sc, AE_VPD_CAP_REG); 943 if ((val & AE_VPD_CAP_DONE) != 0) 944 break; 945 } 946 if (i == AE_VPD_TIMEOUT) { 947 device_printf(sc->dev, "timeout reading VPD register %d.\n", 948 reg); 949 return (ETIMEDOUT); 950 } 951 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 952 return (0); 953 } 954 955 static int 956 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 957 { 958 uint32_t word, reg, val; 959 int error; 960 int found; 961 int vpdc; 962 int i; 963 964 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 965 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 966 967 /* 968 * Check for EEPROM. 969 */ 970 error = ae_check_eeprom_present(sc, &vpdc); 971 if (error != 0) 972 return (error); 973 974 /* 975 * Read the VPD configuration space. 976 * Each register is prefixed with signature, 977 * so we can check if it is valid. 978 */ 979 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 980 error = ae_vpd_read_word(sc, i, &word); 981 if (error != 0) 982 break; 983 984 /* 985 * Check signature. 986 */ 987 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 988 break; 989 reg = word >> AE_VPD_REG_SHIFT; 990 i++; /* Move to the next word. */ 991 992 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 993 continue; 994 995 error = ae_vpd_read_word(sc, i, &val); 996 if (error != 0) 997 break; 998 if (reg == AE_EADDR0_REG) 999 eaddr[0] = val; 1000 else 1001 eaddr[1] = val; 1002 found++; 1003 } 1004 1005 if (found < 2) 1006 return (ENOENT); 1007 1008 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1009 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1010 if (bootverbose) 1011 device_printf(sc->dev, 1012 "VPD ethernet address registers are invalid.\n"); 1013 return (EINVAL); 1014 } 1015 return (0); 1016 } 1017 1018 static int 1019 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1020 { 1021 1022 /* 1023 * BIOS is supposed to set this. 1024 */ 1025 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1026 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1027 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1028 1029 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1030 if (bootverbose) 1031 device_printf(sc->dev, 1032 "Ethernet address registers are invalid.\n"); 1033 return (EINVAL); 1034 } 1035 return (0); 1036 } 1037 1038 static void 1039 ae_retrieve_address(ae_softc_t *sc) 1040 { 1041 uint32_t eaddr[2] = {0, 0}; 1042 int error; 1043 1044 /* 1045 *Check for EEPROM. 1046 */ 1047 error = ae_get_vpd_eaddr(sc, eaddr); 1048 if (error != 0) 1049 error = ae_get_reg_eaddr(sc, eaddr); 1050 if (error != 0) { 1051 if (bootverbose) 1052 device_printf(sc->dev, 1053 "Generating random ethernet address.\n"); 1054 eaddr[0] = arc4random(); 1055 1056 /* 1057 * Set OUI to ASUSTek COMPUTER INC. 1058 */ 1059 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1060 sc->eaddr[1] = 0x1f; 1061 sc->eaddr[2] = 0xc6; 1062 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1063 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1064 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1065 } else { 1066 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1067 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1068 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1069 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1070 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1071 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1072 } 1073 } 1074 1075 static void 1076 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1077 { 1078 bus_addr_t *addr = arg; 1079 1080 if (error != 0) 1081 return; 1082 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1083 nsegs)); 1084 *addr = segs[0].ds_addr; 1085 } 1086 1087 static int 1088 ae_alloc_rings(ae_softc_t *sc) 1089 { 1090 bus_addr_t busaddr; 1091 int error; 1092 1093 /* 1094 * Create parent DMA tag. 1095 */ 1096 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1097 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1098 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1099 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1100 &sc->dma_parent_tag); 1101 if (error != 0) { 1102 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1103 return (error); 1104 } 1105 1106 /* 1107 * Create DMA tag for TxD. 1108 */ 1109 error = bus_dma_tag_create(sc->dma_parent_tag, 1110 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1111 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1112 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1113 &sc->dma_txd_tag); 1114 if (error != 0) { 1115 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1116 return (error); 1117 } 1118 1119 /* 1120 * Create DMA tag for TxS. 1121 */ 1122 error = bus_dma_tag_create(sc->dma_parent_tag, 1123 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1124 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1125 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1126 &sc->dma_txs_tag); 1127 if (error != 0) { 1128 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1129 return (error); 1130 } 1131 1132 /* 1133 * Create DMA tag for RxD. 1134 */ 1135 error = bus_dma_tag_create(sc->dma_parent_tag, 1136 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1137 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1138 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1139 &sc->dma_rxd_tag); 1140 if (error != 0) { 1141 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1142 return (error); 1143 } 1144 1145 /* 1146 * Allocate TxD DMA memory. 1147 */ 1148 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1149 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1150 &sc->dma_txd_map); 1151 if (error != 0) { 1152 device_printf(sc->dev, 1153 "could not allocate DMA memory for TxD ring.\n"); 1154 return (error); 1155 } 1156 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1157 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1158 if (error != 0 || busaddr == 0) { 1159 device_printf(sc->dev, 1160 "could not load DMA map for TxD ring.\n"); 1161 return (error); 1162 } 1163 sc->dma_txd_busaddr = busaddr; 1164 1165 /* 1166 * Allocate TxS DMA memory. 1167 */ 1168 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1169 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1170 &sc->dma_txs_map); 1171 if (error != 0) { 1172 device_printf(sc->dev, 1173 "could not allocate DMA memory for TxS ring.\n"); 1174 return (error); 1175 } 1176 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1177 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1178 if (error != 0 || busaddr == 0) { 1179 device_printf(sc->dev, 1180 "could not load DMA map for TxS ring.\n"); 1181 return (error); 1182 } 1183 sc->dma_txs_busaddr = busaddr; 1184 1185 /* 1186 * Allocate RxD DMA memory. 1187 */ 1188 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1189 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1190 &sc->dma_rxd_map); 1191 if (error != 0) { 1192 device_printf(sc->dev, 1193 "could not allocate DMA memory for RxD ring.\n"); 1194 return (error); 1195 } 1196 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1197 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1198 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1199 if (error != 0 || busaddr == 0) { 1200 device_printf(sc->dev, 1201 "could not load DMA map for RxD ring.\n"); 1202 return (error); 1203 } 1204 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1205 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1206 1207 return (0); 1208 } 1209 1210 static void 1211 ae_dma_free(ae_softc_t *sc) 1212 { 1213 1214 if (sc->dma_txd_tag != NULL) { 1215 if (sc->dma_txd_busaddr != 0) 1216 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1217 if (sc->txd_base != NULL) 1218 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1219 sc->dma_txd_map); 1220 bus_dma_tag_destroy(sc->dma_txd_tag); 1221 sc->dma_txd_tag = NULL; 1222 sc->txd_base = NULL; 1223 sc->dma_txd_busaddr = 0; 1224 } 1225 if (sc->dma_txs_tag != NULL) { 1226 if (sc->dma_txs_busaddr != 0) 1227 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1228 if (sc->txs_base != NULL) 1229 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1230 sc->dma_txs_map); 1231 bus_dma_tag_destroy(sc->dma_txs_tag); 1232 sc->dma_txs_tag = NULL; 1233 sc->txs_base = NULL; 1234 sc->dma_txs_busaddr = 0; 1235 } 1236 if (sc->dma_rxd_tag != NULL) { 1237 if (sc->dma_rxd_busaddr != 0) 1238 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1239 if (sc->rxd_base_dma != NULL) 1240 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1241 sc->dma_rxd_map); 1242 bus_dma_tag_destroy(sc->dma_rxd_tag); 1243 sc->dma_rxd_tag = NULL; 1244 sc->rxd_base_dma = NULL; 1245 sc->dma_rxd_busaddr = 0; 1246 } 1247 if (sc->dma_parent_tag != NULL) { 1248 bus_dma_tag_destroy(sc->dma_parent_tag); 1249 sc->dma_parent_tag = NULL; 1250 } 1251 } 1252 1253 static int 1254 ae_shutdown(device_t dev) 1255 { 1256 ae_softc_t *sc; 1257 int error; 1258 1259 sc = device_get_softc(dev); 1260 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1261 1262 error = ae_suspend(dev); 1263 AE_LOCK(sc); 1264 ae_powersave_enable(sc); 1265 AE_UNLOCK(sc); 1266 return (error); 1267 } 1268 1269 static void 1270 ae_powersave_disable(ae_softc_t *sc) 1271 { 1272 uint32_t val; 1273 1274 AE_LOCK_ASSERT(sc); 1275 1276 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1277 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1278 if (val & AE_PHY_DBG_POWERSAVE) { 1279 val &= ~AE_PHY_DBG_POWERSAVE; 1280 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1281 DELAY(1000); 1282 } 1283 } 1284 1285 static void 1286 ae_powersave_enable(ae_softc_t *sc) 1287 { 1288 uint32_t val; 1289 1290 AE_LOCK_ASSERT(sc); 1291 1292 /* 1293 * XXX magic numbers. 1294 */ 1295 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1296 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1297 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1298 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1299 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1300 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1301 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1302 } 1303 1304 static void 1305 ae_pm_init(ae_softc_t *sc) 1306 { 1307 if_t ifp; 1308 uint32_t val; 1309 uint16_t pmstat; 1310 struct mii_data *mii; 1311 int pmc; 1312 1313 AE_LOCK_ASSERT(sc); 1314 1315 ifp = sc->ifp; 1316 if ((sc->flags & AE_FLAG_PMG) == 0) { 1317 /* Disable WOL entirely. */ 1318 AE_WRITE_4(sc, AE_WOL_REG, 0); 1319 return; 1320 } 1321 1322 /* 1323 * Configure WOL if enabled. 1324 */ 1325 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1326 mii = device_get_softc(sc->miibus); 1327 mii_pollstat(mii); 1328 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1329 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1330 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1331 AE_WOL_MAGIC_PME); 1332 1333 /* 1334 * Configure MAC. 1335 */ 1336 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1337 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1338 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1339 AE_HALFBUF_MASK) | \ 1340 ((AE_MAC_PREAMBLE_DEFAULT << \ 1341 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1342 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1343 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1344 IFM_FDX) != 0) 1345 val |= AE_MAC_FULL_DUPLEX; 1346 AE_WRITE_4(sc, AE_MAC_REG, val); 1347 1348 } else { /* No link. */ 1349 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1350 AE_WOL_LNKCHG_PME); 1351 AE_WRITE_4(sc, AE_MAC_REG, 0); 1352 } 1353 } else { 1354 ae_powersave_enable(sc); 1355 } 1356 1357 /* 1358 * PCIE hacks. Magic numbers. 1359 */ 1360 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1361 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1362 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1363 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1364 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1365 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1366 1367 /* 1368 * Configure PME. 1369 */ 1370 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1371 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1372 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1373 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1374 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1375 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1376 } 1377 } 1378 1379 static int 1380 ae_suspend(device_t dev) 1381 { 1382 ae_softc_t *sc; 1383 1384 sc = device_get_softc(dev); 1385 1386 AE_LOCK(sc); 1387 ae_stop(sc); 1388 ae_pm_init(sc); 1389 AE_UNLOCK(sc); 1390 1391 return (0); 1392 } 1393 1394 static int 1395 ae_resume(device_t dev) 1396 { 1397 ae_softc_t *sc; 1398 1399 sc = device_get_softc(dev); 1400 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1401 1402 AE_LOCK(sc); 1403 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1404 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 1405 ae_init_locked(sc); 1406 AE_UNLOCK(sc); 1407 1408 return (0); 1409 } 1410 1411 static unsigned int 1412 ae_tx_avail_size(ae_softc_t *sc) 1413 { 1414 unsigned int avail; 1415 1416 if (sc->txd_cur >= sc->txd_ack) 1417 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1418 else 1419 avail = sc->txd_ack - sc->txd_cur; 1420 1421 return (avail); 1422 } 1423 1424 static int 1425 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1426 { 1427 struct mbuf *m0; 1428 ae_txd_t *hdr; 1429 unsigned int to_end; 1430 uint16_t len; 1431 1432 AE_LOCK_ASSERT(sc); 1433 1434 m0 = *m_head; 1435 len = m0->m_pkthdr.len; 1436 1437 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1438 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1439 #ifdef AE_DEBUG 1440 if_printf(sc->ifp, "No free Tx available.\n"); 1441 #endif 1442 return ENOBUFS; 1443 } 1444 1445 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1446 bzero(hdr, sizeof(*hdr)); 1447 /* Skip header size. */ 1448 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1449 /* Space available to the end of the ring */ 1450 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1451 if (to_end >= len) { 1452 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1453 } else { 1454 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1455 sc->txd_cur)); 1456 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1457 } 1458 1459 /* 1460 * Set TxD flags and parameters. 1461 */ 1462 if ((m0->m_flags & M_VLANTAG) != 0) { 1463 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1464 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1465 } else { 1466 hdr->len = htole16(len); 1467 } 1468 1469 /* 1470 * Set current TxD position and round up to a 4-byte boundary. 1471 */ 1472 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1473 if (sc->txd_cur == sc->txd_ack) 1474 sc->flags &= ~AE_FLAG_TXAVAIL; 1475 #ifdef AE_DEBUG 1476 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1477 #endif 1478 1479 /* 1480 * Update TxS position and check if there are empty TxS available. 1481 */ 1482 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1483 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1484 if (sc->txs_cur == sc->txs_ack) 1485 sc->flags &= ~AE_FLAG_TXAVAIL; 1486 1487 /* 1488 * Synchronize DMA memory. 1489 */ 1490 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1491 BUS_DMASYNC_PREWRITE); 1492 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1494 1495 return (0); 1496 } 1497 1498 static void 1499 ae_start(if_t ifp) 1500 { 1501 ae_softc_t *sc; 1502 1503 sc = if_getsoftc(ifp); 1504 AE_LOCK(sc); 1505 ae_start_locked(ifp); 1506 AE_UNLOCK(sc); 1507 } 1508 1509 static void 1510 ae_start_locked(if_t ifp) 1511 { 1512 ae_softc_t *sc; 1513 unsigned int count; 1514 struct mbuf *m0; 1515 int error; 1516 1517 sc = if_getsoftc(ifp); 1518 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1519 AE_LOCK_ASSERT(sc); 1520 1521 #ifdef AE_DEBUG 1522 if_printf(ifp, "Start called.\n"); 1523 #endif 1524 1525 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1526 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1527 return; 1528 1529 count = 0; 1530 while (!if_sendq_empty(ifp)) { 1531 m0 = if_dequeue(ifp); 1532 if (m0 == NULL) 1533 break; /* Nothing to do. */ 1534 1535 error = ae_encap(sc, &m0); 1536 if (error != 0) { 1537 if (m0 != NULL) { 1538 if_sendq_prepend(ifp, m0); 1539 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1540 #ifdef AE_DEBUG 1541 if_printf(ifp, "Setting OACTIVE.\n"); 1542 #endif 1543 } 1544 break; 1545 } 1546 count++; 1547 sc->tx_inproc++; 1548 1549 /* Bounce a copy of the frame to BPF. */ 1550 ETHER_BPF_MTAP(ifp, m0); 1551 1552 m_freem(m0); 1553 } 1554 1555 if (count > 0) { /* Something was dequeued. */ 1556 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1557 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1558 #ifdef AE_DEBUG 1559 if_printf(ifp, "%d packets dequeued.\n", count); 1560 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1561 #endif 1562 } 1563 } 1564 1565 static void 1566 ae_link_task(void *arg, int pending) 1567 { 1568 ae_softc_t *sc; 1569 struct mii_data *mii; 1570 if_t ifp; 1571 uint32_t val; 1572 1573 sc = (ae_softc_t *)arg; 1574 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1575 AE_LOCK(sc); 1576 1577 ifp = sc->ifp; 1578 mii = device_get_softc(sc->miibus); 1579 if (mii == NULL || ifp == NULL || 1580 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1581 AE_UNLOCK(sc); /* XXX: could happen? */ 1582 return; 1583 } 1584 1585 sc->flags &= ~AE_FLAG_LINK; 1586 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1587 (IFM_AVALID | IFM_ACTIVE)) { 1588 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1589 case IFM_10_T: 1590 case IFM_100_TX: 1591 sc->flags |= AE_FLAG_LINK; 1592 break; 1593 default: 1594 break; 1595 } 1596 } 1597 1598 /* 1599 * Stop Rx/Tx MACs. 1600 */ 1601 ae_stop_rxmac(sc); 1602 ae_stop_txmac(sc); 1603 1604 if ((sc->flags & AE_FLAG_LINK) != 0) { 1605 ae_mac_config(sc); 1606 1607 /* 1608 * Restart DMA engines. 1609 */ 1610 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1611 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1612 1613 /* 1614 * Enable Rx and Tx MACs. 1615 */ 1616 val = AE_READ_4(sc, AE_MAC_REG); 1617 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1618 AE_WRITE_4(sc, AE_MAC_REG, val); 1619 } 1620 AE_UNLOCK(sc); 1621 } 1622 1623 static void 1624 ae_stop_rxmac(ae_softc_t *sc) 1625 { 1626 uint32_t val; 1627 int i; 1628 1629 AE_LOCK_ASSERT(sc); 1630 1631 /* 1632 * Stop Rx MAC engine. 1633 */ 1634 val = AE_READ_4(sc, AE_MAC_REG); 1635 if ((val & AE_MAC_RX_EN) != 0) { 1636 val &= ~AE_MAC_RX_EN; 1637 AE_WRITE_4(sc, AE_MAC_REG, val); 1638 } 1639 1640 /* 1641 * Stop Rx DMA engine. 1642 */ 1643 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1644 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1645 1646 /* 1647 * Wait for IDLE state. 1648 */ 1649 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1650 val = AE_READ_4(sc, AE_IDLE_REG); 1651 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1652 break; 1653 DELAY(100); 1654 } 1655 if (i == AE_IDLE_TIMEOUT) 1656 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1657 } 1658 1659 static void 1660 ae_stop_txmac(ae_softc_t *sc) 1661 { 1662 uint32_t val; 1663 int i; 1664 1665 AE_LOCK_ASSERT(sc); 1666 1667 /* 1668 * Stop Tx MAC engine. 1669 */ 1670 val = AE_READ_4(sc, AE_MAC_REG); 1671 if ((val & AE_MAC_TX_EN) != 0) { 1672 val &= ~AE_MAC_TX_EN; 1673 AE_WRITE_4(sc, AE_MAC_REG, val); 1674 } 1675 1676 /* 1677 * Stop Tx DMA engine. 1678 */ 1679 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1680 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1681 1682 /* 1683 * Wait for IDLE state. 1684 */ 1685 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1686 val = AE_READ_4(sc, AE_IDLE_REG); 1687 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1688 break; 1689 DELAY(100); 1690 } 1691 if (i == AE_IDLE_TIMEOUT) 1692 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1693 } 1694 1695 static void 1696 ae_mac_config(ae_softc_t *sc) 1697 { 1698 struct mii_data *mii; 1699 uint32_t val; 1700 1701 AE_LOCK_ASSERT(sc); 1702 1703 mii = device_get_softc(sc->miibus); 1704 val = AE_READ_4(sc, AE_MAC_REG); 1705 val &= ~AE_MAC_FULL_DUPLEX; 1706 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1707 1708 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1709 val |= AE_MAC_FULL_DUPLEX; 1710 1711 AE_WRITE_4(sc, AE_MAC_REG, val); 1712 } 1713 1714 static int 1715 ae_intr(void *arg) 1716 { 1717 ae_softc_t *sc; 1718 uint32_t val; 1719 1720 sc = (ae_softc_t *)arg; 1721 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1722 1723 val = AE_READ_4(sc, AE_ISR_REG); 1724 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1725 return (FILTER_STRAY); 1726 1727 /* Disable interrupts. */ 1728 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1729 1730 /* Schedule interrupt processing. */ 1731 taskqueue_enqueue(sc->tq, &sc->int_task); 1732 1733 return (FILTER_HANDLED); 1734 } 1735 1736 static void 1737 ae_int_task(void *arg, int pending) 1738 { 1739 ae_softc_t *sc; 1740 if_t ifp; 1741 uint32_t val; 1742 1743 sc = (ae_softc_t *)arg; 1744 1745 AE_LOCK(sc); 1746 1747 ifp = sc->ifp; 1748 1749 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1750 if (val == 0) { 1751 AE_UNLOCK(sc); 1752 return; 1753 } 1754 1755 /* 1756 * Clear interrupts and disable them. 1757 */ 1758 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1759 1760 #ifdef AE_DEBUG 1761 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1762 #endif 1763 1764 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1765 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1766 AE_ISR_PHY_LINKDOWN)) != 0) { 1767 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1768 ae_init_locked(sc); 1769 AE_UNLOCK(sc); 1770 return; 1771 } 1772 if ((val & AE_ISR_TX_EVENT) != 0) 1773 ae_tx_intr(sc); 1774 if ((val & AE_ISR_RX_EVENT) != 0) 1775 ae_rx_intr(sc); 1776 /* 1777 * Re-enable interrupts. 1778 */ 1779 AE_WRITE_4(sc, AE_ISR_REG, 0); 1780 1781 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1782 if (!if_sendq_empty(ifp)) 1783 ae_start_locked(ifp); 1784 } 1785 } 1786 1787 AE_UNLOCK(sc); 1788 } 1789 1790 static void 1791 ae_tx_intr(ae_softc_t *sc) 1792 { 1793 if_t ifp; 1794 ae_txd_t *txd; 1795 ae_txs_t *txs; 1796 uint16_t flags; 1797 1798 AE_LOCK_ASSERT(sc); 1799 1800 ifp = sc->ifp; 1801 1802 #ifdef AE_DEBUG 1803 if_printf(ifp, "Tx interrupt occuried.\n"); 1804 #endif 1805 1806 /* 1807 * Syncronize DMA buffers. 1808 */ 1809 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1810 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1811 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1812 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1813 1814 for (;;) { 1815 txs = sc->txs_base + sc->txs_ack; 1816 flags = le16toh(txs->flags); 1817 if ((flags & AE_TXS_UPDATE) == 0) 1818 break; 1819 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1820 /* Update stats. */ 1821 ae_update_stats_tx(flags, &sc->stats); 1822 1823 /* 1824 * Update TxS position. 1825 */ 1826 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1827 sc->flags |= AE_FLAG_TXAVAIL; 1828 1829 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1830 if (txs->len != txd->len) 1831 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1832 le16toh(txs->len), le16toh(txd->len)); 1833 1834 /* 1835 * Move txd ack and align on 4-byte boundary. 1836 */ 1837 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1838 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1839 1840 if ((flags & AE_TXS_SUCCESS) != 0) 1841 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1842 else 1843 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1844 1845 sc->tx_inproc--; 1846 } 1847 1848 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1849 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1850 if (sc->tx_inproc < 0) { 1851 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1852 sc->tx_inproc = 0; 1853 } 1854 1855 if (sc->tx_inproc == 0) 1856 sc->wd_timer = 0; /* Unarm watchdog. */ 1857 1858 /* 1859 * Syncronize DMA buffers. 1860 */ 1861 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1862 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1863 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1864 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1865 } 1866 1867 static void 1868 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1869 { 1870 if_t ifp; 1871 struct mbuf *m; 1872 unsigned int size; 1873 uint16_t flags; 1874 1875 AE_LOCK_ASSERT(sc); 1876 1877 ifp = sc->ifp; 1878 flags = le16toh(rxd->flags); 1879 1880 #ifdef AE_DEBUG 1881 if_printf(ifp, "Rx interrupt occuried.\n"); 1882 #endif 1883 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1884 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1885 if_printf(ifp, "Runt frame received."); 1886 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1887 return; 1888 } 1889 1890 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1891 if (m == NULL) { 1892 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1893 return; 1894 } 1895 1896 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1897 (flags & AE_RXD_HAS_VLAN) != 0) { 1898 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1899 m->m_flags |= M_VLANTAG; 1900 } 1901 1902 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1903 /* 1904 * Pass it through. 1905 */ 1906 AE_UNLOCK(sc); 1907 if_input(ifp, m); 1908 AE_LOCK(sc); 1909 } 1910 1911 static void 1912 ae_rx_intr(ae_softc_t *sc) 1913 { 1914 ae_rxd_t *rxd; 1915 if_t ifp; 1916 uint16_t flags; 1917 int count; 1918 1919 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1920 1921 AE_LOCK_ASSERT(sc); 1922 1923 ifp = sc->ifp; 1924 1925 /* 1926 * Syncronize DMA buffers. 1927 */ 1928 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1929 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1930 1931 for (count = 0;; count++) { 1932 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1933 flags = le16toh(rxd->flags); 1934 if ((flags & AE_RXD_UPDATE) == 0) 1935 break; 1936 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1937 /* Update stats. */ 1938 ae_update_stats_rx(flags, &sc->stats); 1939 1940 /* 1941 * Update position index. 1942 */ 1943 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1944 1945 if ((flags & AE_RXD_SUCCESS) != 0) 1946 ae_rxeof(sc, rxd); 1947 else 1948 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1949 } 1950 1951 if (count > 0) { 1952 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1953 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1954 /* 1955 * Update Rx index. 1956 */ 1957 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1958 } 1959 } 1960 1961 static void 1962 ae_watchdog(ae_softc_t *sc) 1963 { 1964 if_t ifp; 1965 1966 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1967 AE_LOCK_ASSERT(sc); 1968 ifp = sc->ifp; 1969 1970 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1971 return; /* Noting to do. */ 1972 1973 if ((sc->flags & AE_FLAG_LINK) == 0) 1974 if_printf(ifp, "watchdog timeout (missed link).\n"); 1975 else 1976 if_printf(ifp, "watchdog timeout - resetting.\n"); 1977 1978 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1979 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1980 ae_init_locked(sc); 1981 if (!if_sendq_empty(ifp)) 1982 ae_start_locked(ifp); 1983 } 1984 1985 static void 1986 ae_tick(void *arg) 1987 { 1988 ae_softc_t *sc; 1989 struct mii_data *mii; 1990 1991 sc = (ae_softc_t *)arg; 1992 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1993 AE_LOCK_ASSERT(sc); 1994 1995 mii = device_get_softc(sc->miibus); 1996 mii_tick(mii); 1997 ae_watchdog(sc); /* Watchdog check. */ 1998 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 1999 } 2000 2001 static void 2002 ae_rxvlan(ae_softc_t *sc) 2003 { 2004 if_t ifp; 2005 uint32_t val; 2006 2007 AE_LOCK_ASSERT(sc); 2008 ifp = sc->ifp; 2009 val = AE_READ_4(sc, AE_MAC_REG); 2010 val &= ~AE_MAC_RMVLAN_EN; 2011 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2012 val |= AE_MAC_RMVLAN_EN; 2013 AE_WRITE_4(sc, AE_MAC_REG, val); 2014 } 2015 2016 static u_int 2017 ae_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2018 { 2019 uint32_t crc, *mchash = arg; 2020 2021 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2022 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2023 2024 return (1); 2025 } 2026 2027 static void 2028 ae_rxfilter(ae_softc_t *sc) 2029 { 2030 if_t ifp; 2031 uint32_t mchash[2]; 2032 uint32_t rxcfg; 2033 2034 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2035 2036 AE_LOCK_ASSERT(sc); 2037 2038 ifp = sc->ifp; 2039 2040 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2041 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2042 2043 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2044 rxcfg |= AE_MAC_BCAST_EN; 2045 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2046 rxcfg |= AE_MAC_PROMISC_EN; 2047 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2048 rxcfg |= AE_MAC_MCAST_EN; 2049 2050 /* 2051 * Wipe old settings. 2052 */ 2053 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2054 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2055 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2056 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2057 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2058 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2059 return; 2060 } 2061 2062 /* 2063 * Load multicast tables. 2064 */ 2065 bzero(mchash, sizeof(mchash)); 2066 if_foreach_llmaddr(ifp, ae_hash_maddr, &mchash); 2067 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2068 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2069 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2070 } 2071 2072 static int 2073 ae_ioctl(if_t ifp, u_long cmd, caddr_t data) 2074 { 2075 struct ae_softc *sc; 2076 struct ifreq *ifr; 2077 struct mii_data *mii; 2078 int error, mask; 2079 2080 sc = if_getsoftc(ifp); 2081 ifr = (struct ifreq *)data; 2082 error = 0; 2083 2084 switch (cmd) { 2085 case SIOCSIFMTU: 2086 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2087 error = EINVAL; 2088 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2089 AE_LOCK(sc); 2090 if_setmtu(ifp, ifr->ifr_mtu); 2091 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2092 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2093 ae_init_locked(sc); 2094 } 2095 AE_UNLOCK(sc); 2096 } 2097 break; 2098 case SIOCSIFFLAGS: 2099 AE_LOCK(sc); 2100 if ((if_getflags(ifp) & IFF_UP) != 0) { 2101 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2102 if (((if_getflags(ifp) ^ sc->if_flags) 2103 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2104 ae_rxfilter(sc); 2105 } else { 2106 if ((sc->flags & AE_FLAG_DETACH) == 0) 2107 ae_init_locked(sc); 2108 } 2109 } else { 2110 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2111 ae_stop(sc); 2112 } 2113 sc->if_flags = if_getflags(ifp); 2114 AE_UNLOCK(sc); 2115 break; 2116 case SIOCADDMULTI: 2117 case SIOCDELMULTI: 2118 AE_LOCK(sc); 2119 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2120 ae_rxfilter(sc); 2121 AE_UNLOCK(sc); 2122 break; 2123 case SIOCSIFMEDIA: 2124 case SIOCGIFMEDIA: 2125 mii = device_get_softc(sc->miibus); 2126 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2127 break; 2128 case SIOCSIFCAP: 2129 AE_LOCK(sc); 2130 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2131 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2132 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2133 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2134 ae_rxvlan(sc); 2135 } 2136 VLAN_CAPABILITIES(ifp); 2137 AE_UNLOCK(sc); 2138 break; 2139 default: 2140 error = ether_ioctl(ifp, cmd, data); 2141 break; 2142 } 2143 return (error); 2144 } 2145 2146 static void 2147 ae_stop(ae_softc_t *sc) 2148 { 2149 if_t ifp; 2150 int i; 2151 2152 AE_LOCK_ASSERT(sc); 2153 2154 ifp = sc->ifp; 2155 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2156 sc->flags &= ~AE_FLAG_LINK; 2157 sc->wd_timer = 0; /* Cancel watchdog. */ 2158 callout_stop(&sc->tick_ch); 2159 2160 /* 2161 * Clear and disable interrupts. 2162 */ 2163 AE_WRITE_4(sc, AE_IMR_REG, 0); 2164 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2165 2166 /* 2167 * Stop Rx/Tx MACs. 2168 */ 2169 ae_stop_txmac(sc); 2170 ae_stop_rxmac(sc); 2171 2172 /* 2173 * Stop DMA engines. 2174 */ 2175 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2176 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2177 2178 /* 2179 * Wait for everything to enter idle state. 2180 */ 2181 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2182 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2183 break; 2184 DELAY(100); 2185 } 2186 if (i == AE_IDLE_TIMEOUT) 2187 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2188 } 2189 2190 static void 2191 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2192 { 2193 2194 if ((flags & AE_TXS_BCAST) != 0) 2195 stats->tx_bcast++; 2196 if ((flags & AE_TXS_MCAST) != 0) 2197 stats->tx_mcast++; 2198 if ((flags & AE_TXS_PAUSE) != 0) 2199 stats->tx_pause++; 2200 if ((flags & AE_TXS_CTRL) != 0) 2201 stats->tx_ctrl++; 2202 if ((flags & AE_TXS_DEFER) != 0) 2203 stats->tx_defer++; 2204 if ((flags & AE_TXS_EXCDEFER) != 0) 2205 stats->tx_excdefer++; 2206 if ((flags & AE_TXS_SINGLECOL) != 0) 2207 stats->tx_singlecol++; 2208 if ((flags & AE_TXS_MULTICOL) != 0) 2209 stats->tx_multicol++; 2210 if ((flags & AE_TXS_LATECOL) != 0) 2211 stats->tx_latecol++; 2212 if ((flags & AE_TXS_ABORTCOL) != 0) 2213 stats->tx_abortcol++; 2214 if ((flags & AE_TXS_UNDERRUN) != 0) 2215 stats->tx_underrun++; 2216 } 2217 2218 static void 2219 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2220 { 2221 2222 if ((flags & AE_RXD_BCAST) != 0) 2223 stats->rx_bcast++; 2224 if ((flags & AE_RXD_MCAST) != 0) 2225 stats->rx_mcast++; 2226 if ((flags & AE_RXD_PAUSE) != 0) 2227 stats->rx_pause++; 2228 if ((flags & AE_RXD_CTRL) != 0) 2229 stats->rx_ctrl++; 2230 if ((flags & AE_RXD_CRCERR) != 0) 2231 stats->rx_crcerr++; 2232 if ((flags & AE_RXD_CODEERR) != 0) 2233 stats->rx_codeerr++; 2234 if ((flags & AE_RXD_RUNT) != 0) 2235 stats->rx_runt++; 2236 if ((flags & AE_RXD_FRAG) != 0) 2237 stats->rx_frag++; 2238 if ((flags & AE_RXD_TRUNC) != 0) 2239 stats->rx_trunc++; 2240 if ((flags & AE_RXD_ALIGN) != 0) 2241 stats->rx_align++; 2242 } 2243