1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 28 * 29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_vlan_var.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 74 #include "miibus_if.h" 75 76 #include "if_aereg.h" 77 #include "if_aevar.h" 78 79 /* 80 * Devices supported by this driver. 81 */ 82 static struct ae_dev { 83 uint16_t vendorid; 84 uint16_t deviceid; 85 const char *name; 86 } ae_devs[] = { 87 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 88 "Attansic Technology Corp, L2 FastEthernet" }, 89 }; 90 #define AE_DEVS_COUNT nitems(ae_devs) 91 92 static struct resource_spec ae_res_spec_mem[] = { 93 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 94 { -1, 0, 0 } 95 }; 96 static struct resource_spec ae_res_spec_irq[] = { 97 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 98 { -1, 0, 0 } 99 }; 100 static struct resource_spec ae_res_spec_msi[] = { 101 { SYS_RES_IRQ, 1, RF_ACTIVE }, 102 { -1, 0, 0 } 103 }; 104 105 static int ae_probe(device_t dev); 106 static int ae_attach(device_t dev); 107 static void ae_pcie_init(ae_softc_t *sc); 108 static void ae_phy_reset(ae_softc_t *sc); 109 static void ae_phy_init(ae_softc_t *sc); 110 static int ae_reset(ae_softc_t *sc); 111 static void ae_init(void *arg); 112 static int ae_init_locked(ae_softc_t *sc); 113 static int ae_detach(device_t dev); 114 static int ae_miibus_readreg(device_t dev, int phy, int reg); 115 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val); 116 static void ae_miibus_statchg(device_t dev); 117 static void ae_mediastatus(if_t ifp, struct ifmediareq *ifmr); 118 static int ae_mediachange(if_t ifp); 119 static void ae_retrieve_address(ae_softc_t *sc); 120 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, 121 int error); 122 static int ae_alloc_rings(ae_softc_t *sc); 123 static void ae_dma_free(ae_softc_t *sc); 124 static int ae_shutdown(device_t dev); 125 static int ae_suspend(device_t dev); 126 static void ae_powersave_disable(ae_softc_t *sc); 127 static void ae_powersave_enable(ae_softc_t *sc); 128 static int ae_resume(device_t dev); 129 static unsigned int ae_tx_avail_size(ae_softc_t *sc); 130 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head); 131 static void ae_start(if_t ifp); 132 static void ae_start_locked(if_t ifp); 133 static void ae_link_task(void *arg, int pending); 134 static void ae_stop_rxmac(ae_softc_t *sc); 135 static void ae_stop_txmac(ae_softc_t *sc); 136 static void ae_mac_config(ae_softc_t *sc); 137 static int ae_intr(void *arg); 138 static void ae_int_task(void *arg, int pending); 139 static void ae_tx_intr(ae_softc_t *sc); 140 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd); 141 static void ae_rx_intr(ae_softc_t *sc); 142 static void ae_watchdog(ae_softc_t *sc); 143 static void ae_tick(void *arg); 144 static void ae_rxfilter(ae_softc_t *sc); 145 static void ae_rxvlan(ae_softc_t *sc); 146 static int ae_ioctl(if_t ifp, u_long cmd, caddr_t data); 147 static void ae_stop(ae_softc_t *sc); 148 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc); 149 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word); 150 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr); 151 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr); 152 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats); 153 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats); 154 static void ae_init_tunables(ae_softc_t *sc); 155 156 static device_method_t ae_methods[] = { 157 /* Device interface. */ 158 DEVMETHOD(device_probe, ae_probe), 159 DEVMETHOD(device_attach, ae_attach), 160 DEVMETHOD(device_detach, ae_detach), 161 DEVMETHOD(device_shutdown, ae_shutdown), 162 DEVMETHOD(device_suspend, ae_suspend), 163 DEVMETHOD(device_resume, ae_resume), 164 165 /* MII interface. */ 166 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 167 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 168 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 169 { NULL, NULL } 170 }; 171 static driver_t ae_driver = { 172 "ae", 173 ae_methods, 174 sizeof(ae_softc_t) 175 }; 176 177 DRIVER_MODULE(ae, pci, ae_driver, 0, 0); 178 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ae, ae_devs, 179 nitems(ae_devs)); 180 DRIVER_MODULE(miibus, ae, miibus_driver, 0, 0); 181 MODULE_DEPEND(ae, pci, 1, 1, 1); 182 MODULE_DEPEND(ae, ether, 1, 1, 1); 183 MODULE_DEPEND(ae, miibus, 1, 1, 1); 184 185 /* 186 * Tunables. 187 */ 188 static int msi_disable = 0; 189 TUNABLE_INT("hw.ae.msi_disable", &msi_disable); 190 191 #define AE_READ_4(sc, reg) \ 192 bus_read_4((sc)->mem[0], (reg)) 193 #define AE_READ_2(sc, reg) \ 194 bus_read_2((sc)->mem[0], (reg)) 195 #define AE_READ_1(sc, reg) \ 196 bus_read_1((sc)->mem[0], (reg)) 197 #define AE_WRITE_4(sc, reg, val) \ 198 bus_write_4((sc)->mem[0], (reg), (val)) 199 #define AE_WRITE_2(sc, reg, val) \ 200 bus_write_2((sc)->mem[0], (reg), (val)) 201 #define AE_WRITE_1(sc, reg, val) \ 202 bus_write_1((sc)->mem[0], (reg), (val)) 203 #define AE_PHY_READ(sc, reg) \ 204 ae_miibus_readreg(sc->dev, 0, reg) 205 #define AE_PHY_WRITE(sc, reg, val) \ 206 ae_miibus_writereg(sc->dev, 0, reg, val) 207 #define AE_CHECK_EADDR_VALID(eaddr) \ 208 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 209 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 210 #define AE_RXD_VLAN(vtag) \ 211 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 212 #define AE_TXD_VLAN(vtag) \ 213 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 214 215 static int 216 ae_probe(device_t dev) 217 { 218 uint16_t deviceid, vendorid; 219 int i; 220 221 vendorid = pci_get_vendor(dev); 222 deviceid = pci_get_device(dev); 223 224 /* 225 * Search through the list of supported devs for matching one. 226 */ 227 for (i = 0; i < AE_DEVS_COUNT; i++) { 228 if (vendorid == ae_devs[i].vendorid && 229 deviceid == ae_devs[i].deviceid) { 230 device_set_desc(dev, ae_devs[i].name); 231 return (BUS_PROBE_DEFAULT); 232 } 233 } 234 return (ENXIO); 235 } 236 237 static int 238 ae_attach(device_t dev) 239 { 240 ae_softc_t *sc; 241 if_t ifp; 242 uint8_t chiprev; 243 uint32_t pcirev; 244 int nmsi, pmc; 245 int error; 246 247 sc = device_get_softc(dev); /* Automatically allocated and zeroed 248 on attach. */ 249 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 250 sc->dev = dev; 251 252 /* 253 * Initialize mutexes and tasks. 254 */ 255 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); 256 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0); 257 TASK_INIT(&sc->int_task, 0, ae_int_task, sc); 258 TASK_INIT(&sc->link_task, 0, ae_link_task, sc); 259 260 pci_enable_busmaster(dev); /* Enable bus mastering. */ 261 262 sc->spec_mem = ae_res_spec_mem; 263 264 /* 265 * Allocate memory-mapped registers. 266 */ 267 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem); 268 if (error != 0) { 269 device_printf(dev, "could not allocate memory resources.\n"); 270 sc->spec_mem = NULL; 271 goto fail; 272 } 273 274 /* 275 * Retrieve PCI and chip revisions. 276 */ 277 pcirev = pci_get_revid(dev); 278 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 279 AE_MASTER_REVNUM_MASK; 280 if (bootverbose) { 281 device_printf(dev, "pci device revision: %#04x\n", pcirev); 282 device_printf(dev, "chip id: %#02x\n", chiprev); 283 } 284 nmsi = pci_msi_count(dev); 285 if (bootverbose) 286 device_printf(dev, "MSI count: %d.\n", nmsi); 287 288 /* 289 * Allocate interrupt resources. 290 */ 291 if (msi_disable == 0 && nmsi == 1) { 292 error = pci_alloc_msi(dev, &nmsi); 293 if (error == 0) { 294 device_printf(dev, "Using MSI messages.\n"); 295 sc->spec_irq = ae_res_spec_msi; 296 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 297 if (error != 0) { 298 device_printf(dev, "MSI allocation failed.\n"); 299 sc->spec_irq = NULL; 300 pci_release_msi(dev); 301 } else { 302 sc->flags |= AE_FLAG_MSI; 303 } 304 } 305 } 306 if (sc->spec_irq == NULL) { 307 sc->spec_irq = ae_res_spec_irq; 308 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq); 309 if (error != 0) { 310 device_printf(dev, "could not allocate IRQ resources.\n"); 311 sc->spec_irq = NULL; 312 goto fail; 313 } 314 } 315 316 ae_init_tunables(sc); 317 318 ae_phy_reset(sc); /* Reset PHY. */ 319 error = ae_reset(sc); /* Reset the controller itself. */ 320 if (error != 0) 321 goto fail; 322 323 ae_pcie_init(sc); 324 325 ae_retrieve_address(sc); /* Load MAC address. */ 326 327 error = ae_alloc_rings(sc); /* Allocate ring buffers. */ 328 if (error != 0) 329 goto fail; 330 331 ifp = sc->ifp = if_alloc(IFT_ETHER); 332 if (ifp == NULL) { 333 device_printf(dev, "could not allocate ifnet structure.\n"); 334 error = ENXIO; 335 goto fail; 336 } 337 338 if_setsoftc(ifp, sc); 339 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 340 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 341 if_setioctlfn(ifp, ae_ioctl); 342 if_setstartfn(ifp, ae_start); 343 if_setinitfn(ifp, ae_init); 344 if_setcapabilities(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING); 345 if_sethwassist(ifp, 0); 346 if_setsendqlen(ifp, ifqmaxlen); 347 if_setsendqready(ifp); 348 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 349 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 350 sc->flags |= AE_FLAG_PMG; 351 } 352 if_setcapenable(ifp, if_getcapabilities(ifp)); 353 354 /* 355 * Configure and attach MII bus. 356 */ 357 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange, 358 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT, 359 MII_OFFSET_ANY, 0); 360 if (error != 0) { 361 device_printf(dev, "attaching PHYs failed\n"); 362 goto fail; 363 } 364 365 ether_ifattach(ifp, sc->eaddr); 366 /* Tell the upper layer(s) we support long frames. */ 367 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 368 369 /* 370 * Create and run all helper tasks. 371 */ 372 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK, 373 taskqueue_thread_enqueue, &sc->tq); 374 if (sc->tq == NULL) { 375 device_printf(dev, "could not create taskqueue.\n"); 376 ether_ifdetach(ifp); 377 error = ENXIO; 378 goto fail; 379 } 380 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", 381 device_get_nameunit(sc->dev)); 382 383 /* 384 * Configure interrupt handlers. 385 */ 386 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE, 387 ae_intr, NULL, sc, &sc->intrhand); 388 if (error != 0) { 389 device_printf(dev, "could not set up interrupt handler.\n"); 390 taskqueue_free(sc->tq); 391 sc->tq = NULL; 392 ether_ifdetach(ifp); 393 goto fail; 394 } 395 396 fail: 397 if (error != 0) 398 ae_detach(dev); 399 400 return (error); 401 } 402 403 #define AE_SYSCTL(stx, parent, name, desc, ptr) \ 404 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc) 405 406 static void 407 ae_init_tunables(ae_softc_t *sc) 408 { 409 struct sysctl_ctx_list *ctx; 410 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 411 struct ae_stats *ae_stats; 412 413 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 414 ae_stats = &sc->stats; 415 416 ctx = device_get_sysctl_ctx(sc->dev); 417 root = device_get_sysctl_tree(sc->dev); 418 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 419 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ae statistics"); 420 421 /* 422 * Receiver statistcics. 423 */ 424 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 425 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast", 427 "broadcast frames", &ae_stats->rx_bcast); 428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast", 429 "multicast frames", &ae_stats->rx_mcast); 430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause", 431 "PAUSE frames", &ae_stats->rx_pause); 432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control", 433 "control frames", &ae_stats->rx_ctrl); 434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors", 435 "frames with CRC errors", &ae_stats->rx_crcerr); 436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors", 437 "frames with invalid opcode", &ae_stats->rx_codeerr); 438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt", 439 "runt frames", &ae_stats->rx_runt); 440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag", 441 "fragmented frames", &ae_stats->rx_frag); 442 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors", 443 "frames with alignment errors", &ae_stats->rx_align); 444 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated", 445 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc); 446 447 /* 448 * Receiver statistcics. 449 */ 450 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 451 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast", 453 "broadcast frames", &ae_stats->tx_bcast); 454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast", 455 "multicast frames", &ae_stats->tx_mcast); 456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause", 457 "PAUSE frames", &ae_stats->tx_pause); 458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control", 459 "control frames", &ae_stats->tx_ctrl); 460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers", 461 "deferrals occuried", &ae_stats->tx_defer); 462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers", 463 "excessive deferrals occuried", &ae_stats->tx_excdefer); 464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols", 465 "single collisions occuried", &ae_stats->tx_singlecol); 466 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols", 467 "multiple collisions occuried", &ae_stats->tx_multicol); 468 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols", 469 "late collisions occuried", &ae_stats->tx_latecol); 470 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts", 471 "transmit aborts due collisions", &ae_stats->tx_abortcol); 472 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns", 473 "Tx FIFO underruns", &ae_stats->tx_underrun); 474 } 475 476 static void 477 ae_pcie_init(ae_softc_t *sc) 478 { 479 480 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT); 481 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT); 482 } 483 484 static void 485 ae_phy_reset(ae_softc_t *sc) 486 { 487 488 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 489 DELAY(1000); /* XXX: pause(9) ? */ 490 } 491 492 static int 493 ae_reset(ae_softc_t *sc) 494 { 495 int i; 496 497 /* 498 * Issue a soft reset. 499 */ 500 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 501 bus_barrier(sc->mem[0], AE_MASTER_REG, 4, 502 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 503 504 /* 505 * Wait for reset to complete. 506 */ 507 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 508 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 509 break; 510 DELAY(10); 511 } 512 if (i == AE_RESET_TIMEOUT) { 513 device_printf(sc->dev, "reset timeout.\n"); 514 return (ENXIO); 515 } 516 517 /* 518 * Wait for everything to enter idle state. 519 */ 520 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 521 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 522 break; 523 DELAY(100); 524 } 525 if (i == AE_IDLE_TIMEOUT) { 526 device_printf(sc->dev, "could not enter idle state.\n"); 527 return (ENXIO); 528 } 529 return (0); 530 } 531 532 static void 533 ae_init(void *arg) 534 { 535 ae_softc_t *sc; 536 537 sc = (ae_softc_t *)arg; 538 AE_LOCK(sc); 539 ae_init_locked(sc); 540 AE_UNLOCK(sc); 541 } 542 543 static void 544 ae_phy_init(ae_softc_t *sc) 545 { 546 547 /* 548 * Enable link status change interrupt. 549 * XXX magic numbers. 550 */ 551 #ifdef notyet 552 AE_PHY_WRITE(sc, 18, 0xc00); 553 #endif 554 } 555 556 static int 557 ae_init_locked(ae_softc_t *sc) 558 { 559 if_t ifp; 560 struct mii_data *mii; 561 uint8_t eaddr[ETHER_ADDR_LEN]; 562 uint32_t val; 563 bus_addr_t addr; 564 565 AE_LOCK_ASSERT(sc); 566 567 ifp = sc->ifp; 568 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 569 return (0); 570 mii = device_get_softc(sc->miibus); 571 572 ae_stop(sc); 573 ae_reset(sc); 574 ae_pcie_init(sc); /* Initialize PCIE stuff. */ 575 ae_phy_init(sc); 576 ae_powersave_disable(sc); 577 578 /* 579 * Clear and disable interrupts. 580 */ 581 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 582 583 /* 584 * Set the MAC address. 585 */ 586 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 587 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 588 AE_WRITE_4(sc, AE_EADDR0_REG, val); 589 val = eaddr[0] << 8 | eaddr[1]; 590 AE_WRITE_4(sc, AE_EADDR1_REG, val); 591 592 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING); 593 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT); 594 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4); 595 /* 596 * Set ring buffers base addresses. 597 */ 598 addr = sc->dma_rxd_busaddr; 599 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 600 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 601 addr = sc->dma_txd_busaddr; 602 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 603 addr = sc->dma_txs_busaddr; 604 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 605 606 /* 607 * Configure ring buffers sizes. 608 */ 609 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 610 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 611 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 612 613 /* 614 * Configure interframe gap parameters. 615 */ 616 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 617 AE_IFG_TXIPG_MASK) | 618 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 619 AE_IFG_RXIPG_MASK) | 620 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 621 AE_IFG_IPGR1_MASK) | 622 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 623 AE_IFG_IPGR2_MASK); 624 AE_WRITE_4(sc, AE_IFG_REG, val); 625 626 /* 627 * Configure half-duplex operation. 628 */ 629 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 630 AE_HDPX_LCOL_MASK) | 631 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 632 AE_HDPX_RETRY_MASK) | 633 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 634 AE_HDPX_ABEBT_MASK) | 635 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 636 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 637 AE_WRITE_4(sc, AE_HDPX_REG, val); 638 639 /* 640 * Configure interrupt moderate timer. 641 */ 642 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 643 val = AE_READ_4(sc, AE_MASTER_REG); 644 val |= AE_MASTER_IMT_EN; 645 AE_WRITE_4(sc, AE_MASTER_REG, val); 646 647 /* 648 * Configure interrupt clearing timer. 649 */ 650 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 651 652 /* 653 * Configure MTU. 654 */ 655 val = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 656 ETHER_CRC_LEN; 657 AE_WRITE_2(sc, AE_MTU_REG, val); 658 659 /* 660 * Configure cut-through threshold. 661 */ 662 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 663 664 /* 665 * Configure flow control. 666 */ 667 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 668 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 669 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 670 (AE_RXD_COUNT_DEFAULT / 12)); 671 672 /* 673 * Init mailboxes. 674 */ 675 sc->txd_cur = sc->rxd_cur = 0; 676 sc->txs_ack = sc->txd_ack = 0; 677 sc->rxd_cur = 0; 678 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 679 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 680 681 sc->tx_inproc = 0; /* Number of packets the chip processes now. */ 682 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 683 684 /* 685 * Enable DMA. 686 */ 687 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 688 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 689 690 /* 691 * Check if everything is OK. 692 */ 693 val = AE_READ_4(sc, AE_ISR_REG); 694 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 695 device_printf(sc->dev, "Initialization failed.\n"); 696 return (ENXIO); 697 } 698 699 /* 700 * Clear interrupt status. 701 */ 702 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 703 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 704 705 /* 706 * Enable interrupts. 707 */ 708 val = AE_READ_4(sc, AE_MASTER_REG); 709 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 710 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 711 712 /* 713 * Disable WOL. 714 */ 715 AE_WRITE_4(sc, AE_WOL_REG, 0); 716 717 /* 718 * Configure MAC. 719 */ 720 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 721 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 722 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 723 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 724 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 725 AE_MAC_PREAMBLE_MASK); 726 AE_WRITE_4(sc, AE_MAC_REG, val); 727 728 /* 729 * Configure Rx MAC. 730 */ 731 ae_rxfilter(sc); 732 ae_rxvlan(sc); 733 734 /* 735 * Enable Tx/Rx. 736 */ 737 val = AE_READ_4(sc, AE_MAC_REG); 738 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 739 740 sc->flags &= ~AE_FLAG_LINK; 741 mii_mediachg(mii); /* Switch to the current media. */ 742 743 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 744 745 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 746 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 747 748 #ifdef AE_DEBUG 749 device_printf(sc->dev, "Initialization complete.\n"); 750 #endif 751 752 return (0); 753 } 754 755 static int 756 ae_detach(device_t dev) 757 { 758 struct ae_softc *sc; 759 if_t ifp; 760 761 sc = device_get_softc(dev); 762 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 763 ifp = sc->ifp; 764 if (device_is_attached(dev)) { 765 AE_LOCK(sc); 766 sc->flags |= AE_FLAG_DETACH; 767 ae_stop(sc); 768 AE_UNLOCK(sc); 769 callout_drain(&sc->tick_ch); 770 taskqueue_drain(sc->tq, &sc->int_task); 771 taskqueue_drain(taskqueue_swi, &sc->link_task); 772 ether_ifdetach(ifp); 773 } 774 if (sc->tq != NULL) { 775 taskqueue_drain(sc->tq, &sc->int_task); 776 taskqueue_free(sc->tq); 777 sc->tq = NULL; 778 } 779 if (sc->miibus != NULL) { 780 device_delete_child(dev, sc->miibus); 781 sc->miibus = NULL; 782 } 783 bus_generic_detach(sc->dev); 784 ae_dma_free(sc); 785 if (sc->intrhand != NULL) { 786 bus_teardown_intr(dev, sc->irq[0], sc->intrhand); 787 sc->intrhand = NULL; 788 } 789 if (ifp != NULL) { 790 if_free(ifp); 791 sc->ifp = NULL; 792 } 793 if (sc->spec_irq != NULL) 794 bus_release_resources(dev, sc->spec_irq, sc->irq); 795 if (sc->spec_mem != NULL) 796 bus_release_resources(dev, sc->spec_mem, sc->mem); 797 if ((sc->flags & AE_FLAG_MSI) != 0) 798 pci_release_msi(dev); 799 mtx_destroy(&sc->mtx); 800 801 return (0); 802 } 803 804 static int 805 ae_miibus_readreg(device_t dev, int phy, int reg) 806 { 807 ae_softc_t *sc; 808 uint32_t val; 809 int i; 810 811 sc = device_get_softc(dev); 812 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 813 814 /* 815 * Locking is done in upper layers. 816 */ 817 818 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 819 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 820 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 821 AE_WRITE_4(sc, AE_MDIO_REG, val); 822 823 /* 824 * Wait for operation to complete. 825 */ 826 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 827 DELAY(2); 828 val = AE_READ_4(sc, AE_MDIO_REG); 829 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 830 break; 831 } 832 if (i == AE_MDIO_TIMEOUT) { 833 device_printf(sc->dev, "phy read timeout: %d.\n", reg); 834 return (0); 835 } 836 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 837 } 838 839 static int 840 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 841 { 842 ae_softc_t *sc; 843 uint32_t aereg; 844 int i; 845 846 sc = device_get_softc(dev); 847 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 848 849 /* 850 * Locking is done in upper layers. 851 */ 852 853 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 854 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 855 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 856 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 857 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 858 859 /* 860 * Wait for operation to complete. 861 */ 862 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 863 DELAY(2); 864 aereg = AE_READ_4(sc, AE_MDIO_REG); 865 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 866 break; 867 } 868 if (i == AE_MDIO_TIMEOUT) { 869 device_printf(sc->dev, "phy write timeout: %d.\n", reg); 870 } 871 return (0); 872 } 873 874 static void 875 ae_miibus_statchg(device_t dev) 876 { 877 ae_softc_t *sc; 878 879 sc = device_get_softc(dev); 880 taskqueue_enqueue(taskqueue_swi, &sc->link_task); 881 } 882 883 static void 884 ae_mediastatus(if_t ifp, struct ifmediareq *ifmr) 885 { 886 ae_softc_t *sc; 887 struct mii_data *mii; 888 889 sc = if_getsoftc(ifp); 890 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 891 892 AE_LOCK(sc); 893 mii = device_get_softc(sc->miibus); 894 mii_pollstat(mii); 895 ifmr->ifm_status = mii->mii_media_status; 896 ifmr->ifm_active = mii->mii_media_active; 897 AE_UNLOCK(sc); 898 } 899 900 static int 901 ae_mediachange(if_t ifp) 902 { 903 ae_softc_t *sc; 904 struct mii_data *mii; 905 struct mii_softc *mii_sc; 906 int error; 907 908 /* XXX: check IFF_UP ?? */ 909 sc = if_getsoftc(ifp); 910 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 911 AE_LOCK(sc); 912 mii = device_get_softc(sc->miibus); 913 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list) 914 PHY_RESET(mii_sc); 915 error = mii_mediachg(mii); 916 AE_UNLOCK(sc); 917 918 return (error); 919 } 920 921 static int 922 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc) 923 { 924 int error; 925 uint32_t val; 926 927 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__)); 928 929 /* 930 * Not sure why, but Linux does this. 931 */ 932 val = AE_READ_4(sc, AE_SPICTL_REG); 933 if ((val & AE_SPICTL_VPD_EN) != 0) { 934 val &= ~AE_SPICTL_VPD_EN; 935 AE_WRITE_4(sc, AE_SPICTL_REG, val); 936 } 937 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc); 938 return (error); 939 } 940 941 static int 942 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word) 943 { 944 uint32_t val; 945 int i; 946 947 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 948 949 /* 950 * VPD registers start at offset 0x100. Read them. 951 */ 952 val = 0x100 + reg * 4; 953 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 954 AE_VPD_CAP_ADDR_MASK); 955 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 956 DELAY(2000); 957 val = AE_READ_4(sc, AE_VPD_CAP_REG); 958 if ((val & AE_VPD_CAP_DONE) != 0) 959 break; 960 } 961 if (i == AE_VPD_TIMEOUT) { 962 device_printf(sc->dev, "timeout reading VPD register %d.\n", 963 reg); 964 return (ETIMEDOUT); 965 } 966 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 967 return (0); 968 } 969 970 static int 971 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr) 972 { 973 uint32_t word, reg, val; 974 int error; 975 int found; 976 int vpdc; 977 int i; 978 979 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 980 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__)); 981 982 /* 983 * Check for EEPROM. 984 */ 985 error = ae_check_eeprom_present(sc, &vpdc); 986 if (error != 0) 987 return (error); 988 989 /* 990 * Read the VPD configuration space. 991 * Each register is prefixed with signature, 992 * so we can check if it is valid. 993 */ 994 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 995 error = ae_vpd_read_word(sc, i, &word); 996 if (error != 0) 997 break; 998 999 /* 1000 * Check signature. 1001 */ 1002 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1003 break; 1004 reg = word >> AE_VPD_REG_SHIFT; 1005 i++; /* Move to the next word. */ 1006 1007 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1008 continue; 1009 1010 error = ae_vpd_read_word(sc, i, &val); 1011 if (error != 0) 1012 break; 1013 if (reg == AE_EADDR0_REG) 1014 eaddr[0] = val; 1015 else 1016 eaddr[1] = val; 1017 found++; 1018 } 1019 1020 if (found < 2) 1021 return (ENOENT); 1022 1023 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1024 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1025 if (bootverbose) 1026 device_printf(sc->dev, 1027 "VPD ethernet address registers are invalid.\n"); 1028 return (EINVAL); 1029 } 1030 return (0); 1031 } 1032 1033 static int 1034 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr) 1035 { 1036 1037 /* 1038 * BIOS is supposed to set this. 1039 */ 1040 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1041 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1042 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1043 1044 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1045 if (bootverbose) 1046 device_printf(sc->dev, 1047 "Ethernet address registers are invalid.\n"); 1048 return (EINVAL); 1049 } 1050 return (0); 1051 } 1052 1053 static void 1054 ae_retrieve_address(ae_softc_t *sc) 1055 { 1056 uint32_t eaddr[2] = {0, 0}; 1057 int error; 1058 1059 /* 1060 *Check for EEPROM. 1061 */ 1062 error = ae_get_vpd_eaddr(sc, eaddr); 1063 if (error != 0) 1064 error = ae_get_reg_eaddr(sc, eaddr); 1065 if (error != 0) { 1066 if (bootverbose) 1067 device_printf(sc->dev, 1068 "Generating random ethernet address.\n"); 1069 eaddr[0] = arc4random(); 1070 1071 /* 1072 * Set OUI to ASUSTek COMPUTER INC. 1073 */ 1074 sc->eaddr[0] = 0x02; /* U/L bit set. */ 1075 sc->eaddr[1] = 0x1f; 1076 sc->eaddr[2] = 0xc6; 1077 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1078 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1079 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1080 } else { 1081 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff; 1082 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff; 1083 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff; 1084 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff; 1085 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff; 1086 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff; 1087 } 1088 } 1089 1090 static void 1091 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1092 { 1093 bus_addr_t *addr = arg; 1094 1095 if (error != 0) 1096 return; 1097 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__, 1098 nsegs)); 1099 *addr = segs[0].ds_addr; 1100 } 1101 1102 static int 1103 ae_alloc_rings(ae_softc_t *sc) 1104 { 1105 bus_addr_t busaddr; 1106 int error; 1107 1108 /* 1109 * Create parent DMA tag. 1110 */ 1111 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1112 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 1113 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1114 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1115 &sc->dma_parent_tag); 1116 if (error != 0) { 1117 device_printf(sc->dev, "could not creare parent DMA tag.\n"); 1118 return (error); 1119 } 1120 1121 /* 1122 * Create DMA tag for TxD. 1123 */ 1124 error = bus_dma_tag_create(sc->dma_parent_tag, 1125 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1126 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1, 1127 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL, 1128 &sc->dma_txd_tag); 1129 if (error != 0) { 1130 device_printf(sc->dev, "could not creare TxD DMA tag.\n"); 1131 return (error); 1132 } 1133 1134 /* 1135 * Create DMA tag for TxS. 1136 */ 1137 error = bus_dma_tag_create(sc->dma_parent_tag, 1138 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1139 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1, 1140 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL, 1141 &sc->dma_txs_tag); 1142 if (error != 0) { 1143 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1144 return (error); 1145 } 1146 1147 /* 1148 * Create DMA tag for RxD. 1149 */ 1150 error = bus_dma_tag_create(sc->dma_parent_tag, 1151 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1152 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1, 1153 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL, 1154 &sc->dma_rxd_tag); 1155 if (error != 0) { 1156 device_printf(sc->dev, "could not creare TxS DMA tag.\n"); 1157 return (error); 1158 } 1159 1160 /* 1161 * Allocate TxD DMA memory. 1162 */ 1163 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base, 1164 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1165 &sc->dma_txd_map); 1166 if (error != 0) { 1167 device_printf(sc->dev, 1168 "could not allocate DMA memory for TxD ring.\n"); 1169 return (error); 1170 } 1171 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base, 1172 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1173 if (error != 0 || busaddr == 0) { 1174 device_printf(sc->dev, 1175 "could not load DMA map for TxD ring.\n"); 1176 return (error); 1177 } 1178 sc->dma_txd_busaddr = busaddr; 1179 1180 /* 1181 * Allocate TxS DMA memory. 1182 */ 1183 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base, 1184 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1185 &sc->dma_txs_map); 1186 if (error != 0) { 1187 device_printf(sc->dev, 1188 "could not allocate DMA memory for TxS ring.\n"); 1189 return (error); 1190 } 1191 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base, 1192 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1193 if (error != 0 || busaddr == 0) { 1194 device_printf(sc->dev, 1195 "could not load DMA map for TxS ring.\n"); 1196 return (error); 1197 } 1198 sc->dma_txs_busaddr = busaddr; 1199 1200 /* 1201 * Allocate RxD DMA memory. 1202 */ 1203 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma, 1204 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1205 &sc->dma_rxd_map); 1206 if (error != 0) { 1207 device_printf(sc->dev, 1208 "could not allocate DMA memory for RxD ring.\n"); 1209 return (error); 1210 } 1211 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map, 1212 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1213 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT); 1214 if (error != 0 || busaddr == 0) { 1215 device_printf(sc->dev, 1216 "could not load DMA map for RxD ring.\n"); 1217 return (error); 1218 } 1219 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING; 1220 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING); 1221 1222 return (0); 1223 } 1224 1225 static void 1226 ae_dma_free(ae_softc_t *sc) 1227 { 1228 1229 if (sc->dma_txd_tag != NULL) { 1230 if (sc->dma_txd_busaddr != 0) 1231 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1232 if (sc->txd_base != NULL) 1233 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1234 sc->dma_txd_map); 1235 bus_dma_tag_destroy(sc->dma_txd_tag); 1236 sc->dma_txd_tag = NULL; 1237 sc->txd_base = NULL; 1238 sc->dma_txd_busaddr = 0; 1239 } 1240 if (sc->dma_txs_tag != NULL) { 1241 if (sc->dma_txs_busaddr != 0) 1242 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1243 if (sc->txs_base != NULL) 1244 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1245 sc->dma_txs_map); 1246 bus_dma_tag_destroy(sc->dma_txs_tag); 1247 sc->dma_txs_tag = NULL; 1248 sc->txs_base = NULL; 1249 sc->dma_txs_busaddr = 0; 1250 } 1251 if (sc->dma_rxd_tag != NULL) { 1252 if (sc->dma_rxd_busaddr != 0) 1253 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1254 if (sc->rxd_base_dma != NULL) 1255 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma, 1256 sc->dma_rxd_map); 1257 bus_dma_tag_destroy(sc->dma_rxd_tag); 1258 sc->dma_rxd_tag = NULL; 1259 sc->rxd_base_dma = NULL; 1260 sc->dma_rxd_busaddr = 0; 1261 } 1262 if (sc->dma_parent_tag != NULL) { 1263 bus_dma_tag_destroy(sc->dma_parent_tag); 1264 sc->dma_parent_tag = NULL; 1265 } 1266 } 1267 1268 static int 1269 ae_shutdown(device_t dev) 1270 { 1271 ae_softc_t *sc; 1272 int error; 1273 1274 sc = device_get_softc(dev); 1275 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__)); 1276 1277 error = ae_suspend(dev); 1278 AE_LOCK(sc); 1279 ae_powersave_enable(sc); 1280 AE_UNLOCK(sc); 1281 return (error); 1282 } 1283 1284 static void 1285 ae_powersave_disable(ae_softc_t *sc) 1286 { 1287 uint32_t val; 1288 1289 AE_LOCK_ASSERT(sc); 1290 1291 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1292 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1293 if (val & AE_PHY_DBG_POWERSAVE) { 1294 val &= ~AE_PHY_DBG_POWERSAVE; 1295 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1296 DELAY(1000); 1297 } 1298 } 1299 1300 static void 1301 ae_powersave_enable(ae_softc_t *sc) 1302 { 1303 uint32_t val; 1304 1305 AE_LOCK_ASSERT(sc); 1306 1307 /* 1308 * XXX magic numbers. 1309 */ 1310 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1311 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1312 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1313 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1314 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1315 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1316 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1317 } 1318 1319 static void 1320 ae_pm_init(ae_softc_t *sc) 1321 { 1322 if_t ifp; 1323 uint32_t val; 1324 uint16_t pmstat; 1325 struct mii_data *mii; 1326 int pmc; 1327 1328 AE_LOCK_ASSERT(sc); 1329 1330 ifp = sc->ifp; 1331 if ((sc->flags & AE_FLAG_PMG) == 0) { 1332 /* Disable WOL entirely. */ 1333 AE_WRITE_4(sc, AE_WOL_REG, 0); 1334 return; 1335 } 1336 1337 /* 1338 * Configure WOL if enabled. 1339 */ 1340 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1341 mii = device_get_softc(sc->miibus); 1342 mii_pollstat(mii); 1343 if ((mii->mii_media_status & IFM_AVALID) != 0 && 1344 (mii->mii_media_status & IFM_ACTIVE) != 0) { 1345 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \ 1346 AE_WOL_MAGIC_PME); 1347 1348 /* 1349 * Configure MAC. 1350 */ 1351 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \ 1352 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \ 1353 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \ 1354 AE_HALFBUF_MASK) | \ 1355 ((AE_MAC_PREAMBLE_DEFAULT << \ 1356 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \ 1357 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN; 1358 if ((IFM_OPTIONS(mii->mii_media_active) & \ 1359 IFM_FDX) != 0) 1360 val |= AE_MAC_FULL_DUPLEX; 1361 AE_WRITE_4(sc, AE_MAC_REG, val); 1362 1363 } else { /* No link. */ 1364 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \ 1365 AE_WOL_LNKCHG_PME); 1366 AE_WRITE_4(sc, AE_MAC_REG, 0); 1367 } 1368 } else { 1369 ae_powersave_enable(sc); 1370 } 1371 1372 /* 1373 * PCIE hacks. Magic numbers. 1374 */ 1375 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG); 1376 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET; 1377 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val); 1378 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG); 1379 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK; 1380 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val); 1381 1382 /* 1383 * Configure PME. 1384 */ 1385 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) { 1386 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2); 1387 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1388 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1389 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1390 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1391 } 1392 } 1393 1394 static int 1395 ae_suspend(device_t dev) 1396 { 1397 ae_softc_t *sc; 1398 1399 sc = device_get_softc(dev); 1400 1401 AE_LOCK(sc); 1402 ae_stop(sc); 1403 ae_pm_init(sc); 1404 AE_UNLOCK(sc); 1405 1406 return (0); 1407 } 1408 1409 static int 1410 ae_resume(device_t dev) 1411 { 1412 ae_softc_t *sc; 1413 1414 sc = device_get_softc(dev); 1415 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1416 1417 AE_LOCK(sc); 1418 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1419 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 1420 ae_init_locked(sc); 1421 AE_UNLOCK(sc); 1422 1423 return (0); 1424 } 1425 1426 static unsigned int 1427 ae_tx_avail_size(ae_softc_t *sc) 1428 { 1429 unsigned int avail; 1430 1431 if (sc->txd_cur >= sc->txd_ack) 1432 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1433 else 1434 avail = sc->txd_ack - sc->txd_cur; 1435 1436 return (avail); 1437 } 1438 1439 static int 1440 ae_encap(ae_softc_t *sc, struct mbuf **m_head) 1441 { 1442 struct mbuf *m0; 1443 ae_txd_t *hdr; 1444 unsigned int to_end; 1445 uint16_t len; 1446 1447 AE_LOCK_ASSERT(sc); 1448 1449 m0 = *m_head; 1450 len = m0->m_pkthdr.len; 1451 1452 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 || 1453 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) { 1454 #ifdef AE_DEBUG 1455 if_printf(sc->ifp, "No free Tx available.\n"); 1456 #endif 1457 return ENOBUFS; 1458 } 1459 1460 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur); 1461 bzero(hdr, sizeof(*hdr)); 1462 /* Skip header size. */ 1463 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT; 1464 /* Space available to the end of the ring */ 1465 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1466 if (to_end >= len) { 1467 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1468 } else { 1469 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1470 sc->txd_cur)); 1471 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1472 } 1473 1474 /* 1475 * Set TxD flags and parameters. 1476 */ 1477 if ((m0->m_flags & M_VLANTAG) != 0) { 1478 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag)); 1479 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1480 } else { 1481 hdr->len = htole16(len); 1482 } 1483 1484 /* 1485 * Set current TxD position and round up to a 4-byte boundary. 1486 */ 1487 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1488 if (sc->txd_cur == sc->txd_ack) 1489 sc->flags &= ~AE_FLAG_TXAVAIL; 1490 #ifdef AE_DEBUG 1491 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1492 #endif 1493 1494 /* 1495 * Update TxS position and check if there are empty TxS available. 1496 */ 1497 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1498 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1499 if (sc->txs_cur == sc->txs_ack) 1500 sc->flags &= ~AE_FLAG_TXAVAIL; 1501 1502 /* 1503 * Synchronize DMA memory. 1504 */ 1505 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD | 1506 BUS_DMASYNC_PREWRITE); 1507 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1508 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1509 1510 return (0); 1511 } 1512 1513 static void 1514 ae_start(if_t ifp) 1515 { 1516 ae_softc_t *sc; 1517 1518 sc = if_getsoftc(ifp); 1519 AE_LOCK(sc); 1520 ae_start_locked(ifp); 1521 AE_UNLOCK(sc); 1522 } 1523 1524 static void 1525 ae_start_locked(if_t ifp) 1526 { 1527 ae_softc_t *sc; 1528 unsigned int count; 1529 struct mbuf *m0; 1530 int error; 1531 1532 sc = if_getsoftc(ifp); 1533 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1534 AE_LOCK_ASSERT(sc); 1535 1536 #ifdef AE_DEBUG 1537 if_printf(ifp, "Start called.\n"); 1538 #endif 1539 1540 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1541 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0) 1542 return; 1543 1544 count = 0; 1545 while (!if_sendq_empty(ifp)) { 1546 m0 = if_dequeue(ifp); 1547 if (m0 == NULL) 1548 break; /* Nothing to do. */ 1549 1550 error = ae_encap(sc, &m0); 1551 if (error != 0) { 1552 if (m0 != NULL) { 1553 if_sendq_prepend(ifp, m0); 1554 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1555 #ifdef AE_DEBUG 1556 if_printf(ifp, "Setting OACTIVE.\n"); 1557 #endif 1558 } 1559 break; 1560 } 1561 count++; 1562 sc->tx_inproc++; 1563 1564 /* Bounce a copy of the frame to BPF. */ 1565 ETHER_BPF_MTAP(ifp, m0); 1566 1567 m_freem(m0); 1568 } 1569 1570 if (count > 0) { /* Something was dequeued. */ 1571 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1572 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1573 #ifdef AE_DEBUG 1574 if_printf(ifp, "%d packets dequeued.\n", count); 1575 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1576 #endif 1577 } 1578 } 1579 1580 static void 1581 ae_link_task(void *arg, int pending) 1582 { 1583 ae_softc_t *sc; 1584 struct mii_data *mii; 1585 if_t ifp; 1586 uint32_t val; 1587 1588 sc = (ae_softc_t *)arg; 1589 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1590 AE_LOCK(sc); 1591 1592 ifp = sc->ifp; 1593 mii = device_get_softc(sc->miibus); 1594 if (mii == NULL || ifp == NULL || 1595 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1596 AE_UNLOCK(sc); /* XXX: could happen? */ 1597 return; 1598 } 1599 1600 sc->flags &= ~AE_FLAG_LINK; 1601 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 1602 (IFM_AVALID | IFM_ACTIVE)) { 1603 switch(IFM_SUBTYPE(mii->mii_media_active)) { 1604 case IFM_10_T: 1605 case IFM_100_TX: 1606 sc->flags |= AE_FLAG_LINK; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 /* 1614 * Stop Rx/Tx MACs. 1615 */ 1616 ae_stop_rxmac(sc); 1617 ae_stop_txmac(sc); 1618 1619 if ((sc->flags & AE_FLAG_LINK) != 0) { 1620 ae_mac_config(sc); 1621 1622 /* 1623 * Restart DMA engines. 1624 */ 1625 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 1626 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 1627 1628 /* 1629 * Enable Rx and Tx MACs. 1630 */ 1631 val = AE_READ_4(sc, AE_MAC_REG); 1632 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 1633 AE_WRITE_4(sc, AE_MAC_REG, val); 1634 } 1635 AE_UNLOCK(sc); 1636 } 1637 1638 static void 1639 ae_stop_rxmac(ae_softc_t *sc) 1640 { 1641 uint32_t val; 1642 int i; 1643 1644 AE_LOCK_ASSERT(sc); 1645 1646 /* 1647 * Stop Rx MAC engine. 1648 */ 1649 val = AE_READ_4(sc, AE_MAC_REG); 1650 if ((val & AE_MAC_RX_EN) != 0) { 1651 val &= ~AE_MAC_RX_EN; 1652 AE_WRITE_4(sc, AE_MAC_REG, val); 1653 } 1654 1655 /* 1656 * Stop Rx DMA engine. 1657 */ 1658 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 1659 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 1660 1661 /* 1662 * Wait for IDLE state. 1663 */ 1664 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1665 val = AE_READ_4(sc, AE_IDLE_REG); 1666 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 1667 break; 1668 DELAY(100); 1669 } 1670 if (i == AE_IDLE_TIMEOUT) 1671 device_printf(sc->dev, "timed out while stopping Rx MAC.\n"); 1672 } 1673 1674 static void 1675 ae_stop_txmac(ae_softc_t *sc) 1676 { 1677 uint32_t val; 1678 int i; 1679 1680 AE_LOCK_ASSERT(sc); 1681 1682 /* 1683 * Stop Tx MAC engine. 1684 */ 1685 val = AE_READ_4(sc, AE_MAC_REG); 1686 if ((val & AE_MAC_TX_EN) != 0) { 1687 val &= ~AE_MAC_TX_EN; 1688 AE_WRITE_4(sc, AE_MAC_REG, val); 1689 } 1690 1691 /* 1692 * Stop Tx DMA engine. 1693 */ 1694 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 1695 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 1696 1697 /* 1698 * Wait for IDLE state. 1699 */ 1700 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1701 val = AE_READ_4(sc, AE_IDLE_REG); 1702 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 1703 break; 1704 DELAY(100); 1705 } 1706 if (i == AE_IDLE_TIMEOUT) 1707 device_printf(sc->dev, "timed out while stopping Tx MAC.\n"); 1708 } 1709 1710 static void 1711 ae_mac_config(ae_softc_t *sc) 1712 { 1713 struct mii_data *mii; 1714 uint32_t val; 1715 1716 AE_LOCK_ASSERT(sc); 1717 1718 mii = device_get_softc(sc->miibus); 1719 val = AE_READ_4(sc, AE_MAC_REG); 1720 val &= ~AE_MAC_FULL_DUPLEX; 1721 /* XXX disable AE_MAC_TX_FLOW_EN? */ 1722 1723 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 1724 val |= AE_MAC_FULL_DUPLEX; 1725 1726 AE_WRITE_4(sc, AE_MAC_REG, val); 1727 } 1728 1729 static int 1730 ae_intr(void *arg) 1731 { 1732 ae_softc_t *sc; 1733 uint32_t val; 1734 1735 sc = (ae_softc_t *)arg; 1736 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__)); 1737 1738 val = AE_READ_4(sc, AE_ISR_REG); 1739 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 1740 return (FILTER_STRAY); 1741 1742 /* Disable interrupts. */ 1743 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 1744 1745 /* Schedule interrupt processing. */ 1746 taskqueue_enqueue(sc->tq, &sc->int_task); 1747 1748 return (FILTER_HANDLED); 1749 } 1750 1751 static void 1752 ae_int_task(void *arg, int pending) 1753 { 1754 ae_softc_t *sc; 1755 if_t ifp; 1756 uint32_t val; 1757 1758 sc = (ae_softc_t *)arg; 1759 1760 AE_LOCK(sc); 1761 1762 ifp = sc->ifp; 1763 1764 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */ 1765 if (val == 0) { 1766 AE_UNLOCK(sc); 1767 return; 1768 } 1769 1770 /* 1771 * Clear interrupts and disable them. 1772 */ 1773 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 1774 1775 #ifdef AE_DEBUG 1776 if_printf(ifp, "Interrupt received: 0x%08x\n", val); 1777 #endif 1778 1779 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1780 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | 1781 AE_ISR_PHY_LINKDOWN)) != 0) { 1782 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1783 ae_init_locked(sc); 1784 AE_UNLOCK(sc); 1785 return; 1786 } 1787 if ((val & AE_ISR_TX_EVENT) != 0) 1788 ae_tx_intr(sc); 1789 if ((val & AE_ISR_RX_EVENT) != 0) 1790 ae_rx_intr(sc); 1791 /* 1792 * Re-enable interrupts. 1793 */ 1794 AE_WRITE_4(sc, AE_ISR_REG, 0); 1795 1796 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) { 1797 if (!if_sendq_empty(ifp)) 1798 ae_start_locked(ifp); 1799 } 1800 } 1801 1802 AE_UNLOCK(sc); 1803 } 1804 1805 static void 1806 ae_tx_intr(ae_softc_t *sc) 1807 { 1808 if_t ifp; 1809 ae_txd_t *txd; 1810 ae_txs_t *txs; 1811 uint16_t flags; 1812 1813 AE_LOCK_ASSERT(sc); 1814 1815 ifp = sc->ifp; 1816 1817 #ifdef AE_DEBUG 1818 if_printf(ifp, "Tx interrupt occuried.\n"); 1819 #endif 1820 1821 /* 1822 * Syncronize DMA buffers. 1823 */ 1824 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1825 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1826 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1827 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1828 1829 for (;;) { 1830 txs = sc->txs_base + sc->txs_ack; 1831 flags = le16toh(txs->flags); 1832 if ((flags & AE_TXS_UPDATE) == 0) 1833 break; 1834 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 1835 /* Update stats. */ 1836 ae_update_stats_tx(flags, &sc->stats); 1837 1838 /* 1839 * Update TxS position. 1840 */ 1841 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 1842 sc->flags |= AE_FLAG_TXAVAIL; 1843 1844 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack); 1845 if (txs->len != txd->len) 1846 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n", 1847 le16toh(txs->len), le16toh(txd->len)); 1848 1849 /* 1850 * Move txd ack and align on 4-byte boundary. 1851 */ 1852 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 1853 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1854 1855 if ((flags & AE_TXS_SUCCESS) != 0) 1856 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1857 else 1858 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1859 1860 sc->tx_inproc--; 1861 } 1862 1863 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) 1864 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1865 if (sc->tx_inproc < 0) { 1866 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 1867 sc->tx_inproc = 0; 1868 } 1869 1870 if (sc->tx_inproc == 0) 1871 sc->wd_timer = 0; /* Unarm watchdog. */ 1872 1873 /* 1874 * Syncronize DMA buffers. 1875 */ 1876 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, 1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, 1879 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1880 } 1881 1882 static void 1883 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd) 1884 { 1885 if_t ifp; 1886 struct mbuf *m; 1887 unsigned int size; 1888 uint16_t flags; 1889 1890 AE_LOCK_ASSERT(sc); 1891 1892 ifp = sc->ifp; 1893 flags = le16toh(rxd->flags); 1894 1895 #ifdef AE_DEBUG 1896 if_printf(ifp, "Rx interrupt occuried.\n"); 1897 #endif 1898 size = le16toh(rxd->len) - ETHER_CRC_LEN; 1899 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) { 1900 if_printf(ifp, "Runt frame received."); 1901 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1902 return; 1903 } 1904 1905 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 1906 if (m == NULL) { 1907 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1908 return; 1909 } 1910 1911 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 1912 (flags & AE_RXD_HAS_VLAN) != 0) { 1913 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan)); 1914 m->m_flags |= M_VLANTAG; 1915 } 1916 1917 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1918 /* 1919 * Pass it through. 1920 */ 1921 AE_UNLOCK(sc); 1922 if_input(ifp, m); 1923 AE_LOCK(sc); 1924 } 1925 1926 static void 1927 ae_rx_intr(ae_softc_t *sc) 1928 { 1929 ae_rxd_t *rxd; 1930 if_t ifp; 1931 uint16_t flags; 1932 int count; 1933 1934 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1935 1936 AE_LOCK_ASSERT(sc); 1937 1938 ifp = sc->ifp; 1939 1940 /* 1941 * Syncronize DMA buffers. 1942 */ 1943 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1944 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1945 1946 for (count = 0;; count++) { 1947 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur); 1948 flags = le16toh(rxd->flags); 1949 if ((flags & AE_RXD_UPDATE) == 0) 1950 break; 1951 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 1952 /* Update stats. */ 1953 ae_update_stats_rx(flags, &sc->stats); 1954 1955 /* 1956 * Update position index. 1957 */ 1958 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 1959 1960 if ((flags & AE_RXD_SUCCESS) != 0) 1961 ae_rxeof(sc, rxd); 1962 else 1963 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1964 } 1965 1966 if (count > 0) { 1967 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 1968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1969 /* 1970 * Update Rx index. 1971 */ 1972 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 1973 } 1974 } 1975 1976 static void 1977 ae_watchdog(ae_softc_t *sc) 1978 { 1979 if_t ifp; 1980 1981 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 1982 AE_LOCK_ASSERT(sc); 1983 ifp = sc->ifp; 1984 1985 if (sc->wd_timer == 0 || --sc->wd_timer != 0) 1986 return; /* Noting to do. */ 1987 1988 if ((sc->flags & AE_FLAG_LINK) == 0) 1989 if_printf(ifp, "watchdog timeout (missed link).\n"); 1990 else 1991 if_printf(ifp, "watchdog timeout - resetting.\n"); 1992 1993 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1994 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1995 ae_init_locked(sc); 1996 if (!if_sendq_empty(ifp)) 1997 ae_start_locked(ifp); 1998 } 1999 2000 static void 2001 ae_tick(void *arg) 2002 { 2003 ae_softc_t *sc; 2004 struct mii_data *mii; 2005 2006 sc = (ae_softc_t *)arg; 2007 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2008 AE_LOCK_ASSERT(sc); 2009 2010 mii = device_get_softc(sc->miibus); 2011 mii_tick(mii); 2012 ae_watchdog(sc); /* Watchdog check. */ 2013 callout_reset(&sc->tick_ch, hz, ae_tick, sc); 2014 } 2015 2016 static void 2017 ae_rxvlan(ae_softc_t *sc) 2018 { 2019 if_t ifp; 2020 uint32_t val; 2021 2022 AE_LOCK_ASSERT(sc); 2023 ifp = sc->ifp; 2024 val = AE_READ_4(sc, AE_MAC_REG); 2025 val &= ~AE_MAC_RMVLAN_EN; 2026 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2027 val |= AE_MAC_RMVLAN_EN; 2028 AE_WRITE_4(sc, AE_MAC_REG, val); 2029 } 2030 2031 static u_int 2032 ae_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2033 { 2034 uint32_t crc, *mchash = arg; 2035 2036 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2037 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2038 2039 return (1); 2040 } 2041 2042 static void 2043 ae_rxfilter(ae_softc_t *sc) 2044 { 2045 if_t ifp; 2046 uint32_t mchash[2]; 2047 uint32_t rxcfg; 2048 2049 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__)); 2050 2051 AE_LOCK_ASSERT(sc); 2052 2053 ifp = sc->ifp; 2054 2055 rxcfg = AE_READ_4(sc, AE_MAC_REG); 2056 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 2057 2058 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2059 rxcfg |= AE_MAC_BCAST_EN; 2060 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2061 rxcfg |= AE_MAC_PROMISC_EN; 2062 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2063 rxcfg |= AE_MAC_MCAST_EN; 2064 2065 /* 2066 * Wipe old settings. 2067 */ 2068 AE_WRITE_4(sc, AE_REG_MHT0, 0); 2069 AE_WRITE_4(sc, AE_REG_MHT1, 0); 2070 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2071 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 2072 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 2073 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2074 return; 2075 } 2076 2077 /* 2078 * Load multicast tables. 2079 */ 2080 bzero(mchash, sizeof(mchash)); 2081 if_foreach_llmaddr(ifp, ae_hash_maddr, &mchash); 2082 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 2083 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 2084 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 2085 } 2086 2087 static int 2088 ae_ioctl(if_t ifp, u_long cmd, caddr_t data) 2089 { 2090 struct ae_softc *sc; 2091 struct ifreq *ifr; 2092 struct mii_data *mii; 2093 int error, mask; 2094 2095 sc = if_getsoftc(ifp); 2096 ifr = (struct ifreq *)data; 2097 error = 0; 2098 2099 switch (cmd) { 2100 case SIOCSIFMTU: 2101 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) 2102 error = EINVAL; 2103 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2104 AE_LOCK(sc); 2105 if_setmtu(ifp, ifr->ifr_mtu); 2106 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2107 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2108 ae_init_locked(sc); 2109 } 2110 AE_UNLOCK(sc); 2111 } 2112 break; 2113 case SIOCSIFFLAGS: 2114 AE_LOCK(sc); 2115 if ((if_getflags(ifp) & IFF_UP) != 0) { 2116 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2117 if (((if_getflags(ifp) ^ sc->if_flags) 2118 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2119 ae_rxfilter(sc); 2120 } else { 2121 if ((sc->flags & AE_FLAG_DETACH) == 0) 2122 ae_init_locked(sc); 2123 } 2124 } else { 2125 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2126 ae_stop(sc); 2127 } 2128 sc->if_flags = if_getflags(ifp); 2129 AE_UNLOCK(sc); 2130 break; 2131 case SIOCADDMULTI: 2132 case SIOCDELMULTI: 2133 AE_LOCK(sc); 2134 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2135 ae_rxfilter(sc); 2136 AE_UNLOCK(sc); 2137 break; 2138 case SIOCSIFMEDIA: 2139 case SIOCGIFMEDIA: 2140 mii = device_get_softc(sc->miibus); 2141 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2142 break; 2143 case SIOCSIFCAP: 2144 AE_LOCK(sc); 2145 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2146 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2147 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2148 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2149 ae_rxvlan(sc); 2150 } 2151 VLAN_CAPABILITIES(ifp); 2152 AE_UNLOCK(sc); 2153 break; 2154 default: 2155 error = ether_ioctl(ifp, cmd, data); 2156 break; 2157 } 2158 return (error); 2159 } 2160 2161 static void 2162 ae_stop(ae_softc_t *sc) 2163 { 2164 if_t ifp; 2165 int i; 2166 2167 AE_LOCK_ASSERT(sc); 2168 2169 ifp = sc->ifp; 2170 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2171 sc->flags &= ~AE_FLAG_LINK; 2172 sc->wd_timer = 0; /* Cancel watchdog. */ 2173 callout_stop(&sc->tick_ch); 2174 2175 /* 2176 * Clear and disable interrupts. 2177 */ 2178 AE_WRITE_4(sc, AE_IMR_REG, 0); 2179 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 2180 2181 /* 2182 * Stop Rx/Tx MACs. 2183 */ 2184 ae_stop_txmac(sc); 2185 ae_stop_rxmac(sc); 2186 2187 /* 2188 * Stop DMA engines. 2189 */ 2190 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 2191 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 2192 2193 /* 2194 * Wait for everything to enter idle state. 2195 */ 2196 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 2197 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 2198 break; 2199 DELAY(100); 2200 } 2201 if (i == AE_IDLE_TIMEOUT) 2202 device_printf(sc->dev, "could not enter idle state in stop.\n"); 2203 } 2204 2205 static void 2206 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats) 2207 { 2208 2209 if ((flags & AE_TXS_BCAST) != 0) 2210 stats->tx_bcast++; 2211 if ((flags & AE_TXS_MCAST) != 0) 2212 stats->tx_mcast++; 2213 if ((flags & AE_TXS_PAUSE) != 0) 2214 stats->tx_pause++; 2215 if ((flags & AE_TXS_CTRL) != 0) 2216 stats->tx_ctrl++; 2217 if ((flags & AE_TXS_DEFER) != 0) 2218 stats->tx_defer++; 2219 if ((flags & AE_TXS_EXCDEFER) != 0) 2220 stats->tx_excdefer++; 2221 if ((flags & AE_TXS_SINGLECOL) != 0) 2222 stats->tx_singlecol++; 2223 if ((flags & AE_TXS_MULTICOL) != 0) 2224 stats->tx_multicol++; 2225 if ((flags & AE_TXS_LATECOL) != 0) 2226 stats->tx_latecol++; 2227 if ((flags & AE_TXS_ABORTCOL) != 0) 2228 stats->tx_abortcol++; 2229 if ((flags & AE_TXS_UNDERRUN) != 0) 2230 stats->tx_underrun++; 2231 } 2232 2233 static void 2234 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats) 2235 { 2236 2237 if ((flags & AE_RXD_BCAST) != 0) 2238 stats->rx_bcast++; 2239 if ((flags & AE_RXD_MCAST) != 0) 2240 stats->rx_mcast++; 2241 if ((flags & AE_RXD_PAUSE) != 0) 2242 stats->rx_pause++; 2243 if ((flags & AE_RXD_CTRL) != 0) 2244 stats->rx_ctrl++; 2245 if ((flags & AE_RXD_CRCERR) != 0) 2246 stats->rx_crcerr++; 2247 if ((flags & AE_RXD_CODEERR) != 0) 2248 stats->rx_codeerr++; 2249 if ((flags & AE_RXD_RUNT) != 0) 2250 stats->rx_runt++; 2251 if ((flags & AE_RXD_FRAG) != 0) 2252 stats->rx_frag++; 2253 if ((flags & AE_RXD_TRUNC) != 0) 2254 stats->rx_trunc++; 2255 if ((flags & AE_RXD_ALIGN) != 0) 2256 stats->rx_align++; 2257 } 2258