1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __ACPI_HPET_H__ 30 #define __ACPI_HPET_H__ 31 32 #define HPET_MEM_WIDTH 0x400 /* Expected memory region size */ 33 34 /* General registers */ 35 #define HPET_CAPABILITIES 0x0 /* General capabilities and ID */ 36 #define HPET_CAP_VENDOR_ID 0xffff0000 37 #define HPET_CAP_LEG_RT 0x00008000 38 #define HPET_CAP_COUNT_SIZE 0x00002000 /* 1 = 64-bit, 0 = 32-bit */ 39 #define HPET_CAP_NUM_TIM 0x00001f00 40 #define HPET_CAP_REV_ID 0x000000ff 41 #define HPET_PERIOD 0x4 /* Period (1/hz) of timer */ 42 #define HPET_CONFIG 0x10 /* General configuration register */ 43 #define HPET_CNF_LEG_RT 0x00000002 44 #define HPET_CNF_ENABLE 0x00000001 45 #define HPET_ISR 0x20 /* General interrupt status register */ 46 #define HPET_MAIN_COUNTER 0xf0 /* Main counter register */ 47 48 /* Timer registers */ 49 #define HPET_TIMER_CAP_CNF(x) ((x) * 0x20 + 0x100) 50 #define HPET_TCAP_INT_ROUTE 0xffffffff00000000 51 #define HPET_TCAP_FSB_INT_DEL 0x00008000 52 #define HPET_TCNF_FSB_EN 0x00004000 53 #define HPET_TCNF_INT_ROUTE 0x00003e00 54 #define HPET_TCNF_32MODE 0x00000100 55 #define HPET_TCNF_VAL_SET 0x00000040 56 #define HPET_TCAP_SIZE 0x00000020 /* 1 = 64-bit, 0 = 32-bit */ 57 #define HPET_TCAP_PER_INT 0x00000010 /* Supports periodic interrupts */ 58 #define HPET_TCNF_TYPE 0x00000008 /* 1 = periodic, 0 = one-shot */ 59 #define HPET_TCNF_INT_ENB 0x00000004 60 #define HPET_TCNF_INT_TYPE 0x00000002 /* 1 = level triggered, 0 = edge */ 61 #define HPET_TIMER_COMPARATOR(x) ((x) * 0x20 + 0x108) 62 #define HPET_TIMER_FSB_VAL(x) ((x) * 0x20 + 0x110) 63 #define HPET_TIMER_FSB_ADDR(x) ((x) * 0x20 + 0x114) 64 65 #define HPET_MIN_CYCLES 128 /* Period considered reliable. */ 66 67 #endif /* !__ACPI_HPET_H__ */ 68