1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 33 #if defined(__amd64__) 34 #define DEV_APIC 35 #else 36 #include "opt_apic.h" 37 #endif 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <sys/mman.h> 46 #include <sys/time.h> 47 #include <sys/smp.h> 48 #include <sys/sysctl.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 #include <dev/acpica/acpi_hpet.h> 58 59 #ifdef DEV_APIC 60 #include "pcib_if.h" 61 #endif 62 63 #define HPET_VENDID_AMD 0x4353 64 #define HPET_VENDID_AMD2 0x1022 65 #define HPET_VENDID_HYGON 0x1d94 66 #define HPET_VENDID_INTEL 0x8086 67 #define HPET_VENDID_NVIDIA 0x10de 68 #define HPET_VENDID_SW 0x1166 69 70 ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 71 72 static devclass_t hpet_devclass; 73 74 /* ACPI CA debugging */ 75 #define _COMPONENT ACPI_TIMER 76 ACPI_MODULE_NAME("HPET") 77 78 struct hpet_softc { 79 device_t dev; 80 int mem_rid; 81 int intr_rid; 82 int irq; 83 int useirq; 84 int legacy_route; 85 int per_cpu; 86 uint32_t allowed_irqs; 87 struct resource *mem_res; 88 struct resource *intr_res; 89 void *intr_handle; 90 ACPI_HANDLE handle; 91 uint32_t acpi_uid; 92 uint64_t freq; 93 uint32_t caps; 94 struct timecounter tc; 95 struct hpet_timer { 96 struct eventtimer et; 97 struct hpet_softc *sc; 98 int num; 99 int mode; 100 #define TIMER_STOPPED 0 101 #define TIMER_PERIODIC 1 102 #define TIMER_ONESHOT 2 103 int intr_rid; 104 int irq; 105 int pcpu_cpu; 106 int pcpu_misrouted; 107 int pcpu_master; 108 int pcpu_slaves[MAXCPU]; 109 struct resource *intr_res; 110 void *intr_handle; 111 uint32_t caps; 112 uint32_t vectors; 113 uint32_t div; 114 uint32_t next; 115 char name[8]; 116 } t[32]; 117 int num_timers; 118 struct cdev *pdev; 119 int mmap_allow; 120 int mmap_allow_write; 121 }; 122 123 static d_open_t hpet_open; 124 static d_mmap_t hpet_mmap; 125 126 static struct cdevsw hpet_cdevsw = { 127 .d_version = D_VERSION, 128 .d_name = "hpet", 129 .d_open = hpet_open, 130 .d_mmap = hpet_mmap, 131 }; 132 133 static u_int hpet_get_timecount(struct timecounter *tc); 134 static void hpet_test(struct hpet_softc *sc); 135 136 static char *hpet_ids[] = { "PNP0103", NULL }; 137 138 /* Knob to disable acpi_hpet device */ 139 bool acpi_hpet_disabled = false; 140 141 static u_int 142 hpet_get_timecount(struct timecounter *tc) 143 { 144 struct hpet_softc *sc; 145 146 sc = tc->tc_priv; 147 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 148 } 149 150 uint32_t 151 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 152 { 153 struct hpet_softc *sc; 154 155 sc = tc->tc_priv; 156 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; 157 vdso_th->th_x86_shift = 0; 158 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); 159 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 160 return (sc->mmap_allow != 0); 161 } 162 163 #ifdef COMPAT_FREEBSD32 164 uint32_t 165 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 166 struct timecounter *tc) 167 { 168 struct hpet_softc *sc; 169 170 sc = tc->tc_priv; 171 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET; 172 vdso_th32->th_x86_shift = 0; 173 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev); 174 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 175 return (sc->mmap_allow != 0); 176 } 177 #endif 178 179 static void 180 hpet_enable(struct hpet_softc *sc) 181 { 182 uint32_t val; 183 184 val = bus_read_4(sc->mem_res, HPET_CONFIG); 185 if (sc->legacy_route) 186 val |= HPET_CNF_LEG_RT; 187 else 188 val &= ~HPET_CNF_LEG_RT; 189 val |= HPET_CNF_ENABLE; 190 bus_write_4(sc->mem_res, HPET_CONFIG, val); 191 } 192 193 static void 194 hpet_disable(struct hpet_softc *sc) 195 { 196 uint32_t val; 197 198 val = bus_read_4(sc->mem_res, HPET_CONFIG); 199 val &= ~HPET_CNF_ENABLE; 200 bus_write_4(sc->mem_res, HPET_CONFIG, val); 201 } 202 203 static int 204 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 205 { 206 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 207 struct hpet_timer *t; 208 struct hpet_softc *sc = mt->sc; 209 uint32_t fdiv, now; 210 211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 212 if (period != 0) { 213 t->mode = TIMER_PERIODIC; 214 t->div = (sc->freq * period) >> 32; 215 } else { 216 t->mode = TIMER_ONESHOT; 217 t->div = 0; 218 } 219 if (first != 0) 220 fdiv = (sc->freq * first) >> 32; 221 else 222 fdiv = t->div; 223 if (t->irq < 0) 224 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 225 t->caps |= HPET_TCNF_INT_ENB; 226 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 227 restart: 228 t->next = now + fdiv; 229 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) { 230 t->caps |= HPET_TCNF_TYPE; 231 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 232 t->caps | HPET_TCNF_VAL_SET); 233 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 234 t->next); 235 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 236 t->div); 237 } else { 238 t->caps &= ~HPET_TCNF_TYPE; 239 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 240 t->caps); 241 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 242 t->next); 243 } 244 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 245 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 246 fdiv *= 2; 247 goto restart; 248 } 249 return (0); 250 } 251 252 static int 253 hpet_stop(struct eventtimer *et) 254 { 255 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 256 struct hpet_timer *t; 257 struct hpet_softc *sc = mt->sc; 258 259 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 260 t->mode = TIMER_STOPPED; 261 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 262 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 263 return (0); 264 } 265 266 static int 267 hpet_intr_single(void *arg) 268 { 269 struct hpet_timer *t = (struct hpet_timer *)arg; 270 struct hpet_timer *mt; 271 struct hpet_softc *sc = t->sc; 272 uint32_t now; 273 274 if (t->mode == TIMER_STOPPED) 275 return (FILTER_STRAY); 276 /* Check that per-CPU timer interrupt reached right CPU. */ 277 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 278 if ((++t->pcpu_misrouted) % 32 == 0) { 279 printf("HPET interrupt routed to the wrong CPU" 280 " (timer %d CPU %d -> %d)!\n", 281 t->num, t->pcpu_cpu, curcpu); 282 } 283 284 /* 285 * Reload timer, hoping that next time may be more lucky 286 * (system will manage proper interrupt binding). 287 */ 288 if ((t->mode == TIMER_PERIODIC && 289 (t->caps & HPET_TCAP_PER_INT) == 0) || 290 t->mode == TIMER_ONESHOT) { 291 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 292 sc->freq / 8; 293 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 294 t->next); 295 } 296 return (FILTER_HANDLED); 297 } 298 if (t->mode == TIMER_PERIODIC && 299 (t->caps & HPET_TCAP_PER_INT) == 0) { 300 t->next += t->div; 301 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 302 if ((int32_t)((now + t->div / 2) - t->next) > 0) 303 t->next = now + t->div / 2; 304 bus_write_4(sc->mem_res, 305 HPET_TIMER_COMPARATOR(t->num), t->next); 306 } else if (t->mode == TIMER_ONESHOT) 307 t->mode = TIMER_STOPPED; 308 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 309 if (mt->et.et_active) 310 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 311 return (FILTER_HANDLED); 312 } 313 314 static int 315 hpet_intr(void *arg) 316 { 317 struct hpet_softc *sc = (struct hpet_softc *)arg; 318 int i; 319 uint32_t val; 320 321 val = bus_read_4(sc->mem_res, HPET_ISR); 322 if (val) { 323 bus_write_4(sc->mem_res, HPET_ISR, val); 324 val &= sc->useirq; 325 for (i = 0; i < sc->num_timers; i++) { 326 if ((val & (1 << i)) == 0) 327 continue; 328 hpet_intr_single(&sc->t[i]); 329 } 330 return (FILTER_HANDLED); 331 } 332 return (FILTER_STRAY); 333 } 334 335 uint32_t 336 hpet_get_uid(device_t dev) 337 { 338 struct hpet_softc *sc; 339 340 sc = device_get_softc(dev); 341 return (sc->acpi_uid); 342 } 343 344 static ACPI_STATUS 345 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 346 void **status) 347 { 348 char **ids; 349 uint32_t id = (uint32_t)(uintptr_t)context; 350 uint32_t uid = 0; 351 352 for (ids = hpet_ids; *ids != NULL; ids++) { 353 if (acpi_MatchHid(handle, *ids)) 354 break; 355 } 356 if (*ids == NULL) 357 return (AE_OK); 358 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 359 id == uid) 360 *status = acpi_get_device(handle); 361 return (AE_OK); 362 } 363 364 /* 365 * Find an existing IRQ resource that matches the requested IRQ range 366 * and return its RID. If one is not found, use a new RID. 367 */ 368 static int 369 hpet_find_irq_rid(device_t dev, u_long start, u_long end) 370 { 371 rman_res_t irq; 372 int error, rid; 373 374 for (rid = 0;; rid++) { 375 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 376 if (error != 0 || (start <= irq && irq <= end)) 377 return (rid); 378 } 379 } 380 381 static int 382 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 383 { 384 struct hpet_softc *sc; 385 386 sc = cdev->si_drv1; 387 if (!sc->mmap_allow) 388 return (EPERM); 389 else 390 return (0); 391 } 392 393 static int 394 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 395 int nprot, vm_memattr_t *memattr) 396 { 397 struct hpet_softc *sc; 398 399 sc = cdev->si_drv1; 400 if (offset >= rman_get_size(sc->mem_res)) 401 return (EINVAL); 402 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 403 return (EPERM); 404 *paddr = rman_get_start(sc->mem_res) + offset; 405 *memattr = VM_MEMATTR_UNCACHEABLE; 406 407 return (0); 408 } 409 410 /* Discover the HPET via the ACPI table of the same name. */ 411 static void 412 hpet_identify(driver_t *driver, device_t parent) 413 { 414 ACPI_TABLE_HPET *hpet; 415 ACPI_STATUS status; 416 device_t child; 417 int i; 418 419 /* Only one HPET device can be added. */ 420 if (devclass_get_device(hpet_devclass, 0)) 421 return; 422 for (i = 1; ; i++) { 423 /* Search for HPET table. */ 424 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 425 if (ACPI_FAILURE(status)) 426 return; 427 /* Search for HPET device with same ID. */ 428 child = NULL; 429 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 430 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 431 (void *)&child); 432 /* If found - let it be probed in normal way. */ 433 if (child) { 434 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 435 NULL, NULL) != 0) 436 bus_set_resource(child, SYS_RES_MEMORY, 0, 437 hpet->Address.Address, HPET_MEM_WIDTH); 438 continue; 439 } 440 /* If not - create it from table info. */ 441 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 442 if (child == NULL) { 443 printf("%s: can't add child\n", __func__); 444 continue; 445 } 446 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 447 HPET_MEM_WIDTH); 448 } 449 } 450 451 static int 452 hpet_probe(device_t dev) 453 { 454 int rv; 455 456 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 457 if (acpi_disabled("hpet") || acpi_hpet_disabled) 458 return (ENXIO); 459 if (acpi_get_handle(dev) != NULL) 460 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids, NULL); 461 else 462 rv = 0; 463 if (rv <= 0) 464 device_set_desc(dev, "High Precision Event Timer"); 465 return (rv); 466 } 467 468 static int 469 hpet_attach(device_t dev) 470 { 471 struct hpet_softc *sc; 472 struct hpet_timer *t; 473 struct make_dev_args mda; 474 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 475 int pcpu_master, error; 476 static int maxhpetet = 0; 477 uint32_t val, val2, cvectors, dvectors; 478 uint16_t vendor, rev; 479 480 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 481 482 sc = device_get_softc(dev); 483 sc->dev = dev; 484 sc->handle = acpi_get_handle(dev); 485 486 sc->mem_rid = 0; 487 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 488 RF_ACTIVE); 489 if (sc->mem_res == NULL) 490 return (ENOMEM); 491 492 /* Validate that we can access the whole region. */ 493 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 494 device_printf(dev, "memory region width %jd too small\n", 495 rman_get_size(sc->mem_res)); 496 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 497 return (ENXIO); 498 } 499 500 /* Be sure timer is enabled. */ 501 hpet_enable(sc); 502 503 /* Read basic statistics about the timer. */ 504 val = bus_read_4(sc->mem_res, HPET_PERIOD); 505 if (val == 0) { 506 device_printf(dev, "invalid period\n"); 507 hpet_disable(sc); 508 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 509 return (ENXIO); 510 } 511 512 sc->freq = (1000000000000000LL + val / 2) / val; 513 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 514 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 515 rev = sc->caps & HPET_CAP_REV_ID; 516 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 517 /* 518 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 519 * Specification and provides an off by one number 520 * of timers/comparators. 521 * Additionally, they use unregistered value in VENDOR_ID field. 522 */ 523 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 524 num_timers--; 525 sc->num_timers = num_timers; 526 if (bootverbose) { 527 device_printf(dev, 528 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 529 vendor, rev, sc->freq, 530 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 531 num_timers, 532 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 533 } 534 for (i = 0; i < num_timers; i++) { 535 t = &sc->t[i]; 536 t->sc = sc; 537 t->num = i; 538 t->mode = TIMER_STOPPED; 539 t->intr_rid = -1; 540 t->irq = -1; 541 t->pcpu_cpu = -1; 542 t->pcpu_misrouted = 0; 543 t->pcpu_master = -1; 544 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 545 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 546 if (bootverbose) { 547 device_printf(dev, 548 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 549 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 550 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 551 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 552 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 553 } 554 } 555 if (testenv("debug.acpi.hpet_test")) 556 hpet_test(sc); 557 /* 558 * Don't attach if the timer never increments. Since the spec 559 * requires it to be at least 10 MHz, it has to change in 1 us. 560 */ 561 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 562 DELAY(1); 563 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 564 if (val == val2) { 565 device_printf(dev, "HPET never increments, disabling\n"); 566 hpet_disable(sc); 567 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 568 return (ENXIO); 569 } 570 /* Announce first HPET as timecounter. */ 571 if (device_get_unit(dev) == 0) { 572 sc->tc.tc_get_timecount = hpet_get_timecount, 573 sc->tc.tc_counter_mask = ~0u, 574 sc->tc.tc_name = "HPET", 575 sc->tc.tc_quality = 950, 576 sc->tc.tc_frequency = sc->freq; 577 sc->tc.tc_priv = sc; 578 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands; 579 #ifdef COMPAT_FREEBSD32 580 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32; 581 #endif 582 tc_init(&sc->tc); 583 } 584 /* If not disabled - setup and announce event timers. */ 585 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 586 "clock", &i) == 0 && i == 0) 587 return (0); 588 589 /* Check whether we can and want legacy routing. */ 590 sc->legacy_route = 0; 591 resource_int_value(device_get_name(dev), device_get_unit(dev), 592 "legacy_route", &sc->legacy_route); 593 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 594 sc->legacy_route = 0; 595 if (sc->legacy_route) { 596 sc->t[0].vectors = 0; 597 sc->t[1].vectors = 0; 598 } 599 600 /* Check what IRQs we want use. */ 601 /* By default allow any PCI IRQs. */ 602 sc->allowed_irqs = 0xffff0000; 603 /* 604 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 605 * Lower are also not always working for different reasons. 606 * SB800 fixed it, but seems do not implements level triggering 607 * properly, that makes it very unreliable - it freezes after any 608 * interrupt loss. Avoid legacy IRQs for AMD. 609 */ 610 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2 || 611 vendor == HPET_VENDID_HYGON) 612 sc->allowed_irqs = 0x00000000; 613 /* 614 * NVidia MCP5x chipsets have number of unexplained interrupt 615 * problems. For some reason, using HPET interrupts breaks HDA sound. 616 */ 617 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 618 sc->allowed_irqs = 0x00000000; 619 /* 620 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 621 * Lower IRQs are working, but allowed mask is not set correctly. 622 * Legacy_route mode works fine. 623 */ 624 if (vendor == HPET_VENDID_SW && rev <= 0x01) 625 sc->allowed_irqs = 0x00000000; 626 /* 627 * Neither QEMU nor VirtualBox report supported IRQs correctly. 628 * The only way to use HPET there is to specify IRQs manually 629 * and/or use legacy_route. Legacy_route mode works on both. 630 */ 631 if (vm_guest) 632 sc->allowed_irqs = 0x00000000; 633 /* Let user override. */ 634 resource_int_value(device_get_name(dev), device_get_unit(dev), 635 "allowed_irqs", &sc->allowed_irqs); 636 637 /* Get how much per-CPU timers we should try to provide. */ 638 sc->per_cpu = 1; 639 resource_int_value(device_get_name(dev), device_get_unit(dev), 640 "per_cpu", &sc->per_cpu); 641 642 num_msi = 0; 643 sc->useirq = 0; 644 /* Find IRQ vectors for all timers. */ 645 cvectors = sc->allowed_irqs & 0xffff0000; 646 dvectors = sc->allowed_irqs & 0x0000ffff; 647 if (sc->legacy_route) 648 dvectors &= 0x0000fefe; 649 for (i = 0; i < num_timers; i++) { 650 t = &sc->t[i]; 651 if (sc->legacy_route && i < 2) 652 t->irq = (i == 0) ? 0 : 8; 653 #ifdef DEV_APIC 654 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 655 if ((j = PCIB_ALLOC_MSIX( 656 device_get_parent(device_get_parent(dev)), dev, 657 &t->irq))) { 658 device_printf(dev, 659 "Can't allocate interrupt for t%d: %d\n", 660 i, j); 661 } 662 } 663 #endif 664 else if (dvectors & t->vectors) { 665 t->irq = ffs(dvectors & t->vectors) - 1; 666 dvectors &= ~(1 << t->irq); 667 } 668 if (t->irq >= 0) { 669 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 670 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 671 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 672 if (t->intr_res == NULL) { 673 t->irq = -1; 674 device_printf(dev, 675 "Can't map interrupt for t%d.\n", i); 676 } else if (bus_setup_intr(dev, t->intr_res, 677 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 678 &t->intr_handle) != 0) { 679 t->irq = -1; 680 device_printf(dev, 681 "Can't setup interrupt for t%d.\n", i); 682 } else { 683 bus_describe_intr(dev, t->intr_res, 684 t->intr_handle, "t%d", i); 685 num_msi++; 686 } 687 } 688 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 689 cvectors &= t->vectors; 690 sc->useirq |= (1 << i); 691 } 692 } 693 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 694 sc->legacy_route = 0; 695 if (sc->legacy_route) 696 hpet_enable(sc); 697 /* Group timers for per-CPU operation. */ 698 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 699 num_percpu_t = num_percpu_et * mp_ncpus; 700 pcpu_master = 0; 701 cur_cpu = CPU_FIRST(); 702 for (i = 0; i < num_timers; i++) { 703 t = &sc->t[i]; 704 if (t->irq >= 0 && num_percpu_t > 0) { 705 if (cur_cpu == CPU_FIRST()) 706 pcpu_master = i; 707 t->pcpu_cpu = cur_cpu; 708 t->pcpu_master = pcpu_master; 709 sc->t[pcpu_master]. 710 pcpu_slaves[cur_cpu] = i; 711 bus_bind_intr(dev, t->intr_res, cur_cpu); 712 cur_cpu = CPU_NEXT(cur_cpu); 713 num_percpu_t--; 714 } else if (t->irq >= 0) 715 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 716 } 717 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 718 sc->irq = -1; 719 /* If at least one timer needs legacy IRQ - set it up. */ 720 if (sc->useirq) { 721 j = i = fls(cvectors) - 1; 722 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 723 j--; 724 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 725 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 726 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 727 if (sc->intr_res == NULL) 728 device_printf(dev, "Can't map interrupt.\n"); 729 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 730 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 731 device_printf(dev, "Can't setup interrupt.\n"); 732 } else { 733 sc->irq = rman_get_start(sc->intr_res); 734 /* Bind IRQ to BSP to avoid live migration. */ 735 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 736 } 737 } 738 /* Program and announce event timers. */ 739 for (i = 0; i < num_timers; i++) { 740 t = &sc->t[i]; 741 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 742 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 743 t->caps &= ~(HPET_TCNF_INT_TYPE); 744 t->caps |= HPET_TCNF_32MODE; 745 if (t->irq >= 0 && sc->legacy_route && i < 2) { 746 /* Legacy route doesn't need more configuration. */ 747 } else 748 #ifdef DEV_APIC 749 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 750 uint64_t addr; 751 uint32_t data; 752 753 if (PCIB_MAP_MSI( 754 device_get_parent(device_get_parent(dev)), dev, 755 t->irq, &addr, &data) == 0) { 756 bus_write_4(sc->mem_res, 757 HPET_TIMER_FSB_ADDR(i), addr); 758 bus_write_4(sc->mem_res, 759 HPET_TIMER_FSB_VAL(i), data); 760 t->caps |= HPET_TCNF_FSB_EN; 761 } else 762 t->irq = -2; 763 } else 764 #endif 765 if (t->irq >= 0) 766 t->caps |= (t->irq << 9); 767 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 768 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 769 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 770 /* Skip event timers without set up IRQ. */ 771 if (t->irq < 0 && 772 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 773 continue; 774 /* Announce the reset. */ 775 if (maxhpetet == 0) 776 t->et.et_name = "HPET"; 777 else { 778 sprintf(t->name, "HPET%d", maxhpetet); 779 t->et.et_name = t->name; 780 } 781 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 782 t->et.et_quality = 450; 783 if (t->pcpu_master >= 0) { 784 t->et.et_flags |= ET_FLAGS_PERCPU; 785 t->et.et_quality += 100; 786 } else if (mp_ncpus >= 8) 787 t->et.et_quality -= 100; 788 if ((t->caps & HPET_TCAP_PER_INT) == 0) 789 t->et.et_quality -= 10; 790 t->et.et_frequency = sc->freq; 791 t->et.et_min_period = 792 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 793 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 794 t->et.et_start = hpet_start; 795 t->et.et_stop = hpet_stop; 796 t->et.et_priv = &sc->t[i]; 797 if (t->pcpu_master < 0 || t->pcpu_master == i) { 798 et_register(&t->et); 799 maxhpetet++; 800 } 801 } 802 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid); 803 804 make_dev_args_init(&mda); 805 mda.mda_devsw = &hpet_cdevsw; 806 mda.mda_uid = UID_ROOT; 807 mda.mda_gid = GID_WHEEL; 808 mda.mda_mode = 0644; 809 mda.mda_si_drv1 = sc; 810 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); 811 if (error == 0) { 812 sc->mmap_allow = 1; 813 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 814 &sc->mmap_allow); 815 sc->mmap_allow_write = 0; 816 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 817 &sc->mmap_allow_write); 818 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 819 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 820 OID_AUTO, "mmap_allow", 821 CTLFLAG_RW, &sc->mmap_allow, 0, 822 "Allow userland to memory map HPET"); 823 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 824 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 825 OID_AUTO, "mmap_allow_write", 826 CTLFLAG_RW, &sc->mmap_allow_write, 0, 827 "Allow userland write to the HPET register space"); 828 } else { 829 device_printf(dev, "could not create /dev/hpet%d, error %d\n", 830 device_get_unit(dev), error); 831 } 832 833 return (0); 834 } 835 836 static int 837 hpet_detach(device_t dev) 838 { 839 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 840 841 /* XXX Without a tc_remove() function, we can't detach. */ 842 return (EBUSY); 843 } 844 845 static int 846 hpet_suspend(device_t dev) 847 { 848 // struct hpet_softc *sc; 849 850 /* 851 * Disable the timer during suspend. The timer will not lose 852 * its state in S1 or S2, but we are required to disable 853 * it. 854 */ 855 // sc = device_get_softc(dev); 856 // hpet_disable(sc); 857 858 return (0); 859 } 860 861 static int 862 hpet_resume(device_t dev) 863 { 864 struct hpet_softc *sc; 865 struct hpet_timer *t; 866 int i; 867 868 /* Re-enable the timer after a resume to keep the clock advancing. */ 869 sc = device_get_softc(dev); 870 hpet_enable(sc); 871 /* Restart event timers that were running on suspend. */ 872 for (i = 0; i < sc->num_timers; i++) { 873 t = &sc->t[i]; 874 #ifdef DEV_APIC 875 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 876 uint64_t addr; 877 uint32_t data; 878 879 if (PCIB_MAP_MSI( 880 device_get_parent(device_get_parent(dev)), dev, 881 t->irq, &addr, &data) == 0) { 882 bus_write_4(sc->mem_res, 883 HPET_TIMER_FSB_ADDR(i), addr); 884 bus_write_4(sc->mem_res, 885 HPET_TIMER_FSB_VAL(i), data); 886 } 887 } 888 #endif 889 if (t->mode == TIMER_STOPPED) 890 continue; 891 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 892 if (t->mode == TIMER_PERIODIC && 893 (t->caps & HPET_TCAP_PER_INT) != 0) { 894 t->caps |= HPET_TCNF_TYPE; 895 t->next += t->div; 896 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 897 t->caps | HPET_TCNF_VAL_SET); 898 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 899 t->next); 900 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 901 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 902 t->div); 903 } else { 904 t->next += sc->freq / 1024; 905 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 906 t->next); 907 } 908 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 909 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 910 } 911 return (0); 912 } 913 914 /* Print some basic latency/rate information to assist in debugging. */ 915 static void 916 hpet_test(struct hpet_softc *sc) 917 { 918 int i; 919 uint32_t u1, u2; 920 struct bintime b0, b1, b2; 921 struct timespec ts; 922 923 binuptime(&b0); 924 binuptime(&b0); 925 binuptime(&b1); 926 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 927 for (i = 1; i < 1000; i++) 928 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 929 binuptime(&b2); 930 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 931 932 bintime_sub(&b2, &b1); 933 bintime_sub(&b1, &b0); 934 bintime_sub(&b2, &b1); 935 bintime2timespec(&b2, &ts); 936 937 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 938 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 939 940 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 941 } 942 943 #ifdef DEV_APIC 944 static int 945 hpet_remap_intr(device_t dev, device_t child, u_int irq) 946 { 947 struct hpet_softc *sc = device_get_softc(dev); 948 struct hpet_timer *t; 949 uint64_t addr; 950 uint32_t data; 951 int error, i; 952 953 for (i = 0; i < sc->num_timers; i++) { 954 t = &sc->t[i]; 955 if (t->irq != irq) 956 continue; 957 error = PCIB_MAP_MSI( 958 device_get_parent(device_get_parent(dev)), dev, 959 irq, &addr, &data); 960 if (error) 961 return (error); 962 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 963 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 964 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 965 hpet_enable(sc); 966 return (0); 967 } 968 return (ENOENT); 969 } 970 #endif 971 972 static device_method_t hpet_methods[] = { 973 /* Device interface */ 974 DEVMETHOD(device_identify, hpet_identify), 975 DEVMETHOD(device_probe, hpet_probe), 976 DEVMETHOD(device_attach, hpet_attach), 977 DEVMETHOD(device_detach, hpet_detach), 978 DEVMETHOD(device_suspend, hpet_suspend), 979 DEVMETHOD(device_resume, hpet_resume), 980 981 #ifdef DEV_APIC 982 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 983 #endif 984 985 DEVMETHOD_END 986 }; 987 988 static driver_t hpet_driver = { 989 "hpet", 990 hpet_methods, 991 sizeof(struct hpet_softc), 992 }; 993 994 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 995 MODULE_DEPEND(hpet, acpi, 1, 1, 1); 996