1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 118 119 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 120 121 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 122 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 123 124 #define PCI_VENDOR_INTEL 0x8086 125 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 126 #define PCI_REVISION_A_STEP 0 127 #define PCI_REVISION_B_STEP 1 128 #define PCI_REVISION_4E 2 129 #define PCI_REVISION_4M 3 130 #define PIIX4_DEVACTB_REG 0x58 131 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 132 #define PIIX4_BRLD_EN_IRQ (1<<1) 133 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 134 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 135 #define PIIX4_PCNTRL_BST_EN (1<<10) 136 137 #define CST_FFH_VENDOR_INTEL 1 138 #define CST_FFH_INTEL_CL_C1IO 1 139 #define CST_FFH_INTEL_CL_MWAIT 2 140 #define CST_FFH_MWAIT_HW_COORD 0x0001 141 #define CST_FFH_MWAIT_BM_AVOID 0x0002 142 143 /* Allow users to ignore processor orders in MADT. */ 144 static int cpu_unordered; 145 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN, 146 &cpu_unordered, 0, 147 "Do not use the MADT to match ACPI Processor objects to CPUs."); 148 149 /* Knob to disable acpi_cpu devices */ 150 bool acpi_cpu_disabled = false; 151 152 /* Platform hardware resource information. */ 153 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 154 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 155 static int cpu_quirks; /* Indicate any hardware bugs. */ 156 157 /* Values for sysctl. */ 158 static struct sysctl_ctx_list cpu_sysctl_ctx; 159 static struct sysctl_oid *cpu_sysctl_tree; 160 static int cpu_cx_generic; 161 static int cpu_cx_lowest_lim; 162 163 static device_t *cpu_devices; 164 static int cpu_ndevices; 165 static struct acpi_cpu_softc **cpu_softc; 166 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 167 168 static int acpi_cpu_probe(device_t dev); 169 static int acpi_cpu_attach(device_t dev); 170 static int acpi_cpu_suspend(device_t dev); 171 static int acpi_cpu_resume(device_t dev); 172 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, 173 uint32_t *cpu_id); 174 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 175 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 176 int unit); 177 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 178 uintptr_t *result); 179 static int acpi_cpu_shutdown(device_t dev); 180 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 181 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 182 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 183 static void acpi_cpu_startup(void *arg); 184 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 185 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 186 #if defined(__i386__) || defined(__amd64__) 187 static void acpi_cpu_idle(sbintime_t sbt); 188 #endif 189 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 190 static void acpi_cpu_quirks(void); 191 static void acpi_cpu_quirks_piix4(void); 192 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 193 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 194 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 195 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 196 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 197 #if defined(__i386__) || defined(__amd64__) 198 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 199 #endif 200 201 static device_method_t acpi_cpu_methods[] = { 202 /* Device interface */ 203 DEVMETHOD(device_probe, acpi_cpu_probe), 204 DEVMETHOD(device_attach, acpi_cpu_attach), 205 DEVMETHOD(device_detach, bus_generic_detach), 206 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 207 DEVMETHOD(device_suspend, acpi_cpu_suspend), 208 DEVMETHOD(device_resume, acpi_cpu_resume), 209 210 /* Bus interface */ 211 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 212 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 213 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 214 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 215 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 216 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 217 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 218 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 219 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 220 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 221 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 222 223 DEVMETHOD_END 224 }; 225 226 static driver_t acpi_cpu_driver = { 227 "cpu", 228 acpi_cpu_methods, 229 sizeof(struct acpi_cpu_softc), 230 }; 231 232 static devclass_t acpi_cpu_devclass; 233 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 234 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 235 236 static int 237 acpi_cpu_probe(device_t dev) 238 { 239 int acpi_id, cpu_id; 240 ACPI_BUFFER buf; 241 ACPI_HANDLE handle; 242 ACPI_OBJECT *obj; 243 ACPI_STATUS status; 244 245 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR || 246 acpi_cpu_disabled) 247 return (ENXIO); 248 249 handle = acpi_get_handle(dev); 250 if (cpu_softc == NULL) 251 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 252 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 253 254 /* Get our Processor object. */ 255 buf.Pointer = NULL; 256 buf.Length = ACPI_ALLOCATE_BUFFER; 257 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 258 if (ACPI_FAILURE(status)) { 259 device_printf(dev, "probe failed to get Processor obj - %s\n", 260 AcpiFormatException(status)); 261 return (ENXIO); 262 } 263 obj = (ACPI_OBJECT *)buf.Pointer; 264 if (obj->Type != ACPI_TYPE_PROCESSOR) { 265 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 266 AcpiOsFree(obj); 267 return (ENXIO); 268 } 269 270 /* 271 * Find the processor associated with our unit. We could use the 272 * ProcId as a key, however, some boxes do not have the same values 273 * in their Processor object as the ProcId values in the MADT. 274 */ 275 acpi_id = obj->Processor.ProcId; 276 AcpiOsFree(obj); 277 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0) 278 return (ENXIO); 279 280 /* 281 * Check if we already probed this processor. We scan the bus twice 282 * so it's possible we've already seen this one. 283 */ 284 if (cpu_softc[cpu_id] != NULL) 285 return (ENXIO); 286 287 /* Mark this processor as in-use and save our derived id for attach. */ 288 cpu_softc[cpu_id] = (void *)1; 289 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 290 device_set_desc(dev, "ACPI CPU"); 291 292 return (0); 293 } 294 295 static int 296 acpi_cpu_attach(device_t dev) 297 { 298 ACPI_BUFFER buf; 299 ACPI_OBJECT arg[4], *obj; 300 ACPI_OBJECT_LIST arglist; 301 struct pcpu *pcpu_data; 302 struct acpi_cpu_softc *sc; 303 struct acpi_softc *acpi_sc; 304 ACPI_STATUS status; 305 u_int features; 306 int cpu_id, drv_count, i; 307 driver_t **drivers; 308 uint32_t cap_set[3]; 309 310 /* UUID needed by _OSC evaluation */ 311 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 312 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 313 0x58, 0x71, 0x39, 0x53 }; 314 315 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 316 317 sc = device_get_softc(dev); 318 sc->cpu_dev = dev; 319 sc->cpu_handle = acpi_get_handle(dev); 320 cpu_id = (int)(intptr_t)acpi_get_private(dev); 321 cpu_softc[cpu_id] = sc; 322 pcpu_data = pcpu_find(cpu_id); 323 pcpu_data->pc_device = dev; 324 sc->cpu_pcpu = pcpu_data; 325 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 326 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 327 328 buf.Pointer = NULL; 329 buf.Length = ACPI_ALLOCATE_BUFFER; 330 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 331 if (ACPI_FAILURE(status)) { 332 device_printf(dev, "attach failed to get Processor obj - %s\n", 333 AcpiFormatException(status)); 334 return (ENXIO); 335 } 336 obj = (ACPI_OBJECT *)buf.Pointer; 337 sc->cpu_p_blk = obj->Processor.PblkAddress; 338 sc->cpu_p_blk_len = obj->Processor.PblkLength; 339 sc->cpu_acpi_id = obj->Processor.ProcId; 340 AcpiOsFree(obj); 341 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 342 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 343 344 /* 345 * If this is the first cpu we attach, create and initialize the generic 346 * resources that will be used by all acpi cpu devices. 347 */ 348 if (device_get_unit(dev) == 0) { 349 /* Assume we won't be using generic Cx mode by default */ 350 cpu_cx_generic = FALSE; 351 352 /* Install hw.acpi.cpu sysctl tree */ 353 acpi_sc = acpi_device_get_parent_softc(dev); 354 sysctl_ctx_init(&cpu_sysctl_ctx); 355 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 356 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 357 CTLFLAG_RD, 0, "node for CPU children"); 358 359 /* Queue post cpu-probing task handler */ 360 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 361 } 362 363 /* 364 * Before calling any CPU methods, collect child driver feature hints 365 * and notify ACPI of them. We support unified SMP power control 366 * so advertise this ourselves. Note this is not the same as independent 367 * SMP control where each CPU can have different settings. 368 */ 369 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 370 ACPI_CAP_C1_IO_HALT; 371 372 #if defined(__i386__) || defined(__amd64__) 373 /* 374 * Ask for MWAIT modes if not disabled and interrupts work 375 * reasonable with MWAIT. 376 */ 377 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 378 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 379 #endif 380 381 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 382 for (i = 0; i < drv_count; i++) { 383 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 384 sc->cpu_features |= features; 385 } 386 free(drivers, M_TEMP); 387 } 388 389 /* 390 * CPU capabilities are specified in 391 * Intel Processor Vendor-Specific ACPI Interface Specification. 392 */ 393 if (sc->cpu_features) { 394 arglist.Pointer = arg; 395 arglist.Count = 4; 396 arg[0].Type = ACPI_TYPE_BUFFER; 397 arg[0].Buffer.Length = sizeof(cpu_oscuuid); 398 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */ 399 arg[1].Type = ACPI_TYPE_INTEGER; 400 arg[1].Integer.Value = 1; /* revision */ 401 arg[2].Type = ACPI_TYPE_INTEGER; 402 arg[2].Integer.Value = 1; /* count */ 403 arg[3].Type = ACPI_TYPE_BUFFER; 404 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */ 405 arg[3].Buffer.Pointer = (uint8_t *)cap_set; 406 cap_set[0] = 0; /* status */ 407 cap_set[1] = sc->cpu_features; 408 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL); 409 if (ACPI_SUCCESS(status)) { 410 if (cap_set[0] != 0) 411 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 412 } 413 else { 414 arglist.Pointer = arg; 415 arglist.Count = 1; 416 arg[0].Type = ACPI_TYPE_BUFFER; 417 arg[0].Buffer.Length = sizeof(cap_set); 418 arg[0].Buffer.Pointer = (uint8_t *)cap_set; 419 cap_set[0] = 1; /* revision */ 420 cap_set[1] = 1; /* number of capabilities integers */ 421 cap_set[2] = sc->cpu_features; 422 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 423 } 424 } 425 426 /* Probe for Cx state support. */ 427 acpi_cpu_cx_probe(sc); 428 429 return (0); 430 } 431 432 static void 433 acpi_cpu_postattach(void *unused __unused) 434 { 435 device_t *devices; 436 int err; 437 int i, n; 438 439 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 440 if (err != 0) { 441 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 442 return; 443 } 444 for (i = 0; i < n; i++) 445 bus_generic_probe(devices[i]); 446 for (i = 0; i < n; i++) 447 bus_generic_attach(devices[i]); 448 free(devices, M_TEMP); 449 } 450 451 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 452 acpi_cpu_postattach, NULL); 453 454 static void 455 disable_idle(struct acpi_cpu_softc *sc) 456 { 457 cpuset_t cpuset; 458 459 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 460 sc->cpu_disable_idle = TRUE; 461 462 /* 463 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 464 * Note that this code depends on the fact that the rendezvous IPI 465 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 466 * is called and executed in such a context with interrupts being re-enabled 467 * right before return. 468 */ 469 smp_rendezvous_cpus(cpuset, smp_no_rendevous_barrier, NULL, 470 smp_no_rendevous_barrier, NULL); 471 } 472 473 static void 474 enable_idle(struct acpi_cpu_softc *sc) 475 { 476 477 sc->cpu_disable_idle = FALSE; 478 } 479 480 #if defined(__i386__) || defined(__amd64__) 481 static int 482 is_idle_disabled(struct acpi_cpu_softc *sc) 483 { 484 485 return (sc->cpu_disable_idle); 486 } 487 #endif 488 489 /* 490 * Disable any entry to the idle function during suspend and re-enable it 491 * during resume. 492 */ 493 static int 494 acpi_cpu_suspend(device_t dev) 495 { 496 int error; 497 498 error = bus_generic_suspend(dev); 499 if (error) 500 return (error); 501 disable_idle(device_get_softc(dev)); 502 return (0); 503 } 504 505 static int 506 acpi_cpu_resume(device_t dev) 507 { 508 509 enable_idle(device_get_softc(dev)); 510 return (bus_generic_resume(dev)); 511 } 512 513 /* 514 * Find the processor associated with a given ACPI ID. By default, 515 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a 516 * processor. Some systems have inconsistent ASL and MADT however. 517 * For these systems the cpu_unordered tunable can be set in which 518 * case we assume that Processor objects are listed in the same order 519 * in both the MADT and ASL. 520 */ 521 static int 522 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id) 523 { 524 struct pcpu *pc; 525 uint32_t i, idx; 526 527 KASSERT(acpi_id != NULL, ("Null acpi_id")); 528 KASSERT(cpu_id != NULL, ("Null cpu_id")); 529 idx = device_get_unit(dev); 530 531 /* 532 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 533 * UP box) use the ACPI ID from the first processor we find. 534 */ 535 if (idx == 0 && mp_ncpus == 1) { 536 pc = pcpu_find(0); 537 if (pc->pc_acpi_id == 0xffffffff) 538 pc->pc_acpi_id = *acpi_id; 539 *cpu_id = 0; 540 return (0); 541 } 542 543 CPU_FOREACH(i) { 544 pc = pcpu_find(i); 545 KASSERT(pc != NULL, ("no pcpu data for %d", i)); 546 if (cpu_unordered) { 547 if (idx-- == 0) { 548 /* 549 * If pc_acpi_id doesn't match the ACPI ID from the 550 * ASL, prefer the MADT-derived value. 551 */ 552 if (pc->pc_acpi_id != *acpi_id) 553 *acpi_id = pc->pc_acpi_id; 554 *cpu_id = pc->pc_cpuid; 555 return (0); 556 } 557 } else { 558 if (pc->pc_acpi_id == *acpi_id) { 559 if (bootverbose) 560 device_printf(dev, 561 "Processor %s (ACPI ID %u) -> APIC ID %d\n", 562 acpi_name(acpi_get_handle(dev)), *acpi_id, 563 pc->pc_cpuid); 564 *cpu_id = pc->pc_cpuid; 565 return (0); 566 } 567 } 568 } 569 570 if (bootverbose) 571 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 572 acpi_name(acpi_get_handle(dev)), *acpi_id); 573 574 return (ESRCH); 575 } 576 577 static struct resource_list * 578 acpi_cpu_get_rlist(device_t dev, device_t child) 579 { 580 struct acpi_cpu_device *ad; 581 582 ad = device_get_ivars(child); 583 if (ad == NULL) 584 return (NULL); 585 return (&ad->ad_rl); 586 } 587 588 static device_t 589 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 590 { 591 struct acpi_cpu_device *ad; 592 device_t child; 593 594 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 595 return (NULL); 596 597 resource_list_init(&ad->ad_rl); 598 599 child = device_add_child_ordered(dev, order, name, unit); 600 if (child != NULL) 601 device_set_ivars(child, ad); 602 else 603 free(ad, M_TEMP); 604 return (child); 605 } 606 607 static int 608 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 609 { 610 struct acpi_cpu_softc *sc; 611 612 sc = device_get_softc(dev); 613 switch (index) { 614 case ACPI_IVAR_HANDLE: 615 *result = (uintptr_t)sc->cpu_handle; 616 break; 617 case CPU_IVAR_PCPU: 618 *result = (uintptr_t)sc->cpu_pcpu; 619 break; 620 #if defined(__amd64__) || defined(__i386__) 621 case CPU_IVAR_NOMINAL_MHZ: 622 if (tsc_is_invariant) { 623 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 624 break; 625 } 626 /* FALLTHROUGH */ 627 #endif 628 default: 629 return (ENOENT); 630 } 631 return (0); 632 } 633 634 static int 635 acpi_cpu_shutdown(device_t dev) 636 { 637 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 638 639 /* Allow children to shutdown first. */ 640 bus_generic_shutdown(dev); 641 642 /* 643 * Disable any entry to the idle function. 644 */ 645 disable_idle(device_get_softc(dev)); 646 647 /* 648 * CPU devices are not truely detached and remain referenced, 649 * so their resources are not freed. 650 */ 651 652 return_VALUE (0); 653 } 654 655 static void 656 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 657 { 658 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 659 660 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 661 sc->cpu_prev_sleep = 1000000; 662 sc->cpu_cx_lowest = 0; 663 sc->cpu_cx_lowest_lim = 0; 664 665 /* 666 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 667 * any, we'll revert to generic FADT/P_BLK Cx control method which will 668 * be handled by acpi_cpu_startup. We need to defer to after having 669 * probed all the cpus in the system before probing for generic Cx 670 * states as we may already have found cpus with valid _CST packages 671 */ 672 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 673 /* 674 * We were unable to find a _CST package for this cpu or there 675 * was an error parsing it. Switch back to generic mode. 676 */ 677 cpu_cx_generic = TRUE; 678 if (bootverbose) 679 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 680 } 681 682 /* 683 * TODO: _CSD Package should be checked here. 684 */ 685 } 686 687 static void 688 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 689 { 690 ACPI_GENERIC_ADDRESS gas; 691 struct acpi_cx *cx_ptr; 692 693 sc->cpu_cx_count = 0; 694 cx_ptr = sc->cpu_cx_states; 695 696 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 697 sc->cpu_prev_sleep = 1000000; 698 699 /* C1 has been required since just after ACPI 1.0 */ 700 cx_ptr->type = ACPI_STATE_C1; 701 cx_ptr->trans_lat = 0; 702 cx_ptr++; 703 sc->cpu_non_c2 = sc->cpu_cx_count; 704 sc->cpu_non_c3 = sc->cpu_cx_count; 705 sc->cpu_cx_count++; 706 cpu_deepest_sleep = 1; 707 708 /* 709 * The spec says P_BLK must be 6 bytes long. However, some systems 710 * use it to indicate a fractional set of features present so we 711 * take 5 as C2. Some may also have a value of 7 to indicate 712 * another C3 but most use _CST for this (as required) and having 713 * "only" C1-C3 is not a hardship. 714 */ 715 if (sc->cpu_p_blk_len < 5) 716 return; 717 718 /* Validate and allocate resources for C2 (P_LVL2). */ 719 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 720 gas.BitWidth = 8; 721 if (AcpiGbl_FADT.C2Latency <= 100) { 722 gas.Address = sc->cpu_p_blk + 4; 723 cx_ptr->res_rid = 0; 724 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 725 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 726 if (cx_ptr->p_lvlx != NULL) { 727 cx_ptr->type = ACPI_STATE_C2; 728 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 729 cx_ptr++; 730 sc->cpu_non_c3 = sc->cpu_cx_count; 731 sc->cpu_cx_count++; 732 cpu_deepest_sleep = 2; 733 } 734 } 735 if (sc->cpu_p_blk_len < 6) 736 return; 737 738 /* Validate and allocate resources for C3 (P_LVL3). */ 739 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 740 gas.Address = sc->cpu_p_blk + 5; 741 cx_ptr->res_rid = 1; 742 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 743 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 744 if (cx_ptr->p_lvlx != NULL) { 745 cx_ptr->type = ACPI_STATE_C3; 746 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 747 cx_ptr++; 748 sc->cpu_cx_count++; 749 cpu_deepest_sleep = 3; 750 } 751 } 752 } 753 754 #if defined(__i386__) || defined(__amd64__) 755 static void 756 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 757 { 758 759 cx_ptr->do_mwait = true; 760 cx_ptr->mwait_hint = address & 0xffffffff; 761 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 762 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 763 } 764 #endif 765 766 static void 767 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 768 { 769 770 if (cx_ptr->p_lvlx == NULL) 771 return; 772 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 773 cx_ptr->p_lvlx); 774 cx_ptr->p_lvlx = NULL; 775 } 776 777 /* 778 * Parse a _CST package and set up its Cx states. Since the _CST object 779 * can change dynamically, our notify handler may call this function 780 * to clean up and probe the new _CST package. 781 */ 782 static int 783 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 784 { 785 struct acpi_cx *cx_ptr; 786 ACPI_STATUS status; 787 ACPI_BUFFER buf; 788 ACPI_OBJECT *top; 789 ACPI_OBJECT *pkg; 790 uint32_t count; 791 int i; 792 #if defined(__i386__) || defined(__amd64__) 793 uint64_t address; 794 int vendor, class, accsize; 795 #endif 796 797 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 798 799 buf.Pointer = NULL; 800 buf.Length = ACPI_ALLOCATE_BUFFER; 801 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 802 if (ACPI_FAILURE(status)) 803 return (ENXIO); 804 805 /* _CST is a package with a count and at least one Cx package. */ 806 top = (ACPI_OBJECT *)buf.Pointer; 807 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 808 device_printf(sc->cpu_dev, "invalid _CST package\n"); 809 AcpiOsFree(buf.Pointer); 810 return (ENXIO); 811 } 812 if (count != top->Package.Count - 1) { 813 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 814 count, top->Package.Count - 1); 815 count = top->Package.Count - 1; 816 } 817 if (count > MAX_CX_STATES) { 818 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 819 count = MAX_CX_STATES; 820 } 821 822 sc->cpu_non_c2 = 0; 823 sc->cpu_non_c3 = 0; 824 sc->cpu_cx_count = 0; 825 cx_ptr = sc->cpu_cx_states; 826 827 /* 828 * C1 has been required since just after ACPI 1.0. 829 * Reserve the first slot for it. 830 */ 831 cx_ptr->type = ACPI_STATE_C0; 832 cx_ptr++; 833 sc->cpu_cx_count++; 834 cpu_deepest_sleep = 1; 835 836 /* Set up all valid states. */ 837 for (i = 0; i < count; i++) { 838 pkg = &top->Package.Elements[i + 1]; 839 if (!ACPI_PKG_VALID(pkg, 4) || 840 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 841 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 842 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 843 844 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 845 continue; 846 } 847 848 /* Validate the state to see if we should use it. */ 849 switch (cx_ptr->type) { 850 case ACPI_STATE_C1: 851 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 852 #if defined(__i386__) || defined(__amd64__) 853 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 854 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 855 if (class == CST_FFH_INTEL_CL_C1IO) { 856 /* C1 I/O then Halt */ 857 cx_ptr->res_rid = sc->cpu_cx_count; 858 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 859 cx_ptr->res_rid, address, 1); 860 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 861 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 862 RF_SHAREABLE); 863 if (cx_ptr->p_lvlx == NULL) { 864 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 865 cx_ptr->res_rid); 866 device_printf(sc->cpu_dev, 867 "C1 I/O failed to allocate port %d, " 868 "degrading to C1 Halt", (int)address); 869 } 870 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 871 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 872 } 873 } 874 #endif 875 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 876 /* This is the first C1 state. Use the reserved slot. */ 877 sc->cpu_cx_states[0] = *cx_ptr; 878 } else { 879 sc->cpu_non_c2 = sc->cpu_cx_count; 880 sc->cpu_non_c3 = sc->cpu_cx_count; 881 cx_ptr++; 882 sc->cpu_cx_count++; 883 } 884 continue; 885 case ACPI_STATE_C2: 886 sc->cpu_non_c3 = sc->cpu_cx_count; 887 if (cpu_deepest_sleep < 2) 888 cpu_deepest_sleep = 2; 889 break; 890 case ACPI_STATE_C3: 891 default: 892 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 893 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 894 "acpi_cpu%d: C3[%d] not available.\n", 895 device_get_unit(sc->cpu_dev), i)); 896 continue; 897 } else 898 cpu_deepest_sleep = 3; 899 break; 900 } 901 902 /* Free up any previous register. */ 903 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 904 905 /* Allocate the control register for C2 or C3. */ 906 #if defined(__i386__) || defined(__amd64__) 907 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 908 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 909 class == CST_FFH_INTEL_CL_MWAIT) { 910 /* Native C State Instruction use (mwait) */ 911 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 912 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 913 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 914 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 915 cx_ptr++; 916 sc->cpu_cx_count++; 917 } else 918 #endif 919 { 920 cx_ptr->res_rid = sc->cpu_cx_count; 921 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 922 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 923 if (cx_ptr->p_lvlx) { 924 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 925 "acpi_cpu%d: Got C%d - %d latency\n", 926 device_get_unit(sc->cpu_dev), cx_ptr->type, 927 cx_ptr->trans_lat)); 928 cx_ptr++; 929 sc->cpu_cx_count++; 930 } 931 } 932 } 933 AcpiOsFree(buf.Pointer); 934 935 /* If C1 state was not found, we need one now. */ 936 cx_ptr = sc->cpu_cx_states; 937 if (cx_ptr->type == ACPI_STATE_C0) { 938 cx_ptr->type = ACPI_STATE_C1; 939 cx_ptr->trans_lat = 0; 940 } 941 942 return (0); 943 } 944 945 /* 946 * Call this *after* all CPUs have been attached. 947 */ 948 static void 949 acpi_cpu_startup(void *arg) 950 { 951 struct acpi_cpu_softc *sc; 952 int i; 953 954 /* Get set of CPU devices */ 955 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 956 957 /* 958 * Setup any quirks that might necessary now that we have probed 959 * all the CPUs 960 */ 961 acpi_cpu_quirks(); 962 963 if (cpu_cx_generic) { 964 /* 965 * We are using generic Cx mode, probe for available Cx states 966 * for all processors. 967 */ 968 for (i = 0; i < cpu_ndevices; i++) { 969 sc = device_get_softc(cpu_devices[i]); 970 acpi_cpu_generic_cx_probe(sc); 971 } 972 } else { 973 /* 974 * We are using _CST mode, remove C3 state if necessary. 975 * As we now know for sure that we will be using _CST mode 976 * install our notify handler. 977 */ 978 for (i = 0; i < cpu_ndevices; i++) { 979 sc = device_get_softc(cpu_devices[i]); 980 if (cpu_quirks & CPU_QUIRK_NO_C3) { 981 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 982 } 983 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 984 acpi_cpu_notify, sc); 985 } 986 } 987 988 /* Perform Cx final initialization. */ 989 for (i = 0; i < cpu_ndevices; i++) { 990 sc = device_get_softc(cpu_devices[i]); 991 acpi_cpu_startup_cx(sc); 992 } 993 994 /* Add a sysctl handler to handle global Cx lowest setting */ 995 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 996 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 997 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 998 "Global lowest Cx sleep state to use"); 999 1000 /* Take over idling from cpu_idle_default(). */ 1001 cpu_cx_lowest_lim = 0; 1002 for (i = 0; i < cpu_ndevices; i++) { 1003 sc = device_get_softc(cpu_devices[i]); 1004 enable_idle(sc); 1005 } 1006 #if defined(__i386__) || defined(__amd64__) 1007 cpu_idle_hook = acpi_cpu_idle; 1008 #endif 1009 } 1010 1011 static void 1012 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 1013 { 1014 struct sbuf sb; 1015 int i; 1016 1017 /* 1018 * Set up the list of Cx states 1019 */ 1020 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1021 SBUF_FIXEDLEN); 1022 for (i = 0; i < sc->cpu_cx_count; i++) 1023 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1024 sc->cpu_cx_states[i].trans_lat); 1025 sbuf_trim(&sb); 1026 sbuf_finish(&sb); 1027 } 1028 1029 static void 1030 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1031 { 1032 acpi_cpu_cx_list(sc); 1033 1034 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1035 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1036 OID_AUTO, "cx_supported", CTLFLAG_RD, 1037 sc->cpu_cx_supported, 0, 1038 "Cx/microsecond values for supported Cx states"); 1039 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1040 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1041 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 1042 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1043 "lowest Cx sleep state to use"); 1044 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1045 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1046 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 1047 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1048 "percent usage for each Cx state"); 1049 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1050 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1051 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD, 1052 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1053 "Cx sleep state counters"); 1054 #if defined(__i386__) || defined(__amd64__) 1055 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1056 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1057 OID_AUTO, "cx_method", CTLTYPE_STRING | CTLFLAG_RD, 1058 (void *)sc, 0, acpi_cpu_method_sysctl, "A", 1059 "Cx entrance methods"); 1060 #endif 1061 1062 /* Signal platform that we can handle _CST notification. */ 1063 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1064 ACPI_LOCK(acpi); 1065 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1066 ACPI_UNLOCK(acpi); 1067 } 1068 } 1069 1070 #if defined(__i386__) || defined(__amd64__) 1071 /* 1072 * Idle the CPU in the lowest state possible. This function is called with 1073 * interrupts disabled. Note that once it re-enables interrupts, a task 1074 * switch can occur so do not access shared data (i.e. the softc) after 1075 * interrupts are re-enabled. 1076 */ 1077 static void 1078 acpi_cpu_idle(sbintime_t sbt) 1079 { 1080 struct acpi_cpu_softc *sc; 1081 struct acpi_cx *cx_next; 1082 uint64_t cputicks; 1083 uint32_t start_time, end_time; 1084 ACPI_STATUS status; 1085 int bm_active, cx_next_idx, i, us; 1086 1087 /* 1088 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1089 * since there is no ACPI processor object for this CPU. This occurs 1090 * for logical CPUs in the HTT case. 1091 */ 1092 sc = cpu_softc[PCPU_GET(cpuid)]; 1093 if (sc == NULL) { 1094 acpi_cpu_c1(); 1095 return; 1096 } 1097 1098 /* If disabled, take the safe path. */ 1099 if (is_idle_disabled(sc)) { 1100 acpi_cpu_c1(); 1101 return; 1102 } 1103 1104 /* Find the lowest state that has small enough latency. */ 1105 us = sc->cpu_prev_sleep; 1106 if (sbt >= 0 && us > (sbt >> 12)) 1107 us = (sbt >> 12); 1108 cx_next_idx = 0; 1109 if (cpu_disable_c2_sleep) 1110 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1111 else if (cpu_disable_c3_sleep) 1112 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1113 else 1114 i = sc->cpu_cx_lowest; 1115 for (; i >= 0; i--) { 1116 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1117 cx_next_idx = i; 1118 break; 1119 } 1120 } 1121 1122 /* 1123 * Check for bus master activity. If there was activity, clear 1124 * the bit and use the lowest non-C3 state. Note that the USB 1125 * driver polling for new devices keeps this bit set all the 1126 * time if USB is loaded. 1127 */ 1128 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1129 cx_next_idx > sc->cpu_non_c3) { 1130 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1131 if (ACPI_SUCCESS(status) && bm_active != 0) { 1132 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1133 cx_next_idx = sc->cpu_non_c3; 1134 } 1135 } 1136 1137 /* Select the next state and update statistics. */ 1138 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1139 sc->cpu_cx_stats[cx_next_idx]++; 1140 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1141 1142 /* 1143 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1144 * precisely calculate the time spent in C1 since the place we wake up 1145 * is an ISR. Assume we slept no more then half of quantum, unless 1146 * we are called inside critical section, delaying context switch. 1147 */ 1148 if (cx_next->type == ACPI_STATE_C1) { 1149 cputicks = cpu_ticks(); 1150 if (cx_next->p_lvlx != NULL) { 1151 /* C1 I/O then Halt */ 1152 CPU_GET_REG(cx_next->p_lvlx, 1); 1153 } 1154 if (cx_next->do_mwait) 1155 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1156 else 1157 acpi_cpu_c1(); 1158 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1159 if (curthread->td_critnest == 0) 1160 end_time = min(end_time, 500000 / hz); 1161 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1162 return; 1163 } 1164 1165 /* 1166 * For C3, disable bus master arbitration and enable bus master wake 1167 * if BM control is available, otherwise flush the CPU cache. 1168 */ 1169 if (cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) { 1170 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1171 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1172 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1173 } else 1174 ACPI_FLUSH_CPU_CACHE(); 1175 } 1176 1177 /* 1178 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1179 * Use the ACPI timer for measuring sleep time. Since we need to 1180 * get the time very close to the CPU start/stop clock logic, this 1181 * is the only reliable time source. 1182 */ 1183 if (cx_next->type == ACPI_STATE_C3) { 1184 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 1185 cputicks = 0; 1186 } else { 1187 start_time = 0; 1188 cputicks = cpu_ticks(); 1189 } 1190 if (cx_next->do_mwait) 1191 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1192 else 1193 CPU_GET_REG(cx_next->p_lvlx, 1); 1194 1195 /* 1196 * Read the end time twice. Since it may take an arbitrary time 1197 * to enter the idle state, the first read may be executed before 1198 * the processor has stopped. Doing it again provides enough 1199 * margin that we are certain to have a correct value. 1200 */ 1201 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1202 if (cx_next->type == ACPI_STATE_C3) { 1203 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1204 end_time = acpi_TimerDelta(end_time, start_time); 1205 } else 1206 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1207 1208 /* Enable bus master arbitration and disable bus master wakeup. */ 1209 if ((cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) && 1210 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1211 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1212 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1213 } 1214 ACPI_ENABLE_IRQS(); 1215 1216 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1217 } 1218 #endif 1219 1220 /* 1221 * Re-evaluate the _CST object when we are notified that it changed. 1222 */ 1223 static void 1224 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1225 { 1226 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1227 1228 if (notify != ACPI_NOTIFY_CX_STATES) 1229 return; 1230 1231 /* 1232 * C-state data for target CPU is going to be in flux while we execute 1233 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1234 * Also, it may happen that multiple ACPI taskqueues may concurrently 1235 * execute notifications for the same CPU. ACPI_SERIAL is used to 1236 * protect against that. 1237 */ 1238 ACPI_SERIAL_BEGIN(cpu); 1239 disable_idle(sc); 1240 1241 /* Update the list of Cx states. */ 1242 acpi_cpu_cx_cst(sc); 1243 acpi_cpu_cx_list(sc); 1244 acpi_cpu_set_cx_lowest(sc); 1245 1246 enable_idle(sc); 1247 ACPI_SERIAL_END(cpu); 1248 1249 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1250 } 1251 1252 static void 1253 acpi_cpu_quirks(void) 1254 { 1255 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1256 1257 /* 1258 * Bus mastering arbitration control is needed to keep caches coherent 1259 * while sleeping in C3. If it's not present but a working flush cache 1260 * instruction is present, flush the caches before entering C3 instead. 1261 * Otherwise, just disable C3 completely. 1262 */ 1263 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1264 AcpiGbl_FADT.Pm2ControlLength == 0) { 1265 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1266 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1267 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1268 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1269 "acpi_cpu: no BM control, using flush cache method\n")); 1270 } else { 1271 cpu_quirks |= CPU_QUIRK_NO_C3; 1272 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1273 "acpi_cpu: no BM control, C3 not available\n")); 1274 } 1275 } 1276 1277 /* 1278 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1279 * the expensive flush cache instruction. 1280 */ 1281 if (cpu_cx_generic && mp_ncpus > 1) { 1282 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1283 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1284 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1285 } 1286 1287 /* Look for various quirks of the PIIX4 part. */ 1288 acpi_cpu_quirks_piix4(); 1289 } 1290 1291 static void 1292 acpi_cpu_quirks_piix4(void) 1293 { 1294 #ifdef __i386__ 1295 device_t acpi_dev; 1296 uint32_t val; 1297 ACPI_STATUS status; 1298 1299 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1300 if (acpi_dev != NULL) { 1301 switch (pci_get_revid(acpi_dev)) { 1302 /* 1303 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1304 * do not report the BMIDE status to the BM status register and 1305 * others have a livelock bug if Type-F DMA is enabled. Linux 1306 * works around the BMIDE bug by reading the BM status directly 1307 * but we take the simpler approach of disabling C3 for these 1308 * parts. 1309 * 1310 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1311 * Livelock") from the January 2002 PIIX4 specification update. 1312 * Applies to all PIIX4 models. 1313 * 1314 * Also, make sure that all interrupts cause a "Stop Break" 1315 * event to exit from C2 state. 1316 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1317 * should be set to zero, otherwise it causes C2 to short-sleep. 1318 * PIIX4 doesn't properly support C3 and bus master activity 1319 * need not break out of C2. 1320 */ 1321 case PCI_REVISION_A_STEP: 1322 case PCI_REVISION_B_STEP: 1323 case PCI_REVISION_4E: 1324 case PCI_REVISION_4M: 1325 cpu_quirks |= CPU_QUIRK_NO_C3; 1326 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1327 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1328 1329 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1330 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1331 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1332 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1333 val |= PIIX4_STOP_BREAK_MASK; 1334 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1335 } 1336 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1337 if (ACPI_SUCCESS(status) && val != 0) { 1338 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1339 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1340 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1341 } 1342 break; 1343 default: 1344 break; 1345 } 1346 } 1347 #endif 1348 } 1349 1350 static int 1351 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1352 { 1353 struct acpi_cpu_softc *sc; 1354 struct sbuf sb; 1355 char buf[128]; 1356 int i; 1357 uintmax_t fract, sum, whole; 1358 1359 sc = (struct acpi_cpu_softc *) arg1; 1360 sum = 0; 1361 for (i = 0; i < sc->cpu_cx_count; i++) 1362 sum += sc->cpu_cx_stats[i]; 1363 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1364 for (i = 0; i < sc->cpu_cx_count; i++) { 1365 if (sum > 0) { 1366 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1367 fract = (whole % sum) * 100; 1368 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1369 (u_int)(fract / sum)); 1370 } else 1371 sbuf_printf(&sb, "0.00%% "); 1372 } 1373 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1374 sbuf_trim(&sb); 1375 sbuf_finish(&sb); 1376 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1377 sbuf_delete(&sb); 1378 1379 return (0); 1380 } 1381 1382 /* 1383 * XXX TODO: actually add support to count each entry/exit 1384 * from the Cx states. 1385 */ 1386 static int 1387 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1388 { 1389 struct acpi_cpu_softc *sc; 1390 struct sbuf sb; 1391 char buf[128]; 1392 int i; 1393 1394 sc = (struct acpi_cpu_softc *) arg1; 1395 1396 /* Print out the raw counters */ 1397 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1398 1399 for (i = 0; i < sc->cpu_cx_count; i++) { 1400 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]); 1401 } 1402 1403 sbuf_trim(&sb); 1404 sbuf_finish(&sb); 1405 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1406 sbuf_delete(&sb); 1407 1408 return (0); 1409 } 1410 1411 #if defined(__i386__) || defined(__amd64__) 1412 static int 1413 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1414 { 1415 struct acpi_cpu_softc *sc; 1416 struct acpi_cx *cx; 1417 struct sbuf sb; 1418 char buf[128]; 1419 int i; 1420 1421 sc = (struct acpi_cpu_softc *)arg1; 1422 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1423 for (i = 0; i < sc->cpu_cx_count; i++) { 1424 cx = &sc->cpu_cx_states[i]; 1425 sbuf_printf(&sb, "C%d/", i + 1); 1426 if (cx->do_mwait) { 1427 sbuf_cat(&sb, "mwait"); 1428 if (cx->mwait_hw_coord) 1429 sbuf_cat(&sb, "/hwc"); 1430 if (cx->mwait_bm_avoidance) 1431 sbuf_cat(&sb, "/bma"); 1432 } else if (cx->type == ACPI_STATE_C1) { 1433 sbuf_cat(&sb, "hlt"); 1434 } else { 1435 sbuf_cat(&sb, "io"); 1436 } 1437 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1438 sbuf_cat(&sb, "/iohlt"); 1439 sbuf_putc(&sb, ' '); 1440 } 1441 sbuf_trim(&sb); 1442 sbuf_finish(&sb); 1443 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1444 sbuf_delete(&sb); 1445 return (0); 1446 } 1447 #endif 1448 1449 static int 1450 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1451 { 1452 int i; 1453 1454 ACPI_SERIAL_ASSERT(cpu); 1455 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1456 1457 /* If not disabling, cache the new lowest non-C3 state. */ 1458 sc->cpu_non_c3 = 0; 1459 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1460 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1461 sc->cpu_non_c3 = i; 1462 break; 1463 } 1464 } 1465 1466 /* Reset the statistics counters. */ 1467 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1468 return (0); 1469 } 1470 1471 static int 1472 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1473 { 1474 struct acpi_cpu_softc *sc; 1475 char state[8]; 1476 int val, error; 1477 1478 sc = (struct acpi_cpu_softc *) arg1; 1479 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1480 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1481 if (error != 0 || req->newptr == NULL) 1482 return (error); 1483 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1484 return (EINVAL); 1485 if (strcasecmp(state, "Cmax") == 0) 1486 val = MAX_CX_STATES; 1487 else { 1488 val = (int) strtol(state + 1, NULL, 10); 1489 if (val < 1 || val > MAX_CX_STATES) 1490 return (EINVAL); 1491 } 1492 1493 ACPI_SERIAL_BEGIN(cpu); 1494 sc->cpu_cx_lowest_lim = val - 1; 1495 acpi_cpu_set_cx_lowest(sc); 1496 ACPI_SERIAL_END(cpu); 1497 1498 return (0); 1499 } 1500 1501 static int 1502 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1503 { 1504 struct acpi_cpu_softc *sc; 1505 char state[8]; 1506 int val, error, i; 1507 1508 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1509 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1510 if (error != 0 || req->newptr == NULL) 1511 return (error); 1512 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1513 return (EINVAL); 1514 if (strcasecmp(state, "Cmax") == 0) 1515 val = MAX_CX_STATES; 1516 else { 1517 val = (int) strtol(state + 1, NULL, 10); 1518 if (val < 1 || val > MAX_CX_STATES) 1519 return (EINVAL); 1520 } 1521 1522 /* Update the new lowest useable Cx state for all CPUs. */ 1523 ACPI_SERIAL_BEGIN(cpu); 1524 cpu_cx_lowest_lim = val - 1; 1525 for (i = 0; i < cpu_ndevices; i++) { 1526 sc = device_get_softc(cpu_devices[i]); 1527 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1528 acpi_cpu_set_cx_lowest(sc); 1529 } 1530 ACPI_SERIAL_END(cpu); 1531 1532 return (0); 1533 } 1534