1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_acpi.h" 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/cpu.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/pcpu.h> 37 #include <sys/power.h> 38 #include <sys/proc.h> 39 #include <sys/sched.h> 40 #include <sys/sbuf.h> 41 #include <sys/smp.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <machine/atomic.h> 45 #include <machine/bus.h> 46 #if defined(__amd64__) || defined(__i386__) 47 #include <machine/clock.h> 48 #include <machine/specialreg.h> 49 #include <machine/md_var.h> 50 #endif 51 #include <sys/rman.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 58 /* 59 * Support for ACPI Processor devices, including C[1-3] sleep states. 60 */ 61 62 /* Hooks for the ACPI CA debugging infrastructure */ 63 #define _COMPONENT ACPI_PROCESSOR 64 ACPI_MODULE_NAME("PROCESSOR") 65 66 struct acpi_cx { 67 struct resource *p_lvlx; /* Register to read to enter state. */ 68 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 69 uint32_t trans_lat; /* Transition latency (usec). */ 70 uint32_t power; /* Power consumed (mW). */ 71 int res_type; /* Resource type for p_lvlx. */ 72 int res_rid; /* Resource ID for p_lvlx. */ 73 bool do_mwait; 74 uint32_t mwait_hint; 75 bool mwait_hw_coord; 76 bool mwait_bm_avoidance; 77 }; 78 #define MAX_CX_STATES 8 79 80 struct acpi_cpu_softc { 81 device_t cpu_dev; 82 ACPI_HANDLE cpu_handle; 83 struct pcpu *cpu_pcpu; 84 uint32_t cpu_acpi_id; /* ACPI processor id */ 85 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 86 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 87 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 88 int cpu_cx_count; /* Number of valid Cx states. */ 89 int cpu_prev_sleep;/* Last idle sleep duration. */ 90 int cpu_features; /* Child driver supported features. */ 91 /* Runtime state. */ 92 int cpu_non_c2; /* Index of lowest non-C2 state. */ 93 int cpu_non_c3; /* Index of lowest non-C3 state. */ 94 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 95 uint64_t cpu_cx_duration[MAX_CX_STATES];/* Cx cumulative sleep */ 96 /* Values for sysctl. */ 97 struct sysctl_ctx_list cpu_sysctl_ctx; 98 struct sysctl_oid *cpu_sysctl_tree; 99 int cpu_cx_lowest; 100 int cpu_cx_lowest_lim; 101 int cpu_disable_idle; /* Disable entry to idle function */ 102 char cpu_cx_supported[64]; 103 }; 104 105 struct acpi_cpu_device { 106 struct resource_list ad_rl; 107 }; 108 109 #define CPU_GET_REG(reg, width) \ 110 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 111 rman_get_bushandle((reg)), 0)) 112 #define CPU_SET_REG(reg, width, val) \ 113 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 114 rman_get_bushandle((reg)), 0, (val))) 115 116 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 117 118 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 119 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 120 121 #define PCI_VENDOR_INTEL 0x8086 122 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 123 #define PCI_REVISION_A_STEP 0 124 #define PCI_REVISION_B_STEP 1 125 #define PCI_REVISION_4E 2 126 #define PCI_REVISION_4M 3 127 #define PIIX4_DEVACTB_REG 0x58 128 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 129 #define PIIX4_BRLD_EN_IRQ (1<<1) 130 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 131 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 132 #define PIIX4_PCNTRL_BST_EN (1<<10) 133 134 #define CST_FFH_VENDOR_INTEL 1 135 #define CST_FFH_VENDOR_AMD 2 136 #define CST_FFH_INTEL_CL_C1IO 1 137 #define CST_FFH_INTEL_CL_MWAIT 2 138 #define CST_FFH_MWAIT_HW_COORD 0x0001 139 #define CST_FFH_MWAIT_BM_AVOID 0x0002 140 141 #define CPUDEV_DEVICE_ID "ACPI0007" 142 143 /* Platform hardware resource information. */ 144 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 145 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 146 static int cpu_quirks; /* Indicate any hardware bugs. */ 147 148 /* Values for sysctl. */ 149 static struct sysctl_ctx_list cpu_sysctl_ctx; 150 static struct sysctl_oid *cpu_sysctl_tree; 151 static int cpu_cx_generic; 152 static int cpu_cx_lowest_lim; 153 #if defined(__i386__) || defined(__amd64__) 154 static bool cppc_notify; 155 #endif 156 157 static struct acpi_cpu_softc **cpu_softc; 158 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 159 160 static int acpi_cpu_probe(device_t dev); 161 static int acpi_cpu_attach(device_t dev); 162 static int acpi_cpu_suspend(device_t dev); 163 static int acpi_cpu_resume(device_t dev); 164 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, 165 u_int *cpu_id); 166 static void acpi_cpu_madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg); 167 static bool acpi_cpu_enabled_in_madt(uint32_t acpi_id); 168 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 169 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 170 int unit); 171 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 172 uintptr_t *result); 173 static int acpi_cpu_shutdown(device_t dev); 174 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 175 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 176 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 177 static void acpi_cpu_startup(void *arg); 178 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 179 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 180 #if defined(__i386__) || defined(__amd64__) 181 static void acpi_cpu_idle(sbintime_t sbt); 182 #endif 183 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 184 static void acpi_cpu_quirks(void); 185 static void acpi_cpu_quirks_piix4(void); 186 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 187 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 188 static int acpi_cpu_duration_counters_sysctl(SYSCTL_HANDLER_ARGS); 189 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 190 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 191 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 192 #if defined(__i386__) || defined(__amd64__) 193 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 194 #endif 195 196 static device_method_t acpi_cpu_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, acpi_cpu_probe), 199 DEVMETHOD(device_attach, acpi_cpu_attach), 200 DEVMETHOD(device_detach, bus_generic_detach), 201 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 202 DEVMETHOD(device_suspend, acpi_cpu_suspend), 203 DEVMETHOD(device_resume, acpi_cpu_resume), 204 205 /* Bus interface */ 206 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 207 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 208 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 209 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 210 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 211 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 212 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 213 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 214 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 215 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 216 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 217 218 DEVMETHOD_END 219 }; 220 221 static driver_t acpi_cpu_driver = { 222 "cpu", 223 acpi_cpu_methods, 224 sizeof(struct acpi_cpu_softc), 225 }; 226 227 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, 0, 0); 228 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 229 230 static int 231 acpi_cpu_probe(device_t dev) 232 { 233 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL }; 234 int acpi_id, cpu_id; 235 ACPI_BUFFER buf; 236 ACPI_HANDLE handle; 237 ACPI_OBJECT *obj; 238 ACPI_STATUS status; 239 ACPI_OBJECT_TYPE type; 240 241 if (acpi_disabled("cpu")) 242 return (ENXIO); 243 type = acpi_get_type(dev); 244 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE) 245 return (ENXIO); 246 if (type == ACPI_TYPE_DEVICE && 247 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0) 248 return (ENXIO); 249 250 handle = acpi_get_handle(dev); 251 if (cpu_softc == NULL) 252 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 253 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 254 255 if (type == ACPI_TYPE_PROCESSOR) { 256 /* Get our Processor object. */ 257 buf.Pointer = NULL; 258 buf.Length = ACPI_ALLOCATE_BUFFER; 259 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 260 if (ACPI_FAILURE(status)) { 261 device_printf(dev, "probe failed to get Processor obj - %s\n", 262 AcpiFormatException(status)); 263 return (ENXIO); 264 } 265 obj = (ACPI_OBJECT *)buf.Pointer; 266 if (obj->Type != ACPI_TYPE_PROCESSOR) { 267 device_printf(dev, "Processor object has bad type %d\n", 268 obj->Type); 269 AcpiOsFree(obj); 270 return (ENXIO); 271 } 272 273 /* 274 * Find the processor associated with our unit. We could use the 275 * ProcId as a key, however, some boxes do not have the same values 276 * in their Processor object as the ProcId values in the MADT. 277 */ 278 acpi_id = obj->Processor.ProcId; 279 AcpiOsFree(obj); 280 } else { 281 status = acpi_GetInteger(handle, "_UID", &acpi_id); 282 if (ACPI_FAILURE(status)) { 283 device_printf(dev, "Device object has bad value - %s\n", 284 AcpiFormatException(status)); 285 return (ENXIO); 286 } 287 } 288 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) { 289 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255) && 290 acpi_cpu_enabled_in_madt(acpi_id)) 291 printf("ACPI: Processor %s (ACPI ID %u) enabled but not online, " 292 "ignored\n", acpi_name(handle), acpi_id); 293 return (ENXIO); 294 } 295 296 if (device_set_unit(dev, cpu_id) != 0) 297 return (ENXIO); 298 299 device_set_desc(dev, "ACPI CPU"); 300 301 if (!bootverbose && device_get_unit(dev) != 0) { 302 device_quiet(dev); 303 device_quiet_children(dev); 304 } 305 306 return (BUS_PROBE_DEFAULT); 307 } 308 309 static int 310 acpi_cpu_attach(device_t dev) 311 { 312 ACPI_BUFFER buf; 313 ACPI_OBJECT arg, *obj; 314 ACPI_OBJECT_LIST arglist; 315 struct pcpu *pcpu_data; 316 struct acpi_cpu_softc *sc; 317 struct acpi_softc *acpi_sc; 318 ACPI_STATUS status; 319 int cpu_id, drv_count, i; 320 driver_t **drivers; 321 uint32_t cap_set[3]; 322 323 /* UUID needed by _OSC evaluation */ 324 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 325 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 326 0x58, 0x71, 0x39, 0x53 }; 327 328 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 329 330 sc = device_get_softc(dev); 331 sc->cpu_dev = dev; 332 sc->cpu_handle = acpi_get_handle(dev); 333 cpu_id = device_get_unit(dev); 334 cpu_softc[cpu_id] = sc; 335 pcpu_data = pcpu_find(cpu_id); 336 pcpu_data->pc_device = dev; 337 sc->cpu_pcpu = pcpu_data; 338 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 339 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 340 341 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) { 342 buf.Pointer = NULL; 343 buf.Length = ACPI_ALLOCATE_BUFFER; 344 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 345 if (ACPI_FAILURE(status)) { 346 device_printf(dev, "attach failed to get Processor obj - %s\n", 347 AcpiFormatException(status)); 348 return (ENXIO); 349 } 350 obj = (ACPI_OBJECT *)buf.Pointer; 351 sc->cpu_p_blk = obj->Processor.PblkAddress; 352 sc->cpu_p_blk_len = obj->Processor.PblkLength; 353 sc->cpu_acpi_id = obj->Processor.ProcId; 354 AcpiOsFree(obj); 355 } else { 356 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE, 357 ("Unexpected ACPI object")); 358 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id); 359 if (ACPI_FAILURE(status)) { 360 device_printf(dev, "Device object has bad value - %s\n", 361 AcpiFormatException(status)); 362 return (ENXIO); 363 } 364 sc->cpu_p_blk = 0; 365 sc->cpu_p_blk_len = 0; 366 } 367 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 368 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 369 370 /* 371 * If this is the first cpu we attach, create and initialize the generic 372 * resources that will be used by all acpi cpu devices. 373 */ 374 if (device_get_unit(dev) == 0) { 375 /* Assume we won't be using generic Cx mode by default */ 376 cpu_cx_generic = FALSE; 377 378 /* Install hw.acpi.cpu sysctl tree */ 379 acpi_sc = acpi_device_get_parent_softc(dev); 380 sysctl_ctx_init(&cpu_sysctl_ctx); 381 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 382 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children"); 384 385 #if defined(__i386__) || defined(__amd64__) 386 /* Add sysctl handler to control registering for CPPC notifications */ 387 cppc_notify = 1; 388 SYSCTL_ADD_BOOL(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 389 OID_AUTO, "cppc_notify", CTLFLAG_RDTUN | CTLFLAG_MPSAFE, 390 &cppc_notify, 0, "Register for CPPC Notifications"); 391 #endif 392 } 393 394 /* 395 * Before calling any CPU methods, collect child driver feature hints 396 * and notify ACPI of them. We support unified SMP power control 397 * so advertise this ourselves. Note this is not the same as independent 398 * SMP control where each CPU can have different settings. 399 */ 400 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 401 ACPI_CAP_C1_IO_HALT; 402 403 #if defined(__i386__) || defined(__amd64__) 404 /* 405 * Ask for MWAIT modes if not disabled and interrupts work 406 * reasonable with MWAIT. 407 */ 408 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 409 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 410 411 /* 412 * Work around a lingering SMM bug which leads to freezes when handling 413 * CPPC notifications. Tell the SMM we will handle any CPPC notifications. 414 */ 415 if ((cpu_power_eax & CPUTPM1_HWP_NOTIFICATION) && cppc_notify) 416 sc->cpu_features |= ACPI_CAP_INTR_CPPC; 417 #endif 418 419 if (devclass_get_drivers(device_get_devclass(dev), &drivers, 420 &drv_count) == 0) { 421 for (i = 0; i < drv_count; i++) { 422 u_int features = 0; 423 424 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 425 sc->cpu_features |= features; 426 } 427 free(drivers, M_TEMP); 428 } 429 430 /* 431 * CPU capabilities are specified in 432 * Intel Processor Vendor-Specific ACPI Interface Specification. 433 */ 434 if (sc->cpu_features) { 435 cap_set[1] = sc->cpu_features; 436 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 437 cap_set, false); 438 if (ACPI_SUCCESS(status)) { 439 if (cap_set[0] != 0) 440 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 441 } 442 else { 443 arglist.Pointer = &arg; 444 arglist.Count = 1; 445 arg.Type = ACPI_TYPE_BUFFER; 446 arg.Buffer.Length = sizeof(cap_set); 447 arg.Buffer.Pointer = (uint8_t *)cap_set; 448 cap_set[0] = 1; /* revision */ 449 cap_set[1] = 1; /* number of capabilities integers */ 450 cap_set[2] = sc->cpu_features; 451 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 452 } 453 } 454 455 /* Probe for Cx state support. */ 456 acpi_cpu_cx_probe(sc); 457 458 return (0); 459 } 460 461 static void 462 acpi_cpu_postattach(void *unused __unused) 463 { 464 struct acpi_cpu_softc *sc; 465 int attached = 0, i; 466 467 if (cpu_softc == NULL) 468 return; 469 470 bus_topo_lock(); 471 CPU_FOREACH(i) { 472 if ((sc = cpu_softc[i]) != NULL) 473 bus_identify_children(sc->cpu_dev); 474 } 475 CPU_FOREACH(i) { 476 if ((sc = cpu_softc[i]) != NULL) { 477 bus_attach_children(sc->cpu_dev); 478 attached = 1; 479 } 480 } 481 bus_topo_unlock(); 482 483 if (attached) { 484 #ifdef EARLY_AP_STARTUP 485 acpi_cpu_startup(NULL); 486 #else 487 /* Queue post cpu-probing task handler */ 488 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 489 #endif 490 } 491 } 492 493 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 494 acpi_cpu_postattach, NULL); 495 496 static void 497 disable_idle(struct acpi_cpu_softc *sc) 498 { 499 cpuset_t cpuset; 500 501 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 502 sc->cpu_disable_idle = TRUE; 503 504 /* 505 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 506 * Note that this code depends on the fact that the rendezvous IPI 507 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 508 * is called and executed in such a context with interrupts being re-enabled 509 * right before return. 510 */ 511 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 512 smp_no_rendezvous_barrier, NULL); 513 } 514 515 static void 516 enable_idle(struct acpi_cpu_softc *sc) 517 { 518 519 if (sc->cpu_cx_count > sc->cpu_non_c3 + 1 && 520 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 521 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 522 sc->cpu_disable_idle = FALSE; 523 } 524 525 #if defined(__i386__) || defined(__amd64__) 526 static int 527 is_idle_disabled(struct acpi_cpu_softc *sc) 528 { 529 530 return (sc->cpu_disable_idle); 531 } 532 #endif 533 534 /* 535 * Disable any entry to the idle function during suspend and re-enable it 536 * during resume. 537 */ 538 static int 539 acpi_cpu_suspend(device_t dev) 540 { 541 int error; 542 543 error = bus_generic_suspend(dev); 544 if (error) 545 return (error); 546 disable_idle(device_get_softc(dev)); 547 return (0); 548 } 549 550 static int 551 acpi_cpu_resume(device_t dev) 552 { 553 554 enable_idle(device_get_softc(dev)); 555 return (bus_generic_resume(dev)); 556 } 557 558 /* 559 * Find the processor associated with a given ACPI ID. 560 */ 561 static int 562 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id) 563 { 564 struct pcpu *pc; 565 u_int i; 566 567 CPU_FOREACH(i) { 568 pc = pcpu_find(i); 569 if (pc->pc_acpi_id == acpi_id) { 570 *cpu_id = pc->pc_cpuid; 571 return (0); 572 } 573 } 574 575 /* 576 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 577 * UP box) use the ACPI ID from the first processor we find. 578 */ 579 if (mp_ncpus == 1) { 580 pc = pcpu_find(0); 581 if (pc->pc_acpi_id == 0xffffffff) 582 pc->pc_acpi_id = acpi_id; 583 *cpu_id = 0; 584 return (0); 585 } 586 587 return (ESRCH); 588 } 589 590 struct acpi_cpu_madt_check { 591 uint32_t acpi_id; 592 bool enabled; 593 }; 594 595 static void 596 acpi_cpu_madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg) 597 { 598 struct acpi_cpu_madt_check *check = arg; 599 uint32_t id, flags; 600 601 switch (entry->Type) { 602 case ACPI_MADT_TYPE_LOCAL_APIC: 603 id = ((ACPI_MADT_LOCAL_APIC *)entry)->ProcessorId; 604 flags = ((ACPI_MADT_LOCAL_APIC *)entry)->LapicFlags; 605 break; 606 case ACPI_MADT_TYPE_LOCAL_X2APIC: 607 id = ((ACPI_MADT_LOCAL_X2APIC *)entry)->Uid; 608 flags = ((ACPI_MADT_LOCAL_X2APIC *)entry)->LapicFlags; 609 break; 610 case ACPI_MADT_TYPE_GENERIC_INTERRUPT: 611 id = ((ACPI_MADT_GENERIC_INTERRUPT *)entry)->Uid; 612 flags = ((ACPI_MADT_GENERIC_INTERRUPT *)entry)->Flags; 613 break; 614 case ACPI_MADT_TYPE_RINTC: 615 id = ((ACPI_MADT_RINTC *)entry)->Uid; 616 flags = ((ACPI_MADT_RINTC *)entry)->Flags; 617 break; 618 default: 619 return; 620 } 621 if (id == check->acpi_id && (flags & ACPI_MADT_ENABLED) != 0) 622 check->enabled = true; 623 } 624 625 static bool 626 acpi_cpu_enabled_in_madt(uint32_t acpi_id) 627 { 628 static ACPI_TABLE_MADT *madt; 629 struct acpi_cpu_madt_check check = { 630 .acpi_id = acpi_id, 631 }; 632 ACPI_TABLE_HEADER *hdr; 633 634 if (madt == NULL) { 635 if (ACPI_FAILURE(AcpiGetTable(ACPI_SIG_MADT, 1, &hdr))) 636 return (false); 637 madt = (ACPI_TABLE_MADT *)hdr; 638 /* Retain the table reference for subsequent processor probes. */ 639 } 640 641 acpi_walk_subtables(madt + 1, 642 (char *)madt + madt->Header.Length, acpi_cpu_madt_handler, &check); 643 return (check.enabled); 644 } 645 646 static struct resource_list * 647 acpi_cpu_get_rlist(device_t dev, device_t child) 648 { 649 struct acpi_cpu_device *ad; 650 651 ad = device_get_ivars(child); 652 if (ad == NULL) 653 return (NULL); 654 return (&ad->ad_rl); 655 } 656 657 static device_t 658 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 659 { 660 struct acpi_cpu_device *ad; 661 device_t child; 662 663 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 664 return (NULL); 665 666 resource_list_init(&ad->ad_rl); 667 668 child = device_add_child_ordered(dev, order, name, unit); 669 if (child != NULL) 670 device_set_ivars(child, ad); 671 else 672 free(ad, M_TEMP); 673 return (child); 674 } 675 676 static int 677 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 678 { 679 struct acpi_cpu_softc *sc; 680 681 sc = device_get_softc(dev); 682 switch (index) { 683 case ACPI_IVAR_HANDLE: 684 *result = (uintptr_t)sc->cpu_handle; 685 break; 686 case CPU_IVAR_PCPU: 687 *result = (uintptr_t)sc->cpu_pcpu; 688 break; 689 #if defined(__amd64__) || defined(__i386__) 690 case CPU_IVAR_NOMINAL_MHZ: 691 if (tsc_is_invariant) { 692 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 693 break; 694 } 695 /* FALLTHROUGH */ 696 #endif 697 default: 698 return (ENOENT); 699 } 700 return (0); 701 } 702 703 static int 704 acpi_cpu_shutdown(device_t dev) 705 { 706 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 707 708 /* Allow children to shutdown first. */ 709 bus_generic_shutdown(dev); 710 711 /* 712 * Disable any entry to the idle function. 713 */ 714 disable_idle(device_get_softc(dev)); 715 716 /* 717 * CPU devices are not truly detached and remain referenced, 718 * so their resources are not freed. 719 */ 720 721 return_VALUE (0); 722 } 723 724 static void 725 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 726 { 727 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 728 729 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 730 sc->cpu_prev_sleep = 1000000; 731 sc->cpu_cx_lowest = 0; 732 sc->cpu_cx_lowest_lim = 0; 733 734 /* 735 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 736 * any, we'll revert to generic FADT/P_BLK Cx control method which will 737 * be handled by acpi_cpu_startup. We need to defer to after having 738 * probed all the cpus in the system before probing for generic Cx 739 * states as we may already have found cpus with valid _CST packages 740 */ 741 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 742 /* 743 * We were unable to find a _CST package for this cpu or there 744 * was an error parsing it. Switch back to generic mode. 745 */ 746 cpu_cx_generic = TRUE; 747 if (bootverbose) 748 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 749 } 750 751 /* 752 * TODO: _CSD Package should be checked here. 753 */ 754 } 755 756 static void 757 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 758 { 759 ACPI_GENERIC_ADDRESS gas; 760 struct acpi_cx *cx_ptr; 761 762 sc->cpu_cx_count = 0; 763 cx_ptr = sc->cpu_cx_states; 764 765 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 766 sc->cpu_prev_sleep = 1000000; 767 768 /* C1 has been required since just after ACPI 1.0 */ 769 cx_ptr->type = ACPI_STATE_C1; 770 cx_ptr->trans_lat = 0; 771 cx_ptr++; 772 sc->cpu_non_c2 = sc->cpu_cx_count; 773 sc->cpu_non_c3 = sc->cpu_cx_count; 774 sc->cpu_cx_count++; 775 776 /* 777 * The spec says P_BLK must be 6 bytes long. However, some systems 778 * use it to indicate a fractional set of features present so we 779 * take 5 as C2. Some may also have a value of 7 to indicate 780 * another C3 but most use _CST for this (as required) and having 781 * "only" C1-C3 is not a hardship. 782 */ 783 if (sc->cpu_p_blk_len < 5) 784 return; 785 786 /* Validate and allocate resources for C2 (P_LVL2). */ 787 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 788 gas.BitWidth = 8; 789 if (AcpiGbl_FADT.C2Latency <= 100) { 790 gas.Address = sc->cpu_p_blk + 4; 791 cx_ptr->res_rid = 0; 792 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, cx_ptr->res_rid, 793 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 794 if (cx_ptr->p_lvlx != NULL) { 795 cx_ptr->type = ACPI_STATE_C2; 796 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 797 cx_ptr++; 798 sc->cpu_non_c3 = sc->cpu_cx_count; 799 sc->cpu_cx_count++; 800 } 801 } 802 if (sc->cpu_p_blk_len < 6) 803 return; 804 805 /* Validate and allocate resources for C3 (P_LVL3). */ 806 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 807 gas.Address = sc->cpu_p_blk + 5; 808 cx_ptr->res_rid = 1; 809 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, cx_ptr->res_rid, 810 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 811 if (cx_ptr->p_lvlx != NULL) { 812 cx_ptr->type = ACPI_STATE_C3; 813 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 814 cx_ptr++; 815 sc->cpu_cx_count++; 816 } 817 } 818 } 819 820 #if defined(__i386__) || defined(__amd64__) 821 static void 822 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 823 { 824 825 cx_ptr->do_mwait = true; 826 cx_ptr->mwait_hint = address & 0xffffffff; 827 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 828 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 829 } 830 #endif 831 832 static void 833 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 834 { 835 836 if (cx_ptr->p_lvlx == NULL) 837 return; 838 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 839 cx_ptr->p_lvlx); 840 cx_ptr->p_lvlx = NULL; 841 } 842 843 /* 844 * Parse a _CST package and set up its Cx states. Since the _CST object 845 * can change dynamically, our notify handler may call this function 846 * to clean up and probe the new _CST package. 847 */ 848 static int 849 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 850 { 851 struct acpi_cx *cx_ptr; 852 ACPI_STATUS status; 853 ACPI_BUFFER buf; 854 ACPI_OBJECT *top; 855 ACPI_OBJECT *pkg; 856 uint32_t count; 857 int i; 858 #if defined(__i386__) || defined(__amd64__) 859 uint64_t address; 860 int vendor, class, accsize; 861 #endif 862 863 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 864 865 buf.Pointer = NULL; 866 buf.Length = ACPI_ALLOCATE_BUFFER; 867 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 868 if (ACPI_FAILURE(status)) 869 return (ENXIO); 870 871 /* _CST is a package with a count and at least one Cx package. */ 872 top = (ACPI_OBJECT *)buf.Pointer; 873 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 874 device_printf(sc->cpu_dev, "invalid _CST package\n"); 875 AcpiOsFree(buf.Pointer); 876 return (ENXIO); 877 } 878 if (count != top->Package.Count - 1) { 879 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 880 count, top->Package.Count - 1); 881 count = top->Package.Count - 1; 882 } 883 if (count > MAX_CX_STATES) { 884 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 885 count = MAX_CX_STATES; 886 } 887 888 sc->cpu_non_c2 = 0; 889 sc->cpu_non_c3 = 0; 890 sc->cpu_cx_count = 0; 891 cx_ptr = sc->cpu_cx_states; 892 893 /* 894 * C1 has been required since just after ACPI 1.0. 895 * Reserve the first slot for it. 896 */ 897 cx_ptr->type = ACPI_STATE_C0; 898 cx_ptr++; 899 sc->cpu_cx_count++; 900 901 /* Set up all valid states. */ 902 for (i = 0; i < count; i++) { 903 pkg = &top->Package.Elements[i + 1]; 904 if (!ACPI_PKG_VALID(pkg, 4) || 905 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 906 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 907 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 908 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 909 continue; 910 } 911 912 /* Validate the state to see if we should use it. */ 913 switch (cx_ptr->type) { 914 case ACPI_STATE_C1: 915 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 916 #if defined(__i386__) || defined(__amd64__) 917 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 918 &accsize) == 0 && 919 (vendor == CST_FFH_VENDOR_INTEL || vendor == CST_FFH_VENDOR_AMD)) { 920 if (class == CST_FFH_INTEL_CL_C1IO) { 921 /* C1 I/O then Halt */ 922 cx_ptr->res_rid = sc->cpu_cx_count; 923 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 924 cx_ptr->res_rid, address, 1); 925 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 926 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 927 RF_SHAREABLE); 928 if (cx_ptr->p_lvlx == NULL) { 929 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 930 cx_ptr->res_rid); 931 device_printf(sc->cpu_dev, 932 "C1 I/O failed to allocate port %d, " 933 "degrading to C1 Halt", (int)address); 934 } 935 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 936 if (vendor == CST_FFH_VENDOR_INTEL || 937 (vendor == CST_FFH_VENDOR_AMD && cpu_mon_mwait_edx != 0)) 938 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 939 } 940 } 941 #endif 942 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 943 /* This is the first C1 state. Use the reserved slot. */ 944 sc->cpu_cx_states[0] = *cx_ptr; 945 } else { 946 sc->cpu_non_c2 = sc->cpu_cx_count; 947 sc->cpu_non_c3 = sc->cpu_cx_count; 948 cx_ptr++; 949 sc->cpu_cx_count++; 950 } 951 continue; 952 case ACPI_STATE_C2: 953 sc->cpu_non_c3 = sc->cpu_cx_count; 954 break; 955 case ACPI_STATE_C3: 956 default: 957 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 958 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 959 "acpi_cpu%d: C3[%d] not available.\n", 960 device_get_unit(sc->cpu_dev), i)); 961 continue; 962 } 963 break; 964 } 965 966 /* Free up any previous register. */ 967 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 968 969 /* Allocate the control register for C2 or C3. */ 970 #if defined(__i386__) || defined(__amd64__) 971 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 972 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 973 class == CST_FFH_INTEL_CL_MWAIT) { 974 /* Native C State Instruction use (mwait) */ 975 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 976 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 977 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 978 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 979 cx_ptr++; 980 sc->cpu_cx_count++; 981 } else 982 #endif 983 { 984 cx_ptr->res_rid = sc->cpu_cx_count; 985 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 986 cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 987 if (cx_ptr->p_lvlx) { 988 cx_ptr->do_mwait = false; 989 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 990 "acpi_cpu%d: Got C%d - %d latency\n", 991 device_get_unit(sc->cpu_dev), cx_ptr->type, 992 cx_ptr->trans_lat)); 993 cx_ptr++; 994 sc->cpu_cx_count++; 995 } 996 } 997 } 998 AcpiOsFree(buf.Pointer); 999 1000 /* If C1 state was not found, we need one now. */ 1001 cx_ptr = sc->cpu_cx_states; 1002 if (cx_ptr->type == ACPI_STATE_C0) { 1003 cx_ptr->type = ACPI_STATE_C1; 1004 cx_ptr->trans_lat = 0; 1005 } 1006 1007 return (0); 1008 } 1009 1010 /* 1011 * Call this *after* all CPUs have been attached. 1012 */ 1013 static void 1014 acpi_cpu_startup(void *arg) 1015 { 1016 struct acpi_cpu_softc *sc; 1017 int i; 1018 1019 /* 1020 * Setup any quirks that might necessary now that we have probed 1021 * all the CPUs 1022 */ 1023 acpi_cpu_quirks(); 1024 1025 if (cpu_cx_generic) { 1026 /* 1027 * We are using generic Cx mode, probe for available Cx states 1028 * for all processors. 1029 */ 1030 CPU_FOREACH(i) { 1031 if ((sc = cpu_softc[i]) != NULL) 1032 acpi_cpu_generic_cx_probe(sc); 1033 } 1034 } else { 1035 /* 1036 * We are using _CST mode, remove C3 state if necessary. 1037 * As we now know for sure that we will be using _CST mode 1038 * install our notify handler. 1039 */ 1040 CPU_FOREACH(i) { 1041 if ((sc = cpu_softc[i]) == NULL) 1042 continue; 1043 if (cpu_quirks & CPU_QUIRK_NO_C3) { 1044 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 1045 } 1046 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 1047 acpi_cpu_notify, sc); 1048 } 1049 } 1050 1051 /* Perform Cx final initialization. */ 1052 CPU_FOREACH(i) { 1053 if ((sc = cpu_softc[i]) != NULL) 1054 acpi_cpu_startup_cx(sc); 1055 } 1056 1057 /* Add a sysctl handler to handle global Cx lowest setting */ 1058 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 1059 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1060 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 1061 "Global lowest Cx sleep state to use"); 1062 1063 /* Take over idling from cpu_idle_default(). */ 1064 cpu_cx_lowest_lim = 0; 1065 CPU_FOREACH(i) { 1066 if ((sc = cpu_softc[i]) != NULL) 1067 enable_idle(sc); 1068 } 1069 #if defined(__i386__) || defined(__amd64__) 1070 cpu_idle_hook = acpi_cpu_idle; 1071 #endif 1072 } 1073 1074 static void 1075 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 1076 { 1077 struct sbuf sb; 1078 int i; 1079 1080 /* 1081 * Set up the list of Cx states 1082 */ 1083 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1084 SBUF_FIXEDLEN); 1085 for (i = 0; i < sc->cpu_cx_count; i++) 1086 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1087 sc->cpu_cx_states[i].trans_lat); 1088 sbuf_trim(&sb); 1089 sbuf_finish(&sb); 1090 } 1091 1092 static void 1093 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1094 { 1095 acpi_cpu_cx_list(sc); 1096 1097 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1098 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1099 OID_AUTO, "cx_supported", CTLFLAG_RD, 1100 sc->cpu_cx_supported, 0, 1101 "Cx/microsecond values for supported Cx states"); 1102 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1103 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1104 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1105 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1106 "lowest Cx sleep state to use"); 1107 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1108 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1109 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1110 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1111 "percent usage for each Cx state"); 1112 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1113 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1114 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1115 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1116 "Cx sleep state counters"); 1117 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1118 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1119 "cx_duration_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1120 (void *)sc, 0, acpi_cpu_duration_counters_sysctl, "A", 1121 "Cx sleep duration cumulative time"); 1122 1123 #if defined(__i386__) || defined(__amd64__) 1124 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1125 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1126 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1127 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods"); 1128 #endif 1129 1130 /* Signal platform that we can handle _CST notification. */ 1131 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1132 ACPI_LOCK(acpi); 1133 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1134 ACPI_UNLOCK(acpi); 1135 } 1136 } 1137 1138 #if defined(__i386__) || defined(__amd64__) 1139 /* 1140 * Idle the CPU in the lowest state possible. This function is called with 1141 * interrupts disabled. Note that once it re-enables interrupts, a task 1142 * switch can occur so do not access shared data (i.e. the softc) after 1143 * interrupts are re-enabled. 1144 */ 1145 static void 1146 acpi_cpu_idle(sbintime_t sbt) 1147 { 1148 struct acpi_cpu_softc *sc; 1149 struct acpi_cx *cx_next; 1150 uint64_t start_ticks, end_ticks; 1151 uint32_t start_time, end_time; 1152 ACPI_STATUS status; 1153 int bm_active, cx_next_idx, i, us; 1154 1155 /* 1156 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1157 * since there is no ACPI processor object for this CPU. This occurs 1158 * for logical CPUs in the HTT case. 1159 */ 1160 sc = cpu_softc[PCPU_GET(cpuid)]; 1161 if (sc == NULL) { 1162 acpi_cpu_c1(); 1163 return; 1164 } 1165 1166 /* If disabled, take the safe path. */ 1167 if (is_idle_disabled(sc)) { 1168 acpi_cpu_c1(); 1169 return; 1170 } 1171 1172 /* Find the lowest state that has small enough latency. */ 1173 us = sc->cpu_prev_sleep; 1174 if (sbt >= 0 && us > (sbt >> 12)) 1175 us = (sbt >> 12); 1176 cx_next_idx = 0; 1177 if (cpu_disable_c2_sleep) 1178 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1179 else if (cpu_disable_c3_sleep) 1180 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1181 else 1182 i = sc->cpu_cx_lowest; 1183 for (; i >= 0; i--) { 1184 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1185 cx_next_idx = i; 1186 break; 1187 } 1188 } 1189 1190 /* 1191 * Check for bus master activity. If there was activity, clear 1192 * the bit and use the lowest non-C3 state. Note that the USB 1193 * driver polling for new devices keeps this bit set all the 1194 * time if USB is loaded. 1195 */ 1196 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1197 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1198 cx_next_idx > sc->cpu_non_c3 && 1199 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) { 1200 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1201 if (ACPI_SUCCESS(status) && bm_active != 0) { 1202 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1203 cx_next_idx = sc->cpu_non_c3; 1204 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1205 } 1206 } 1207 1208 /* Select the next state and update statistics. */ 1209 sc->cpu_cx_stats[cx_next_idx]++; 1210 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1211 1212 /* 1213 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1214 * precisely calculate the time spent in C1 since the place we wake up 1215 * is an ISR. Assume we slept no more then half of quantum, unless 1216 * we are called inside critical section, delaying context switch. 1217 */ 1218 if (cx_next->type == ACPI_STATE_C1) { 1219 start_ticks = cpu_ticks(); 1220 if (cx_next->p_lvlx != NULL) { 1221 /* C1 I/O then Halt */ 1222 CPU_GET_REG(cx_next->p_lvlx, 1); 1223 } 1224 if (cx_next->do_mwait) 1225 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1226 else 1227 acpi_cpu_c1(); 1228 end_ticks = cpu_ticks(); 1229 /* acpi_cpu_c1() returns with interrupts enabled. */ 1230 if (cx_next->do_mwait) 1231 ACPI_ENABLE_IRQS(); 1232 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1233 if (!cx_next->do_mwait && curthread->td_critnest == 0) 1234 end_time = min(end_time, 500000 / hz); 1235 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1236 sc->cpu_cx_duration[cx_next_idx] += end_time; 1237 return; 1238 } 1239 1240 /* 1241 * For C3, disable bus master arbitration if BM control is available. 1242 * CPU may have to wake up to handle it. Otherwise flush the CPU cache. 1243 */ 1244 if (cx_next->type == ACPI_STATE_C3) { 1245 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 1246 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1247 else 1248 ACPI_FLUSH_CPU_CACHE(); 1249 } 1250 1251 /* 1252 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1253 * Use the ACPI timer for measuring sleep time. Since we need to 1254 * get the time very close to the CPU start/stop clock logic, this 1255 * is the only reliable time source. 1256 */ 1257 if (cx_next->type == ACPI_STATE_C3) { 1258 AcpiGetTimer(&start_time); 1259 start_ticks = 0; 1260 } else { 1261 start_time = 0; 1262 start_ticks = cpu_ticks(); 1263 } 1264 if (cx_next->do_mwait) { 1265 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1266 } else { 1267 CPU_GET_REG(cx_next->p_lvlx, 1); 1268 /* 1269 * Read the end time twice. Since it may take an arbitrary time 1270 * to enter the idle state, the first read may be executed before 1271 * the processor has stopped. Doing it again provides enough 1272 * margin that we are certain to have a correct value. 1273 */ 1274 AcpiGetTimer(&end_time); 1275 } 1276 1277 if (cx_next->type == ACPI_STATE_C3) 1278 AcpiGetTimer(&end_time); 1279 else 1280 end_ticks = cpu_ticks(); 1281 1282 /* Enable bus master arbitration. */ 1283 if (cx_next->type == ACPI_STATE_C3 && 1284 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 1285 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1286 ACPI_ENABLE_IRQS(); 1287 1288 if (cx_next->type == ACPI_STATE_C3) 1289 AcpiGetTimerDuration(start_time, end_time, &end_time); 1290 else 1291 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1292 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1293 sc->cpu_cx_duration[cx_next_idx] += end_time; 1294 } 1295 #endif 1296 1297 /* 1298 * Re-evaluate the _CST object when we are notified that it changed. 1299 */ 1300 static void 1301 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1302 { 1303 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1304 1305 if (notify != ACPI_NOTIFY_CX_STATES) 1306 return; 1307 1308 /* 1309 * C-state data for target CPU is going to be in flux while we execute 1310 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1311 * Also, it may happen that multiple ACPI taskqueues may concurrently 1312 * execute notifications for the same CPU. ACPI_SERIAL is used to 1313 * protect against that. 1314 */ 1315 ACPI_SERIAL_BEGIN(cpu); 1316 disable_idle(sc); 1317 1318 /* Update the list of Cx states. */ 1319 acpi_cpu_cx_cst(sc); 1320 acpi_cpu_cx_list(sc); 1321 acpi_cpu_set_cx_lowest(sc); 1322 1323 enable_idle(sc); 1324 ACPI_SERIAL_END(cpu); 1325 1326 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1327 } 1328 1329 static void 1330 acpi_cpu_quirks(void) 1331 { 1332 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1333 1334 /* 1335 * Bus mastering arbitration control is needed to keep caches coherent 1336 * while sleeping in C3. If it's not present but a working flush cache 1337 * instruction is present, flush the caches before entering C3 instead. 1338 * Otherwise, just disable C3 completely. 1339 */ 1340 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1341 AcpiGbl_FADT.Pm2ControlLength == 0) { 1342 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1343 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1344 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1345 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1346 "acpi_cpu: no BM control, using flush cache method\n")); 1347 } else { 1348 cpu_quirks |= CPU_QUIRK_NO_C3; 1349 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1350 "acpi_cpu: no BM control, C3 not available\n")); 1351 } 1352 } 1353 1354 /* 1355 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1356 * the expensive flush cache instruction. 1357 */ 1358 if (cpu_cx_generic && mp_ncpus > 1) { 1359 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1360 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1361 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1362 } 1363 1364 /* Look for various quirks of the PIIX4 part. */ 1365 acpi_cpu_quirks_piix4(); 1366 } 1367 1368 static void 1369 acpi_cpu_quirks_piix4(void) 1370 { 1371 #ifdef __i386__ 1372 device_t acpi_dev; 1373 uint32_t val; 1374 ACPI_STATUS status; 1375 1376 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1377 if (acpi_dev != NULL) { 1378 switch (pci_get_revid(acpi_dev)) { 1379 /* 1380 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1381 * do not report the BMIDE status to the BM status register and 1382 * others have a livelock bug if Type-F DMA is enabled. Linux 1383 * works around the BMIDE bug by reading the BM status directly 1384 * but we take the simpler approach of disabling C3 for these 1385 * parts. 1386 * 1387 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1388 * Livelock") from the January 2002 PIIX4 specification update. 1389 * Applies to all PIIX4 models. 1390 * 1391 * Also, make sure that all interrupts cause a "Stop Break" 1392 * event to exit from C2 state. 1393 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1394 * should be set to zero, otherwise it causes C2 to short-sleep. 1395 * PIIX4 doesn't properly support C3 and bus master activity 1396 * need not break out of C2. 1397 */ 1398 case PCI_REVISION_A_STEP: 1399 case PCI_REVISION_B_STEP: 1400 case PCI_REVISION_4E: 1401 case PCI_REVISION_4M: 1402 cpu_quirks |= CPU_QUIRK_NO_C3; 1403 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1404 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1405 1406 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1407 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1408 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1409 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1410 val |= PIIX4_STOP_BREAK_MASK; 1411 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1412 } 1413 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1414 if (ACPI_SUCCESS(status) && val != 0) { 1415 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1416 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1417 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1418 } 1419 break; 1420 default: 1421 break; 1422 } 1423 } 1424 #endif 1425 } 1426 1427 static int 1428 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1429 { 1430 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1431 struct sbuf sb; 1432 char buf[128]; 1433 int error, i; 1434 uintmax_t fract, sum, whole; 1435 1436 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1437 sum = 0; 1438 for (i = 0; i < sc->cpu_cx_count; i++) 1439 sum += sc->cpu_cx_stats[i]; 1440 for (i = 0; i < sc->cpu_cx_count; i++) { 1441 if (sum > 0) { 1442 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1443 fract = (whole % sum) * 100; 1444 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1445 (u_int)(fract / sum)); 1446 } else 1447 sbuf_printf(&sb, "0.00%% "); 1448 } 1449 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1450 error = sbuf_finish(&sb); 1451 sbuf_delete(&sb); 1452 return (error); 1453 } 1454 1455 /* 1456 * XXX TODO: actually add support to count each entry/exit 1457 * from the Cx states. 1458 */ 1459 static int 1460 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1461 { 1462 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1463 struct sbuf sb; 1464 char buf[128]; 1465 int error, i; 1466 1467 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1468 for (i = 0; i < sc->cpu_cx_count; i++) { 1469 if (i > 0) 1470 sbuf_putc(&sb, ' '); 1471 sbuf_printf(&sb, "%u", sc->cpu_cx_stats[i]); 1472 } 1473 error = sbuf_finish(&sb); 1474 sbuf_delete(&sb); 1475 return (error); 1476 } 1477 1478 static int 1479 acpi_cpu_duration_counters_sysctl(SYSCTL_HANDLER_ARGS) 1480 { 1481 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1482 struct sbuf sb; 1483 char buf[128]; 1484 int error, i; 1485 1486 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1487 for (i = 0; i < sc->cpu_cx_count; i++) { 1488 if (i > 0) 1489 sbuf_putc(&sb, ' '); 1490 sbuf_printf(&sb, "%ju", (uintmax_t) sc->cpu_cx_duration[i]); 1491 } 1492 error = sbuf_finish(&sb); 1493 sbuf_delete(&sb); 1494 return (error); 1495 } 1496 1497 1498 #if defined(__i386__) || defined(__amd64__) 1499 static int 1500 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1501 { 1502 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1503 struct acpi_cx *cx; 1504 struct sbuf sb; 1505 char buf[128]; 1506 int error, i; 1507 1508 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1509 for (i = 0; i < sc->cpu_cx_count; i++) { 1510 cx = &sc->cpu_cx_states[i]; 1511 if (i > 0) 1512 sbuf_putc(&sb, ' '); 1513 sbuf_printf(&sb, "C%d/", i + 1); 1514 if (cx->do_mwait) { 1515 sbuf_cat(&sb, "mwait"); 1516 if (cx->mwait_hw_coord) 1517 sbuf_cat(&sb, "/hwc"); 1518 if (cx->mwait_bm_avoidance) 1519 sbuf_cat(&sb, "/bma"); 1520 } else if (cx->type == ACPI_STATE_C1) { 1521 sbuf_cat(&sb, "hlt"); 1522 } else { 1523 sbuf_cat(&sb, "io"); 1524 } 1525 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1526 sbuf_cat(&sb, "/iohlt"); 1527 } 1528 error = sbuf_finish(&sb); 1529 sbuf_delete(&sb); 1530 return (error); 1531 } 1532 #endif 1533 1534 static int 1535 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1536 { 1537 int i; 1538 1539 ACPI_SERIAL_ASSERT(cpu); 1540 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1541 1542 /* If not disabling, cache the new lowest non-C3 state. */ 1543 sc->cpu_non_c3 = 0; 1544 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1545 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1546 sc->cpu_non_c3 = i; 1547 break; 1548 } 1549 } 1550 1551 /* Reset the statistics counters. */ 1552 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1553 return (0); 1554 } 1555 1556 static int 1557 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1558 { 1559 struct acpi_cpu_softc *sc; 1560 char state[8]; 1561 int val, error; 1562 1563 sc = (struct acpi_cpu_softc *) arg1; 1564 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1565 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1566 if (error != 0 || req->newptr == NULL) 1567 return (error); 1568 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1569 return (EINVAL); 1570 if (strcasecmp(state, "Cmax") == 0) 1571 val = MAX_CX_STATES; 1572 else { 1573 val = (int) strtol(state + 1, NULL, 10); 1574 if (val < 1 || val > MAX_CX_STATES) 1575 return (EINVAL); 1576 } 1577 1578 ACPI_SERIAL_BEGIN(cpu); 1579 sc->cpu_cx_lowest_lim = val - 1; 1580 acpi_cpu_set_cx_lowest(sc); 1581 ACPI_SERIAL_END(cpu); 1582 1583 return (0); 1584 } 1585 1586 static int 1587 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1588 { 1589 struct acpi_cpu_softc *sc; 1590 char state[8]; 1591 int val, error, i; 1592 1593 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1594 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1595 if (error != 0 || req->newptr == NULL) 1596 return (error); 1597 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1598 return (EINVAL); 1599 if (strcasecmp(state, "Cmax") == 0) 1600 val = MAX_CX_STATES; 1601 else { 1602 val = (int) strtol(state + 1, NULL, 10); 1603 if (val < 1 || val > MAX_CX_STATES) 1604 return (EINVAL); 1605 } 1606 1607 /* Update the new lowest useable Cx state for all CPUs. */ 1608 ACPI_SERIAL_BEGIN(cpu); 1609 cpu_cx_lowest_lim = val - 1; 1610 CPU_FOREACH(i) { 1611 if ((sc = cpu_softc[i]) == NULL) 1612 continue; 1613 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1614 acpi_cpu_set_cx_lowest(sc); 1615 } 1616 ACPI_SERIAL_END(cpu); 1617 1618 return (0); 1619 } 1620