1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 118 119 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 120 121 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 122 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 123 124 #define PCI_VENDOR_INTEL 0x8086 125 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 126 #define PCI_REVISION_A_STEP 0 127 #define PCI_REVISION_B_STEP 1 128 #define PCI_REVISION_4E 2 129 #define PCI_REVISION_4M 3 130 #define PIIX4_DEVACTB_REG 0x58 131 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 132 #define PIIX4_BRLD_EN_IRQ (1<<1) 133 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 134 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 135 #define PIIX4_PCNTRL_BST_EN (1<<10) 136 137 #define CST_FFH_VENDOR_INTEL 1 138 #define CST_FFH_INTEL_CL_C1IO 1 139 #define CST_FFH_INTEL_CL_MWAIT 2 140 #define CST_FFH_MWAIT_HW_COORD 0x0001 141 #define CST_FFH_MWAIT_BM_AVOID 0x0002 142 143 /* Allow users to ignore processor orders in MADT. */ 144 static int cpu_unordered; 145 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN, 146 &cpu_unordered, 0, 147 "Do not use the MADT to match ACPI Processor objects to CPUs."); 148 149 /* Knob to disable acpi_cpu devices */ 150 bool acpi_cpu_disabled = false; 151 152 /* Platform hardware resource information. */ 153 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 154 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 155 static int cpu_quirks; /* Indicate any hardware bugs. */ 156 157 /* Values for sysctl. */ 158 static struct sysctl_ctx_list cpu_sysctl_ctx; 159 static struct sysctl_oid *cpu_sysctl_tree; 160 static int cpu_cx_generic; 161 static int cpu_cx_lowest_lim; 162 163 static device_t *cpu_devices; 164 static int cpu_ndevices; 165 static struct acpi_cpu_softc **cpu_softc; 166 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 167 168 static int acpi_cpu_probe(device_t dev); 169 static int acpi_cpu_attach(device_t dev); 170 static int acpi_cpu_suspend(device_t dev); 171 static int acpi_cpu_resume(device_t dev); 172 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, 173 uint32_t *cpu_id); 174 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 175 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 176 int unit); 177 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 178 uintptr_t *result); 179 static int acpi_cpu_shutdown(device_t dev); 180 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 181 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 182 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 183 static void acpi_cpu_startup(void *arg); 184 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 185 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 186 static void acpi_cpu_idle(sbintime_t sbt); 187 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 188 static int acpi_cpu_quirks(void); 189 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 190 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 191 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 192 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 193 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 194 #if defined(__i386__) || defined(__amd64__) 195 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 196 #endif 197 198 static device_method_t acpi_cpu_methods[] = { 199 /* Device interface */ 200 DEVMETHOD(device_probe, acpi_cpu_probe), 201 DEVMETHOD(device_attach, acpi_cpu_attach), 202 DEVMETHOD(device_detach, bus_generic_detach), 203 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 204 DEVMETHOD(device_suspend, acpi_cpu_suspend), 205 DEVMETHOD(device_resume, acpi_cpu_resume), 206 207 /* Bus interface */ 208 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 209 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 210 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 211 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 212 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 213 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 214 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 215 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 216 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 217 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 218 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 219 220 DEVMETHOD_END 221 }; 222 223 static driver_t acpi_cpu_driver = { 224 "cpu", 225 acpi_cpu_methods, 226 sizeof(struct acpi_cpu_softc), 227 }; 228 229 static devclass_t acpi_cpu_devclass; 230 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 231 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 232 233 static int 234 acpi_cpu_probe(device_t dev) 235 { 236 int acpi_id, cpu_id; 237 ACPI_BUFFER buf; 238 ACPI_HANDLE handle; 239 ACPI_OBJECT *obj; 240 ACPI_STATUS status; 241 242 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR || 243 acpi_cpu_disabled) 244 return (ENXIO); 245 246 handle = acpi_get_handle(dev); 247 if (cpu_softc == NULL) 248 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 249 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 250 251 /* Get our Processor object. */ 252 buf.Pointer = NULL; 253 buf.Length = ACPI_ALLOCATE_BUFFER; 254 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 255 if (ACPI_FAILURE(status)) { 256 device_printf(dev, "probe failed to get Processor obj - %s\n", 257 AcpiFormatException(status)); 258 return (ENXIO); 259 } 260 obj = (ACPI_OBJECT *)buf.Pointer; 261 if (obj->Type != ACPI_TYPE_PROCESSOR) { 262 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 263 AcpiOsFree(obj); 264 return (ENXIO); 265 } 266 267 /* 268 * Find the processor associated with our unit. We could use the 269 * ProcId as a key, however, some boxes do not have the same values 270 * in their Processor object as the ProcId values in the MADT. 271 */ 272 acpi_id = obj->Processor.ProcId; 273 AcpiOsFree(obj); 274 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0) 275 return (ENXIO); 276 277 /* 278 * Check if we already probed this processor. We scan the bus twice 279 * so it's possible we've already seen this one. 280 */ 281 if (cpu_softc[cpu_id] != NULL) 282 return (ENXIO); 283 284 /* Mark this processor as in-use and save our derived id for attach. */ 285 cpu_softc[cpu_id] = (void *)1; 286 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 287 device_set_desc(dev, "ACPI CPU"); 288 289 return (0); 290 } 291 292 static int 293 acpi_cpu_attach(device_t dev) 294 { 295 ACPI_BUFFER buf; 296 ACPI_OBJECT arg[4], *obj; 297 ACPI_OBJECT_LIST arglist; 298 struct pcpu *pcpu_data; 299 struct acpi_cpu_softc *sc; 300 struct acpi_softc *acpi_sc; 301 ACPI_STATUS status; 302 u_int features; 303 int cpu_id, drv_count, i; 304 driver_t **drivers; 305 uint32_t cap_set[3]; 306 307 /* UUID needed by _OSC evaluation */ 308 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 309 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 310 0x58, 0x71, 0x39, 0x53 }; 311 312 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 313 314 sc = device_get_softc(dev); 315 sc->cpu_dev = dev; 316 sc->cpu_handle = acpi_get_handle(dev); 317 cpu_id = (int)(intptr_t)acpi_get_private(dev); 318 cpu_softc[cpu_id] = sc; 319 pcpu_data = pcpu_find(cpu_id); 320 pcpu_data->pc_device = dev; 321 sc->cpu_pcpu = pcpu_data; 322 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 323 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 324 325 buf.Pointer = NULL; 326 buf.Length = ACPI_ALLOCATE_BUFFER; 327 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 328 if (ACPI_FAILURE(status)) { 329 device_printf(dev, "attach failed to get Processor obj - %s\n", 330 AcpiFormatException(status)); 331 return (ENXIO); 332 } 333 obj = (ACPI_OBJECT *)buf.Pointer; 334 sc->cpu_p_blk = obj->Processor.PblkAddress; 335 sc->cpu_p_blk_len = obj->Processor.PblkLength; 336 sc->cpu_acpi_id = obj->Processor.ProcId; 337 AcpiOsFree(obj); 338 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 339 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 340 341 /* 342 * If this is the first cpu we attach, create and initialize the generic 343 * resources that will be used by all acpi cpu devices. 344 */ 345 if (device_get_unit(dev) == 0) { 346 /* Assume we won't be using generic Cx mode by default */ 347 cpu_cx_generic = FALSE; 348 349 /* Install hw.acpi.cpu sysctl tree */ 350 acpi_sc = acpi_device_get_parent_softc(dev); 351 sysctl_ctx_init(&cpu_sysctl_ctx); 352 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 353 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 354 CTLFLAG_RD, 0, "node for CPU children"); 355 356 /* Queue post cpu-probing task handler */ 357 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 358 } 359 360 /* 361 * Before calling any CPU methods, collect child driver feature hints 362 * and notify ACPI of them. We support unified SMP power control 363 * so advertise this ourselves. Note this is not the same as independent 364 * SMP control where each CPU can have different settings. 365 */ 366 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 367 ACPI_CAP_C1_IO_HALT; 368 369 #if defined(__i386__) || defined(__amd64__) 370 /* 371 * Ask for MWAIT modes if not disabled and interrupts work 372 * reasonable with MWAIT. 373 */ 374 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 375 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 376 #endif 377 378 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 379 for (i = 0; i < drv_count; i++) { 380 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 381 sc->cpu_features |= features; 382 } 383 free(drivers, M_TEMP); 384 } 385 386 /* 387 * CPU capabilities are specified in 388 * Intel Processor Vendor-Specific ACPI Interface Specification. 389 */ 390 if (sc->cpu_features) { 391 arglist.Pointer = arg; 392 arglist.Count = 4; 393 arg[0].Type = ACPI_TYPE_BUFFER; 394 arg[0].Buffer.Length = sizeof(cpu_oscuuid); 395 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */ 396 arg[1].Type = ACPI_TYPE_INTEGER; 397 arg[1].Integer.Value = 1; /* revision */ 398 arg[2].Type = ACPI_TYPE_INTEGER; 399 arg[2].Integer.Value = 1; /* count */ 400 arg[3].Type = ACPI_TYPE_BUFFER; 401 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */ 402 arg[3].Buffer.Pointer = (uint8_t *)cap_set; 403 cap_set[0] = 0; /* status */ 404 cap_set[1] = sc->cpu_features; 405 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL); 406 if (ACPI_SUCCESS(status)) { 407 if (cap_set[0] != 0) 408 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 409 } 410 else { 411 arglist.Pointer = arg; 412 arglist.Count = 1; 413 arg[0].Type = ACPI_TYPE_BUFFER; 414 arg[0].Buffer.Length = sizeof(cap_set); 415 arg[0].Buffer.Pointer = (uint8_t *)cap_set; 416 cap_set[0] = 1; /* revision */ 417 cap_set[1] = 1; /* number of capabilities integers */ 418 cap_set[2] = sc->cpu_features; 419 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 420 } 421 } 422 423 /* Probe for Cx state support. */ 424 acpi_cpu_cx_probe(sc); 425 426 return (0); 427 } 428 429 static void 430 acpi_cpu_postattach(void *unused __unused) 431 { 432 device_t *devices; 433 int err; 434 int i, n; 435 436 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 437 if (err != 0) { 438 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 439 return; 440 } 441 for (i = 0; i < n; i++) 442 bus_generic_probe(devices[i]); 443 for (i = 0; i < n; i++) 444 bus_generic_attach(devices[i]); 445 free(devices, M_TEMP); 446 } 447 448 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 449 acpi_cpu_postattach, NULL); 450 451 static void 452 disable_idle(struct acpi_cpu_softc *sc) 453 { 454 cpuset_t cpuset; 455 456 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 457 sc->cpu_disable_idle = TRUE; 458 459 /* 460 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 461 * Note that this code depends on the fact that the rendezvous IPI 462 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 463 * is called and executed in such a context with interrupts being re-enabled 464 * right before return. 465 */ 466 smp_rendezvous_cpus(cpuset, smp_no_rendevous_barrier, NULL, 467 smp_no_rendevous_barrier, NULL); 468 } 469 470 static void 471 enable_idle(struct acpi_cpu_softc *sc) 472 { 473 474 sc->cpu_disable_idle = FALSE; 475 } 476 477 static int 478 is_idle_disabled(struct acpi_cpu_softc *sc) 479 { 480 481 return (sc->cpu_disable_idle); 482 } 483 484 /* 485 * Disable any entry to the idle function during suspend and re-enable it 486 * during resume. 487 */ 488 static int 489 acpi_cpu_suspend(device_t dev) 490 { 491 int error; 492 493 error = bus_generic_suspend(dev); 494 if (error) 495 return (error); 496 disable_idle(device_get_softc(dev)); 497 return (0); 498 } 499 500 static int 501 acpi_cpu_resume(device_t dev) 502 { 503 504 enable_idle(device_get_softc(dev)); 505 return (bus_generic_resume(dev)); 506 } 507 508 /* 509 * Find the processor associated with a given ACPI ID. By default, 510 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a 511 * processor. Some systems have inconsistent ASL and MADT however. 512 * For these systems the cpu_unordered tunable can be set in which 513 * case we assume that Processor objects are listed in the same order 514 * in both the MADT and ASL. 515 */ 516 static int 517 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id) 518 { 519 struct pcpu *pc; 520 uint32_t i, idx; 521 522 KASSERT(acpi_id != NULL, ("Null acpi_id")); 523 KASSERT(cpu_id != NULL, ("Null cpu_id")); 524 idx = device_get_unit(dev); 525 526 /* 527 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 528 * UP box) use the ACPI ID from the first processor we find. 529 */ 530 if (idx == 0 && mp_ncpus == 1) { 531 pc = pcpu_find(0); 532 if (pc->pc_acpi_id == 0xffffffff) 533 pc->pc_acpi_id = *acpi_id; 534 *cpu_id = 0; 535 return (0); 536 } 537 538 CPU_FOREACH(i) { 539 pc = pcpu_find(i); 540 KASSERT(pc != NULL, ("no pcpu data for %d", i)); 541 if (cpu_unordered) { 542 if (idx-- == 0) { 543 /* 544 * If pc_acpi_id doesn't match the ACPI ID from the 545 * ASL, prefer the MADT-derived value. 546 */ 547 if (pc->pc_acpi_id != *acpi_id) 548 *acpi_id = pc->pc_acpi_id; 549 *cpu_id = pc->pc_cpuid; 550 return (0); 551 } 552 } else { 553 if (pc->pc_acpi_id == *acpi_id) { 554 if (bootverbose) 555 device_printf(dev, 556 "Processor %s (ACPI ID %u) -> APIC ID %d\n", 557 acpi_name(acpi_get_handle(dev)), *acpi_id, 558 pc->pc_cpuid); 559 *cpu_id = pc->pc_cpuid; 560 return (0); 561 } 562 } 563 } 564 565 if (bootverbose) 566 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 567 acpi_name(acpi_get_handle(dev)), *acpi_id); 568 569 return (ESRCH); 570 } 571 572 static struct resource_list * 573 acpi_cpu_get_rlist(device_t dev, device_t child) 574 { 575 struct acpi_cpu_device *ad; 576 577 ad = device_get_ivars(child); 578 if (ad == NULL) 579 return (NULL); 580 return (&ad->ad_rl); 581 } 582 583 static device_t 584 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 585 { 586 struct acpi_cpu_device *ad; 587 device_t child; 588 589 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 590 return (NULL); 591 592 resource_list_init(&ad->ad_rl); 593 594 child = device_add_child_ordered(dev, order, name, unit); 595 if (child != NULL) 596 device_set_ivars(child, ad); 597 else 598 free(ad, M_TEMP); 599 return (child); 600 } 601 602 static int 603 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 604 { 605 struct acpi_cpu_softc *sc; 606 607 sc = device_get_softc(dev); 608 switch (index) { 609 case ACPI_IVAR_HANDLE: 610 *result = (uintptr_t)sc->cpu_handle; 611 break; 612 case CPU_IVAR_PCPU: 613 *result = (uintptr_t)sc->cpu_pcpu; 614 break; 615 #if defined(__amd64__) || defined(__i386__) 616 case CPU_IVAR_NOMINAL_MHZ: 617 if (tsc_is_invariant) { 618 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 619 break; 620 } 621 /* FALLTHROUGH */ 622 #endif 623 default: 624 return (ENOENT); 625 } 626 return (0); 627 } 628 629 static int 630 acpi_cpu_shutdown(device_t dev) 631 { 632 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 633 634 /* Allow children to shutdown first. */ 635 bus_generic_shutdown(dev); 636 637 /* 638 * Disable any entry to the idle function. 639 */ 640 disable_idle(device_get_softc(dev)); 641 642 /* 643 * CPU devices are not truely detached and remain referenced, 644 * so their resources are not freed. 645 */ 646 647 return_VALUE (0); 648 } 649 650 static void 651 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 652 { 653 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 654 655 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 656 sc->cpu_prev_sleep = 1000000; 657 sc->cpu_cx_lowest = 0; 658 sc->cpu_cx_lowest_lim = 0; 659 660 /* 661 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 662 * any, we'll revert to generic FADT/P_BLK Cx control method which will 663 * be handled by acpi_cpu_startup. We need to defer to after having 664 * probed all the cpus in the system before probing for generic Cx 665 * states as we may already have found cpus with valid _CST packages 666 */ 667 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 668 /* 669 * We were unable to find a _CST package for this cpu or there 670 * was an error parsing it. Switch back to generic mode. 671 */ 672 cpu_cx_generic = TRUE; 673 if (bootverbose) 674 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 675 } 676 677 /* 678 * TODO: _CSD Package should be checked here. 679 */ 680 } 681 682 static void 683 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 684 { 685 ACPI_GENERIC_ADDRESS gas; 686 struct acpi_cx *cx_ptr; 687 688 sc->cpu_cx_count = 0; 689 cx_ptr = sc->cpu_cx_states; 690 691 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 692 sc->cpu_prev_sleep = 1000000; 693 694 /* C1 has been required since just after ACPI 1.0 */ 695 cx_ptr->type = ACPI_STATE_C1; 696 cx_ptr->trans_lat = 0; 697 cx_ptr++; 698 sc->cpu_non_c2 = sc->cpu_cx_count; 699 sc->cpu_non_c3 = sc->cpu_cx_count; 700 sc->cpu_cx_count++; 701 cpu_deepest_sleep = 1; 702 703 /* 704 * The spec says P_BLK must be 6 bytes long. However, some systems 705 * use it to indicate a fractional set of features present so we 706 * take 5 as C2. Some may also have a value of 7 to indicate 707 * another C3 but most use _CST for this (as required) and having 708 * "only" C1-C3 is not a hardship. 709 */ 710 if (sc->cpu_p_blk_len < 5) 711 return; 712 713 /* Validate and allocate resources for C2 (P_LVL2). */ 714 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 715 gas.BitWidth = 8; 716 if (AcpiGbl_FADT.C2Latency <= 100) { 717 gas.Address = sc->cpu_p_blk + 4; 718 cx_ptr->res_rid = 0; 719 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 720 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 721 if (cx_ptr->p_lvlx != NULL) { 722 cx_ptr->type = ACPI_STATE_C2; 723 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 724 cx_ptr++; 725 sc->cpu_non_c3 = sc->cpu_cx_count; 726 sc->cpu_cx_count++; 727 cpu_deepest_sleep = 2; 728 } 729 } 730 if (sc->cpu_p_blk_len < 6) 731 return; 732 733 /* Validate and allocate resources for C3 (P_LVL3). */ 734 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 735 gas.Address = sc->cpu_p_blk + 5; 736 cx_ptr->res_rid = 1; 737 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 738 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 739 if (cx_ptr->p_lvlx != NULL) { 740 cx_ptr->type = ACPI_STATE_C3; 741 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 742 cx_ptr++; 743 sc->cpu_cx_count++; 744 cpu_deepest_sleep = 3; 745 } 746 } 747 } 748 749 #if defined(__i386__) || defined(__amd64__) 750 static void 751 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 752 { 753 754 cx_ptr->do_mwait = true; 755 cx_ptr->mwait_hint = address & 0xffffffff; 756 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 757 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 758 } 759 #endif 760 761 static void 762 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 763 { 764 765 if (cx_ptr->p_lvlx == NULL) 766 return; 767 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 768 cx_ptr->p_lvlx); 769 cx_ptr->p_lvlx = NULL; 770 } 771 772 /* 773 * Parse a _CST package and set up its Cx states. Since the _CST object 774 * can change dynamically, our notify handler may call this function 775 * to clean up and probe the new _CST package. 776 */ 777 static int 778 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 779 { 780 struct acpi_cx *cx_ptr; 781 ACPI_STATUS status; 782 ACPI_BUFFER buf; 783 ACPI_OBJECT *top; 784 ACPI_OBJECT *pkg; 785 uint32_t count; 786 int i; 787 #if defined(__i386__) || defined(__amd64__) 788 uint64_t address; 789 int vendor, class, accsize; 790 #endif 791 792 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 793 794 buf.Pointer = NULL; 795 buf.Length = ACPI_ALLOCATE_BUFFER; 796 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 797 if (ACPI_FAILURE(status)) 798 return (ENXIO); 799 800 /* _CST is a package with a count and at least one Cx package. */ 801 top = (ACPI_OBJECT *)buf.Pointer; 802 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 803 device_printf(sc->cpu_dev, "invalid _CST package\n"); 804 AcpiOsFree(buf.Pointer); 805 return (ENXIO); 806 } 807 if (count != top->Package.Count - 1) { 808 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 809 count, top->Package.Count - 1); 810 count = top->Package.Count - 1; 811 } 812 if (count > MAX_CX_STATES) { 813 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 814 count = MAX_CX_STATES; 815 } 816 817 sc->cpu_non_c2 = 0; 818 sc->cpu_non_c3 = 0; 819 sc->cpu_cx_count = 0; 820 cx_ptr = sc->cpu_cx_states; 821 822 /* 823 * C1 has been required since just after ACPI 1.0. 824 * Reserve the first slot for it. 825 */ 826 cx_ptr->type = ACPI_STATE_C0; 827 cx_ptr++; 828 sc->cpu_cx_count++; 829 cpu_deepest_sleep = 1; 830 831 /* Set up all valid states. */ 832 for (i = 0; i < count; i++) { 833 pkg = &top->Package.Elements[i + 1]; 834 if (!ACPI_PKG_VALID(pkg, 4) || 835 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 836 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 837 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 838 839 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 840 continue; 841 } 842 843 /* Validate the state to see if we should use it. */ 844 switch (cx_ptr->type) { 845 case ACPI_STATE_C1: 846 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 847 #if defined(__i386__) || defined(__amd64__) 848 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 849 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 850 if (class == CST_FFH_INTEL_CL_C1IO) { 851 /* C1 I/O then Halt */ 852 cx_ptr->res_rid = sc->cpu_cx_count; 853 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 854 cx_ptr->res_rid, address, 1); 855 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 856 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 857 RF_SHAREABLE); 858 if (cx_ptr->p_lvlx == NULL) { 859 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 860 cx_ptr->res_rid); 861 device_printf(sc->cpu_dev, 862 "C1 I/O failed to allocate port %d, " 863 "degrading to C1 Halt", (int)address); 864 } 865 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 866 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 867 } 868 } 869 #endif 870 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 871 /* This is the first C1 state. Use the reserved slot. */ 872 sc->cpu_cx_states[0] = *cx_ptr; 873 } else { 874 sc->cpu_non_c2 = sc->cpu_cx_count; 875 sc->cpu_non_c3 = sc->cpu_cx_count; 876 cx_ptr++; 877 sc->cpu_cx_count++; 878 } 879 continue; 880 case ACPI_STATE_C2: 881 sc->cpu_non_c3 = sc->cpu_cx_count; 882 if (cpu_deepest_sleep < 2) 883 cpu_deepest_sleep = 2; 884 break; 885 case ACPI_STATE_C3: 886 default: 887 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 888 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 889 "acpi_cpu%d: C3[%d] not available.\n", 890 device_get_unit(sc->cpu_dev), i)); 891 continue; 892 } else 893 cpu_deepest_sleep = 3; 894 break; 895 } 896 897 /* Free up any previous register. */ 898 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 899 900 /* Allocate the control register for C2 or C3. */ 901 #if defined(__i386__) || defined(__amd64__) 902 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 903 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 904 class == CST_FFH_INTEL_CL_MWAIT) { 905 /* Native C State Instruction use (mwait) */ 906 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 907 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 908 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 909 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 910 cx_ptr++; 911 sc->cpu_cx_count++; 912 } else 913 #endif 914 { 915 cx_ptr->res_rid = sc->cpu_cx_count; 916 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 917 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 918 if (cx_ptr->p_lvlx) { 919 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 920 "acpi_cpu%d: Got C%d - %d latency\n", 921 device_get_unit(sc->cpu_dev), cx_ptr->type, 922 cx_ptr->trans_lat)); 923 cx_ptr++; 924 sc->cpu_cx_count++; 925 } 926 } 927 } 928 AcpiOsFree(buf.Pointer); 929 930 /* If C1 state was not found, we need one now. */ 931 cx_ptr = sc->cpu_cx_states; 932 if (cx_ptr->type == ACPI_STATE_C0) { 933 cx_ptr->type = ACPI_STATE_C1; 934 cx_ptr->trans_lat = 0; 935 } 936 937 return (0); 938 } 939 940 /* 941 * Call this *after* all CPUs have been attached. 942 */ 943 static void 944 acpi_cpu_startup(void *arg) 945 { 946 struct acpi_cpu_softc *sc; 947 int i; 948 949 /* Get set of CPU devices */ 950 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 951 952 /* 953 * Setup any quirks that might necessary now that we have probed 954 * all the CPUs 955 */ 956 acpi_cpu_quirks(); 957 958 if (cpu_cx_generic) { 959 /* 960 * We are using generic Cx mode, probe for available Cx states 961 * for all processors. 962 */ 963 for (i = 0; i < cpu_ndevices; i++) { 964 sc = device_get_softc(cpu_devices[i]); 965 acpi_cpu_generic_cx_probe(sc); 966 } 967 } else { 968 /* 969 * We are using _CST mode, remove C3 state if necessary. 970 * As we now know for sure that we will be using _CST mode 971 * install our notify handler. 972 */ 973 for (i = 0; i < cpu_ndevices; i++) { 974 sc = device_get_softc(cpu_devices[i]); 975 if (cpu_quirks & CPU_QUIRK_NO_C3) { 976 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 977 } 978 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 979 acpi_cpu_notify, sc); 980 } 981 } 982 983 /* Perform Cx final initialization. */ 984 for (i = 0; i < cpu_ndevices; i++) { 985 sc = device_get_softc(cpu_devices[i]); 986 acpi_cpu_startup_cx(sc); 987 } 988 989 /* Add a sysctl handler to handle global Cx lowest setting */ 990 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 991 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 992 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 993 "Global lowest Cx sleep state to use"); 994 995 /* Take over idling from cpu_idle_default(). */ 996 cpu_cx_lowest_lim = 0; 997 for (i = 0; i < cpu_ndevices; i++) { 998 sc = device_get_softc(cpu_devices[i]); 999 enable_idle(sc); 1000 } 1001 cpu_idle_hook = acpi_cpu_idle; 1002 } 1003 1004 static void 1005 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 1006 { 1007 struct sbuf sb; 1008 int i; 1009 1010 /* 1011 * Set up the list of Cx states 1012 */ 1013 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1014 SBUF_FIXEDLEN); 1015 for (i = 0; i < sc->cpu_cx_count; i++) 1016 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1017 sc->cpu_cx_states[i].trans_lat); 1018 sbuf_trim(&sb); 1019 sbuf_finish(&sb); 1020 } 1021 1022 static void 1023 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1024 { 1025 acpi_cpu_cx_list(sc); 1026 1027 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1028 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1029 OID_AUTO, "cx_supported", CTLFLAG_RD, 1030 sc->cpu_cx_supported, 0, 1031 "Cx/microsecond values for supported Cx states"); 1032 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1033 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1034 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 1035 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1036 "lowest Cx sleep state to use"); 1037 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1038 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1039 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 1040 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1041 "percent usage for each Cx state"); 1042 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1043 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1044 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD, 1045 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1046 "Cx sleep state counters"); 1047 #if defined(__i386__) || defined(__amd64__) 1048 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1049 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1050 OID_AUTO, "cx_method", CTLTYPE_STRING | CTLFLAG_RD, 1051 (void *)sc, 0, acpi_cpu_method_sysctl, "A", 1052 "Cx entrance methods"); 1053 #endif 1054 1055 /* Signal platform that we can handle _CST notification. */ 1056 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1057 ACPI_LOCK(acpi); 1058 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1059 ACPI_UNLOCK(acpi); 1060 } 1061 } 1062 1063 /* 1064 * Idle the CPU in the lowest state possible. This function is called with 1065 * interrupts disabled. Note that once it re-enables interrupts, a task 1066 * switch can occur so do not access shared data (i.e. the softc) after 1067 * interrupts are re-enabled. 1068 */ 1069 static void 1070 acpi_cpu_idle(sbintime_t sbt) 1071 { 1072 struct acpi_cpu_softc *sc; 1073 struct acpi_cx *cx_next; 1074 uint64_t cputicks; 1075 uint32_t start_time, end_time; 1076 int bm_active, cx_next_idx, i, us; 1077 1078 /* 1079 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1080 * since there is no ACPI processor object for this CPU. This occurs 1081 * for logical CPUs in the HTT case. 1082 */ 1083 sc = cpu_softc[PCPU_GET(cpuid)]; 1084 if (sc == NULL) { 1085 acpi_cpu_c1(); 1086 return; 1087 } 1088 1089 /* If disabled, take the safe path. */ 1090 if (is_idle_disabled(sc)) { 1091 acpi_cpu_c1(); 1092 return; 1093 } 1094 1095 /* Find the lowest state that has small enough latency. */ 1096 us = sc->cpu_prev_sleep; 1097 if (sbt >= 0 && us > (sbt >> 12)) 1098 us = (sbt >> 12); 1099 cx_next_idx = 0; 1100 if (cpu_disable_c2_sleep) 1101 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1102 else if (cpu_disable_c3_sleep) 1103 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1104 else 1105 i = sc->cpu_cx_lowest; 1106 for (; i >= 0; i--) { 1107 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1108 cx_next_idx = i; 1109 break; 1110 } 1111 } 1112 1113 /* 1114 * Check for bus master activity. If there was activity, clear 1115 * the bit and use the lowest non-C3 state. Note that the USB 1116 * driver polling for new devices keeps this bit set all the 1117 * time if USB is loaded. 1118 */ 1119 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1120 cx_next_idx > sc->cpu_non_c3) { 1121 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1122 if (bm_active != 0) { 1123 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1124 cx_next_idx = sc->cpu_non_c3; 1125 } 1126 } 1127 1128 /* Select the next state and update statistics. */ 1129 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1130 sc->cpu_cx_stats[cx_next_idx]++; 1131 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1132 1133 /* 1134 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1135 * precisely calculate the time spent in C1 since the place we wake up 1136 * is an ISR. Assume we slept no more then half of quantum, unless 1137 * we are called inside critical section, delaying context switch. 1138 */ 1139 if (cx_next->type == ACPI_STATE_C1) { 1140 cputicks = cpu_ticks(); 1141 if (cx_next->p_lvlx != NULL) { 1142 /* C1 I/O then Halt */ 1143 CPU_GET_REG(cx_next->p_lvlx, 1); 1144 } 1145 if (cx_next->do_mwait) 1146 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1147 else 1148 acpi_cpu_c1(); 1149 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1150 if (curthread->td_critnest == 0) 1151 end_time = min(end_time, 500000 / hz); 1152 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1153 return; 1154 } 1155 1156 /* 1157 * For C3, disable bus master arbitration and enable bus master wake 1158 * if BM control is available, otherwise flush the CPU cache. 1159 */ 1160 if (cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) { 1161 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1162 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1163 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1164 } else 1165 ACPI_FLUSH_CPU_CACHE(); 1166 } 1167 1168 /* 1169 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1170 * Use the ACPI timer for measuring sleep time. Since we need to 1171 * get the time very close to the CPU start/stop clock logic, this 1172 * is the only reliable time source. 1173 */ 1174 if (cx_next->type == ACPI_STATE_C3) { 1175 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 1176 cputicks = 0; 1177 } else { 1178 start_time = 0; 1179 cputicks = cpu_ticks(); 1180 } 1181 if (cx_next->do_mwait) 1182 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1183 else 1184 CPU_GET_REG(cx_next->p_lvlx, 1); 1185 1186 /* 1187 * Read the end time twice. Since it may take an arbitrary time 1188 * to enter the idle state, the first read may be executed before 1189 * the processor has stopped. Doing it again provides enough 1190 * margin that we are certain to have a correct value. 1191 */ 1192 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1193 if (cx_next->type == ACPI_STATE_C3) { 1194 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1195 end_time = acpi_TimerDelta(end_time, start_time); 1196 } else 1197 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1198 1199 /* Enable bus master arbitration and disable bus master wakeup. */ 1200 if ((cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) && 1201 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1202 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1203 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1204 } 1205 ACPI_ENABLE_IRQS(); 1206 1207 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1208 } 1209 1210 /* 1211 * Re-evaluate the _CST object when we are notified that it changed. 1212 */ 1213 static void 1214 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1215 { 1216 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1217 1218 if (notify != ACPI_NOTIFY_CX_STATES) 1219 return; 1220 1221 /* 1222 * C-state data for target CPU is going to be in flux while we execute 1223 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1224 * Also, it may happen that multiple ACPI taskqueues may concurrently 1225 * execute notifications for the same CPU. ACPI_SERIAL is used to 1226 * protect against that. 1227 */ 1228 ACPI_SERIAL_BEGIN(cpu); 1229 disable_idle(sc); 1230 1231 /* Update the list of Cx states. */ 1232 acpi_cpu_cx_cst(sc); 1233 acpi_cpu_cx_list(sc); 1234 acpi_cpu_set_cx_lowest(sc); 1235 1236 enable_idle(sc); 1237 ACPI_SERIAL_END(cpu); 1238 1239 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1240 } 1241 1242 static int 1243 acpi_cpu_quirks(void) 1244 { 1245 device_t acpi_dev; 1246 uint32_t val; 1247 1248 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1249 1250 /* 1251 * Bus mastering arbitration control is needed to keep caches coherent 1252 * while sleeping in C3. If it's not present but a working flush cache 1253 * instruction is present, flush the caches before entering C3 instead. 1254 * Otherwise, just disable C3 completely. 1255 */ 1256 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1257 AcpiGbl_FADT.Pm2ControlLength == 0) { 1258 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1259 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1260 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1261 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1262 "acpi_cpu: no BM control, using flush cache method\n")); 1263 } else { 1264 cpu_quirks |= CPU_QUIRK_NO_C3; 1265 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1266 "acpi_cpu: no BM control, C3 not available\n")); 1267 } 1268 } 1269 1270 /* 1271 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1272 * the expensive flush cache instruction. 1273 */ 1274 if (cpu_cx_generic && mp_ncpus > 1) { 1275 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1276 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1277 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1278 } 1279 1280 /* Look for various quirks of the PIIX4 part. */ 1281 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1282 if (acpi_dev != NULL) { 1283 switch (pci_get_revid(acpi_dev)) { 1284 /* 1285 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1286 * do not report the BMIDE status to the BM status register and 1287 * others have a livelock bug if Type-F DMA is enabled. Linux 1288 * works around the BMIDE bug by reading the BM status directly 1289 * but we take the simpler approach of disabling C3 for these 1290 * parts. 1291 * 1292 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1293 * Livelock") from the January 2002 PIIX4 specification update. 1294 * Applies to all PIIX4 models. 1295 * 1296 * Also, make sure that all interrupts cause a "Stop Break" 1297 * event to exit from C2 state. 1298 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1299 * should be set to zero, otherwise it causes C2 to short-sleep. 1300 * PIIX4 doesn't properly support C3 and bus master activity 1301 * need not break out of C2. 1302 */ 1303 case PCI_REVISION_A_STEP: 1304 case PCI_REVISION_B_STEP: 1305 case PCI_REVISION_4E: 1306 case PCI_REVISION_4M: 1307 cpu_quirks |= CPU_QUIRK_NO_C3; 1308 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1309 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1310 1311 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1312 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1313 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1314 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1315 val |= PIIX4_STOP_BREAK_MASK; 1316 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1317 } 1318 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1319 if (val) { 1320 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1321 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1322 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1323 } 1324 break; 1325 default: 1326 break; 1327 } 1328 } 1329 1330 return (0); 1331 } 1332 1333 static int 1334 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1335 { 1336 struct acpi_cpu_softc *sc; 1337 struct sbuf sb; 1338 char buf[128]; 1339 int i; 1340 uintmax_t fract, sum, whole; 1341 1342 sc = (struct acpi_cpu_softc *) arg1; 1343 sum = 0; 1344 for (i = 0; i < sc->cpu_cx_count; i++) 1345 sum += sc->cpu_cx_stats[i]; 1346 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1347 for (i = 0; i < sc->cpu_cx_count; i++) { 1348 if (sum > 0) { 1349 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1350 fract = (whole % sum) * 100; 1351 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1352 (u_int)(fract / sum)); 1353 } else 1354 sbuf_printf(&sb, "0.00%% "); 1355 } 1356 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1357 sbuf_trim(&sb); 1358 sbuf_finish(&sb); 1359 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1360 sbuf_delete(&sb); 1361 1362 return (0); 1363 } 1364 1365 /* 1366 * XXX TODO: actually add support to count each entry/exit 1367 * from the Cx states. 1368 */ 1369 static int 1370 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1371 { 1372 struct acpi_cpu_softc *sc; 1373 struct sbuf sb; 1374 char buf[128]; 1375 int i; 1376 1377 sc = (struct acpi_cpu_softc *) arg1; 1378 1379 /* Print out the raw counters */ 1380 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1381 1382 for (i = 0; i < sc->cpu_cx_count; i++) { 1383 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]); 1384 } 1385 1386 sbuf_trim(&sb); 1387 sbuf_finish(&sb); 1388 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1389 sbuf_delete(&sb); 1390 1391 return (0); 1392 } 1393 1394 #if defined(__i386__) || defined(__amd64__) 1395 static int 1396 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1397 { 1398 struct acpi_cpu_softc *sc; 1399 struct acpi_cx *cx; 1400 struct sbuf sb; 1401 char buf[128]; 1402 int i; 1403 1404 sc = (struct acpi_cpu_softc *)arg1; 1405 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1406 for (i = 0; i < sc->cpu_cx_count; i++) { 1407 cx = &sc->cpu_cx_states[i]; 1408 sbuf_printf(&sb, "C%d/", i + 1); 1409 if (cx->do_mwait) { 1410 sbuf_cat(&sb, "mwait"); 1411 if (cx->mwait_hw_coord) 1412 sbuf_cat(&sb, "/hwc"); 1413 if (cx->mwait_bm_avoidance) 1414 sbuf_cat(&sb, "/bma"); 1415 } else if (cx->type == ACPI_STATE_C1) { 1416 sbuf_cat(&sb, "hlt"); 1417 } else { 1418 sbuf_cat(&sb, "io"); 1419 } 1420 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1421 sbuf_cat(&sb, "/iohlt"); 1422 sbuf_putc(&sb, ' '); 1423 } 1424 sbuf_trim(&sb); 1425 sbuf_finish(&sb); 1426 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1427 sbuf_delete(&sb); 1428 return (0); 1429 } 1430 #endif 1431 1432 static int 1433 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1434 { 1435 int i; 1436 1437 ACPI_SERIAL_ASSERT(cpu); 1438 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1439 1440 /* If not disabling, cache the new lowest non-C3 state. */ 1441 sc->cpu_non_c3 = 0; 1442 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1443 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1444 sc->cpu_non_c3 = i; 1445 break; 1446 } 1447 } 1448 1449 /* Reset the statistics counters. */ 1450 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1451 return (0); 1452 } 1453 1454 static int 1455 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1456 { 1457 struct acpi_cpu_softc *sc; 1458 char state[8]; 1459 int val, error; 1460 1461 sc = (struct acpi_cpu_softc *) arg1; 1462 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1463 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1464 if (error != 0 || req->newptr == NULL) 1465 return (error); 1466 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1467 return (EINVAL); 1468 if (strcasecmp(state, "Cmax") == 0) 1469 val = MAX_CX_STATES; 1470 else { 1471 val = (int) strtol(state + 1, NULL, 10); 1472 if (val < 1 || val > MAX_CX_STATES) 1473 return (EINVAL); 1474 } 1475 1476 ACPI_SERIAL_BEGIN(cpu); 1477 sc->cpu_cx_lowest_lim = val - 1; 1478 acpi_cpu_set_cx_lowest(sc); 1479 ACPI_SERIAL_END(cpu); 1480 1481 return (0); 1482 } 1483 1484 static int 1485 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1486 { 1487 struct acpi_cpu_softc *sc; 1488 char state[8]; 1489 int val, error, i; 1490 1491 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1492 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1493 if (error != 0 || req->newptr == NULL) 1494 return (error); 1495 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1496 return (EINVAL); 1497 if (strcasecmp(state, "Cmax") == 0) 1498 val = MAX_CX_STATES; 1499 else { 1500 val = (int) strtol(state + 1, NULL, 10); 1501 if (val < 1 || val > MAX_CX_STATES) 1502 return (EINVAL); 1503 } 1504 1505 /* Update the new lowest useable Cx state for all CPUs. */ 1506 ACPI_SERIAL_BEGIN(cpu); 1507 cpu_cx_lowest_lim = val - 1; 1508 for (i = 0; i < cpu_ndevices; i++) { 1509 sc = device_get_softc(cpu_devices[i]); 1510 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1511 acpi_cpu_set_cx_lowest(sc); 1512 } 1513 ACPI_SERIAL_END(cpu); 1514 1515 return (0); 1516 } 1517