1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include "opt_acpi.h" 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/cpu.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/pcpu.h> 37 #include <sys/power.h> 38 #include <sys/proc.h> 39 #include <sys/sched.h> 40 #include <sys/sbuf.h> 41 #include <sys/smp.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <machine/atomic.h> 45 #include <machine/bus.h> 46 #if defined(__amd64__) || defined(__i386__) 47 #include <machine/clock.h> 48 #include <machine/specialreg.h> 49 #include <machine/md_var.h> 50 #endif 51 #include <sys/rman.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 58 /* 59 * Support for ACPI Processor devices, including C[1-3] sleep states. 60 */ 61 62 /* Hooks for the ACPI CA debugging infrastructure */ 63 #define _COMPONENT ACPI_PROCESSOR 64 ACPI_MODULE_NAME("PROCESSOR") 65 66 struct acpi_cx { 67 struct resource *p_lvlx; /* Register to read to enter state. */ 68 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 69 uint32_t trans_lat; /* Transition latency (usec). */ 70 uint32_t power; /* Power consumed (mW). */ 71 int res_type; /* Resource type for p_lvlx. */ 72 int res_rid; /* Resource ID for p_lvlx. */ 73 bool do_mwait; 74 uint32_t mwait_hint; 75 bool mwait_hw_coord; 76 bool mwait_bm_avoidance; 77 }; 78 #define MAX_CX_STATES 8 79 80 struct acpi_cpu_softc { 81 device_t cpu_dev; 82 ACPI_HANDLE cpu_handle; 83 struct pcpu *cpu_pcpu; 84 uint32_t cpu_acpi_id; /* ACPI processor id */ 85 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 86 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 87 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 88 int cpu_cx_count; /* Number of valid Cx states. */ 89 int cpu_prev_sleep;/* Last idle sleep duration. */ 90 int cpu_features; /* Child driver supported features. */ 91 /* Runtime state. */ 92 int cpu_non_c2; /* Index of lowest non-C2 state. */ 93 int cpu_non_c3; /* Index of lowest non-C3 state. */ 94 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 95 uint64_t cpu_cx_duration[MAX_CX_STATES];/* Cx cumulative sleep */ 96 /* Values for sysctl. */ 97 struct sysctl_ctx_list cpu_sysctl_ctx; 98 struct sysctl_oid *cpu_sysctl_tree; 99 int cpu_cx_lowest; 100 int cpu_cx_lowest_lim; 101 int cpu_disable_idle; /* Disable entry to idle function */ 102 char cpu_cx_supported[64]; 103 }; 104 105 struct acpi_cpu_device { 106 struct resource_list ad_rl; 107 }; 108 109 #define CPU_GET_REG(reg, width) \ 110 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 111 rman_get_bushandle((reg)), 0)) 112 #define CPU_SET_REG(reg, width, val) \ 113 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 114 rman_get_bushandle((reg)), 0, (val))) 115 116 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 117 118 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 119 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 120 121 #define PCI_VENDOR_INTEL 0x8086 122 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 123 #define PCI_REVISION_A_STEP 0 124 #define PCI_REVISION_B_STEP 1 125 #define PCI_REVISION_4E 2 126 #define PCI_REVISION_4M 3 127 #define PIIX4_DEVACTB_REG 0x58 128 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 129 #define PIIX4_BRLD_EN_IRQ (1<<1) 130 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 131 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 132 #define PIIX4_PCNTRL_BST_EN (1<<10) 133 134 #define CST_FFH_VENDOR_INTEL 1 135 #define CST_FFH_VENDOR_AMD 2 136 #define CST_FFH_INTEL_CL_C1IO 1 137 #define CST_FFH_INTEL_CL_MWAIT 2 138 #define CST_FFH_MWAIT_HW_COORD 0x0001 139 #define CST_FFH_MWAIT_BM_AVOID 0x0002 140 141 #define CPUDEV_DEVICE_ID "ACPI0007" 142 143 /* Knob to disable acpi_cpu devices */ 144 bool acpi_cpu_disabled = false; 145 146 /* Platform hardware resource information. */ 147 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 148 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 149 static int cpu_quirks; /* Indicate any hardware bugs. */ 150 151 /* Values for sysctl. */ 152 static struct sysctl_ctx_list cpu_sysctl_ctx; 153 static struct sysctl_oid *cpu_sysctl_tree; 154 static int cpu_cx_generic; 155 static int cpu_cx_lowest_lim; 156 #if defined(__i386__) || defined(__amd64__) 157 static bool cppc_notify; 158 #endif 159 160 static struct acpi_cpu_softc **cpu_softc; 161 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 162 163 static int acpi_cpu_probe(device_t dev); 164 static int acpi_cpu_attach(device_t dev); 165 static int acpi_cpu_suspend(device_t dev); 166 static int acpi_cpu_resume(device_t dev); 167 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, 168 u_int *cpu_id); 169 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 170 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 171 int unit); 172 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 173 uintptr_t *result); 174 static int acpi_cpu_shutdown(device_t dev); 175 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 176 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 177 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 178 static void acpi_cpu_startup(void *arg); 179 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 180 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 181 #if defined(__i386__) || defined(__amd64__) 182 static void acpi_cpu_idle(sbintime_t sbt); 183 #endif 184 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 185 static void acpi_cpu_quirks(void); 186 static void acpi_cpu_quirks_piix4(void); 187 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 188 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 189 static int acpi_cpu_duration_counters_sysctl(SYSCTL_HANDLER_ARGS); 190 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 191 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 192 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 193 #if defined(__i386__) || defined(__amd64__) 194 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 195 #endif 196 197 static device_method_t acpi_cpu_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, acpi_cpu_probe), 200 DEVMETHOD(device_attach, acpi_cpu_attach), 201 DEVMETHOD(device_detach, bus_generic_detach), 202 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 203 DEVMETHOD(device_suspend, acpi_cpu_suspend), 204 DEVMETHOD(device_resume, acpi_cpu_resume), 205 206 /* Bus interface */ 207 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 208 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 209 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 210 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 211 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 212 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 213 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 214 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 215 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 216 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 217 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 218 219 DEVMETHOD_END 220 }; 221 222 static driver_t acpi_cpu_driver = { 223 "cpu", 224 acpi_cpu_methods, 225 sizeof(struct acpi_cpu_softc), 226 }; 227 228 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, 0, 0); 229 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 230 231 static int 232 acpi_cpu_probe(device_t dev) 233 { 234 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL }; 235 int acpi_id, cpu_id; 236 ACPI_BUFFER buf; 237 ACPI_HANDLE handle; 238 ACPI_OBJECT *obj; 239 ACPI_STATUS status; 240 ACPI_OBJECT_TYPE type; 241 242 if (acpi_disabled("cpu") || acpi_cpu_disabled) 243 return (ENXIO); 244 type = acpi_get_type(dev); 245 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE) 246 return (ENXIO); 247 if (type == ACPI_TYPE_DEVICE && 248 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0) 249 return (ENXIO); 250 251 handle = acpi_get_handle(dev); 252 if (cpu_softc == NULL) 253 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 254 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 255 256 if (type == ACPI_TYPE_PROCESSOR) { 257 /* Get our Processor object. */ 258 buf.Pointer = NULL; 259 buf.Length = ACPI_ALLOCATE_BUFFER; 260 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 261 if (ACPI_FAILURE(status)) { 262 device_printf(dev, "probe failed to get Processor obj - %s\n", 263 AcpiFormatException(status)); 264 return (ENXIO); 265 } 266 obj = (ACPI_OBJECT *)buf.Pointer; 267 if (obj->Type != ACPI_TYPE_PROCESSOR) { 268 device_printf(dev, "Processor object has bad type %d\n", 269 obj->Type); 270 AcpiOsFree(obj); 271 return (ENXIO); 272 } 273 274 /* 275 * Find the processor associated with our unit. We could use the 276 * ProcId as a key, however, some boxes do not have the same values 277 * in their Processor object as the ProcId values in the MADT. 278 */ 279 acpi_id = obj->Processor.ProcId; 280 AcpiOsFree(obj); 281 } else { 282 status = acpi_GetInteger(handle, "_UID", &acpi_id); 283 if (ACPI_FAILURE(status)) { 284 device_printf(dev, "Device object has bad value - %s\n", 285 AcpiFormatException(status)); 286 return (ENXIO); 287 } 288 } 289 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) { 290 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255)) 291 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 292 acpi_name(acpi_get_handle(dev)), acpi_id); 293 return (ENXIO); 294 } 295 296 if (device_set_unit(dev, cpu_id) != 0) 297 return (ENXIO); 298 299 device_set_desc(dev, "ACPI CPU"); 300 301 if (!bootverbose && device_get_unit(dev) != 0) { 302 device_quiet(dev); 303 device_quiet_children(dev); 304 } 305 306 return (BUS_PROBE_DEFAULT); 307 } 308 309 static int 310 acpi_cpu_attach(device_t dev) 311 { 312 ACPI_BUFFER buf; 313 ACPI_OBJECT arg, *obj; 314 ACPI_OBJECT_LIST arglist; 315 struct pcpu *pcpu_data; 316 struct acpi_cpu_softc *sc; 317 struct acpi_softc *acpi_sc; 318 ACPI_STATUS status; 319 u_int features; 320 int cpu_id, drv_count, i; 321 driver_t **drivers; 322 uint32_t cap_set[3]; 323 324 /* UUID needed by _OSC evaluation */ 325 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 326 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 327 0x58, 0x71, 0x39, 0x53 }; 328 329 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 330 331 sc = device_get_softc(dev); 332 sc->cpu_dev = dev; 333 sc->cpu_handle = acpi_get_handle(dev); 334 cpu_id = device_get_unit(dev); 335 cpu_softc[cpu_id] = sc; 336 pcpu_data = pcpu_find(cpu_id); 337 pcpu_data->pc_device = dev; 338 sc->cpu_pcpu = pcpu_data; 339 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 340 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 341 342 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) { 343 buf.Pointer = NULL; 344 buf.Length = ACPI_ALLOCATE_BUFFER; 345 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 346 if (ACPI_FAILURE(status)) { 347 device_printf(dev, "attach failed to get Processor obj - %s\n", 348 AcpiFormatException(status)); 349 return (ENXIO); 350 } 351 obj = (ACPI_OBJECT *)buf.Pointer; 352 sc->cpu_p_blk = obj->Processor.PblkAddress; 353 sc->cpu_p_blk_len = obj->Processor.PblkLength; 354 sc->cpu_acpi_id = obj->Processor.ProcId; 355 AcpiOsFree(obj); 356 } else { 357 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE, 358 ("Unexpected ACPI object")); 359 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id); 360 if (ACPI_FAILURE(status)) { 361 device_printf(dev, "Device object has bad value - %s\n", 362 AcpiFormatException(status)); 363 return (ENXIO); 364 } 365 sc->cpu_p_blk = 0; 366 sc->cpu_p_blk_len = 0; 367 } 368 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 369 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 370 371 /* 372 * If this is the first cpu we attach, create and initialize the generic 373 * resources that will be used by all acpi cpu devices. 374 */ 375 if (device_get_unit(dev) == 0) { 376 /* Assume we won't be using generic Cx mode by default */ 377 cpu_cx_generic = FALSE; 378 379 /* Install hw.acpi.cpu sysctl tree */ 380 acpi_sc = acpi_device_get_parent_softc(dev); 381 sysctl_ctx_init(&cpu_sysctl_ctx); 382 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 383 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 384 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children"); 385 386 #if defined(__i386__) || defined(__amd64__) 387 /* Add sysctl handler to control registering for CPPC notifications */ 388 cppc_notify = 1; 389 SYSCTL_ADD_BOOL(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 390 OID_AUTO, "cppc_notify", CTLFLAG_RDTUN | CTLFLAG_MPSAFE, 391 &cppc_notify, 0, "Register for CPPC Notifications"); 392 #endif 393 } 394 395 /* 396 * Before calling any CPU methods, collect child driver feature hints 397 * and notify ACPI of them. We support unified SMP power control 398 * so advertise this ourselves. Note this is not the same as independent 399 * SMP control where each CPU can have different settings. 400 */ 401 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 402 ACPI_CAP_C1_IO_HALT; 403 404 #if defined(__i386__) || defined(__amd64__) 405 /* 406 * Ask for MWAIT modes if not disabled and interrupts work 407 * reasonable with MWAIT. 408 */ 409 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 410 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 411 412 /* 413 * Work around a lingering SMM bug which leads to freezes when handling 414 * CPPC notifications. Tell the SMM we will handle any CPPC notifications. 415 */ 416 if ((cpu_power_eax & CPUTPM1_HWP_NOTIFICATION) && cppc_notify) 417 sc->cpu_features |= ACPI_CAP_INTR_CPPC; 418 #endif 419 420 if (devclass_get_drivers(device_get_devclass(dev), &drivers, 421 &drv_count) == 0) { 422 for (i = 0; i < drv_count; i++) { 423 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 424 sc->cpu_features |= features; 425 } 426 free(drivers, M_TEMP); 427 } 428 429 /* 430 * CPU capabilities are specified in 431 * Intel Processor Vendor-Specific ACPI Interface Specification. 432 */ 433 if (sc->cpu_features) { 434 cap_set[1] = sc->cpu_features; 435 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 436 cap_set, false); 437 if (ACPI_SUCCESS(status)) { 438 if (cap_set[0] != 0) 439 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 440 } 441 else { 442 arglist.Pointer = &arg; 443 arglist.Count = 1; 444 arg.Type = ACPI_TYPE_BUFFER; 445 arg.Buffer.Length = sizeof(cap_set); 446 arg.Buffer.Pointer = (uint8_t *)cap_set; 447 cap_set[0] = 1; /* revision */ 448 cap_set[1] = 1; /* number of capabilities integers */ 449 cap_set[2] = sc->cpu_features; 450 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 451 } 452 } 453 454 /* Probe for Cx state support. */ 455 acpi_cpu_cx_probe(sc); 456 457 return (0); 458 } 459 460 static void 461 acpi_cpu_postattach(void *unused __unused) 462 { 463 struct acpi_cpu_softc *sc; 464 int attached = 0, i; 465 466 if (cpu_softc == NULL) 467 return; 468 469 bus_topo_lock(); 470 CPU_FOREACH(i) { 471 if ((sc = cpu_softc[i]) != NULL) 472 bus_identify_children(sc->cpu_dev); 473 } 474 CPU_FOREACH(i) { 475 if ((sc = cpu_softc[i]) != NULL) { 476 bus_attach_children(sc->cpu_dev); 477 attached = 1; 478 } 479 } 480 bus_topo_unlock(); 481 482 if (attached) { 483 #ifdef EARLY_AP_STARTUP 484 acpi_cpu_startup(NULL); 485 #else 486 /* Queue post cpu-probing task handler */ 487 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 488 #endif 489 } 490 } 491 492 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 493 acpi_cpu_postattach, NULL); 494 495 static void 496 disable_idle(struct acpi_cpu_softc *sc) 497 { 498 cpuset_t cpuset; 499 500 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 501 sc->cpu_disable_idle = TRUE; 502 503 /* 504 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 505 * Note that this code depends on the fact that the rendezvous IPI 506 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 507 * is called and executed in such a context with interrupts being re-enabled 508 * right before return. 509 */ 510 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 511 smp_no_rendezvous_barrier, NULL); 512 } 513 514 static void 515 enable_idle(struct acpi_cpu_softc *sc) 516 { 517 518 if (sc->cpu_cx_count > sc->cpu_non_c3 + 1 && 519 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 520 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 521 sc->cpu_disable_idle = FALSE; 522 } 523 524 #if defined(__i386__) || defined(__amd64__) 525 static int 526 is_idle_disabled(struct acpi_cpu_softc *sc) 527 { 528 529 return (sc->cpu_disable_idle); 530 } 531 #endif 532 533 /* 534 * Disable any entry to the idle function during suspend and re-enable it 535 * during resume. 536 */ 537 static int 538 acpi_cpu_suspend(device_t dev) 539 { 540 int error; 541 542 error = bus_generic_suspend(dev); 543 if (error) 544 return (error); 545 disable_idle(device_get_softc(dev)); 546 return (0); 547 } 548 549 static int 550 acpi_cpu_resume(device_t dev) 551 { 552 553 enable_idle(device_get_softc(dev)); 554 return (bus_generic_resume(dev)); 555 } 556 557 /* 558 * Find the processor associated with a given ACPI ID. 559 */ 560 static int 561 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id) 562 { 563 struct pcpu *pc; 564 u_int i; 565 566 CPU_FOREACH(i) { 567 pc = pcpu_find(i); 568 if (pc->pc_acpi_id == acpi_id) { 569 *cpu_id = pc->pc_cpuid; 570 return (0); 571 } 572 } 573 574 /* 575 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 576 * UP box) use the ACPI ID from the first processor we find. 577 */ 578 if (mp_ncpus == 1) { 579 pc = pcpu_find(0); 580 if (pc->pc_acpi_id == 0xffffffff) 581 pc->pc_acpi_id = acpi_id; 582 *cpu_id = 0; 583 return (0); 584 } 585 586 return (ESRCH); 587 } 588 589 static struct resource_list * 590 acpi_cpu_get_rlist(device_t dev, device_t child) 591 { 592 struct acpi_cpu_device *ad; 593 594 ad = device_get_ivars(child); 595 if (ad == NULL) 596 return (NULL); 597 return (&ad->ad_rl); 598 } 599 600 static device_t 601 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 602 { 603 struct acpi_cpu_device *ad; 604 device_t child; 605 606 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 607 return (NULL); 608 609 resource_list_init(&ad->ad_rl); 610 611 child = device_add_child_ordered(dev, order, name, unit); 612 if (child != NULL) 613 device_set_ivars(child, ad); 614 else 615 free(ad, M_TEMP); 616 return (child); 617 } 618 619 static int 620 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 621 { 622 struct acpi_cpu_softc *sc; 623 624 sc = device_get_softc(dev); 625 switch (index) { 626 case ACPI_IVAR_HANDLE: 627 *result = (uintptr_t)sc->cpu_handle; 628 break; 629 case CPU_IVAR_PCPU: 630 *result = (uintptr_t)sc->cpu_pcpu; 631 break; 632 #if defined(__amd64__) || defined(__i386__) 633 case CPU_IVAR_NOMINAL_MHZ: 634 if (tsc_is_invariant) { 635 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 636 break; 637 } 638 /* FALLTHROUGH */ 639 #endif 640 default: 641 return (ENOENT); 642 } 643 return (0); 644 } 645 646 static int 647 acpi_cpu_shutdown(device_t dev) 648 { 649 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 650 651 /* Allow children to shutdown first. */ 652 bus_generic_shutdown(dev); 653 654 /* 655 * Disable any entry to the idle function. 656 */ 657 disable_idle(device_get_softc(dev)); 658 659 /* 660 * CPU devices are not truly detached and remain referenced, 661 * so their resources are not freed. 662 */ 663 664 return_VALUE (0); 665 } 666 667 static void 668 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 669 { 670 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 671 672 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 673 sc->cpu_prev_sleep = 1000000; 674 sc->cpu_cx_lowest = 0; 675 sc->cpu_cx_lowest_lim = 0; 676 677 /* 678 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 679 * any, we'll revert to generic FADT/P_BLK Cx control method which will 680 * be handled by acpi_cpu_startup. We need to defer to after having 681 * probed all the cpus in the system before probing for generic Cx 682 * states as we may already have found cpus with valid _CST packages 683 */ 684 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 685 /* 686 * We were unable to find a _CST package for this cpu or there 687 * was an error parsing it. Switch back to generic mode. 688 */ 689 cpu_cx_generic = TRUE; 690 if (bootverbose) 691 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 692 } 693 694 /* 695 * TODO: _CSD Package should be checked here. 696 */ 697 } 698 699 static void 700 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 701 { 702 ACPI_GENERIC_ADDRESS gas; 703 struct acpi_cx *cx_ptr; 704 705 sc->cpu_cx_count = 0; 706 cx_ptr = sc->cpu_cx_states; 707 708 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 709 sc->cpu_prev_sleep = 1000000; 710 711 /* C1 has been required since just after ACPI 1.0 */ 712 cx_ptr->type = ACPI_STATE_C1; 713 cx_ptr->trans_lat = 0; 714 cx_ptr++; 715 sc->cpu_non_c2 = sc->cpu_cx_count; 716 sc->cpu_non_c3 = sc->cpu_cx_count; 717 sc->cpu_cx_count++; 718 719 /* 720 * The spec says P_BLK must be 6 bytes long. However, some systems 721 * use it to indicate a fractional set of features present so we 722 * take 5 as C2. Some may also have a value of 7 to indicate 723 * another C3 but most use _CST for this (as required) and having 724 * "only" C1-C3 is not a hardship. 725 */ 726 if (sc->cpu_p_blk_len < 5) 727 return; 728 729 /* Validate and allocate resources for C2 (P_LVL2). */ 730 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 731 gas.BitWidth = 8; 732 if (AcpiGbl_FADT.C2Latency <= 100) { 733 gas.Address = sc->cpu_p_blk + 4; 734 cx_ptr->res_rid = 0; 735 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 736 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 737 if (cx_ptr->p_lvlx != NULL) { 738 cx_ptr->type = ACPI_STATE_C2; 739 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 740 cx_ptr++; 741 sc->cpu_non_c3 = sc->cpu_cx_count; 742 sc->cpu_cx_count++; 743 } 744 } 745 if (sc->cpu_p_blk_len < 6) 746 return; 747 748 /* Validate and allocate resources for C3 (P_LVL3). */ 749 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 750 gas.Address = sc->cpu_p_blk + 5; 751 cx_ptr->res_rid = 1; 752 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 753 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 754 if (cx_ptr->p_lvlx != NULL) { 755 cx_ptr->type = ACPI_STATE_C3; 756 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 757 cx_ptr++; 758 sc->cpu_cx_count++; 759 } 760 } 761 } 762 763 #if defined(__i386__) || defined(__amd64__) 764 static void 765 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 766 { 767 768 cx_ptr->do_mwait = true; 769 cx_ptr->mwait_hint = address & 0xffffffff; 770 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 771 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 772 } 773 #endif 774 775 static void 776 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 777 { 778 779 if (cx_ptr->p_lvlx == NULL) 780 return; 781 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 782 cx_ptr->p_lvlx); 783 cx_ptr->p_lvlx = NULL; 784 } 785 786 /* 787 * Parse a _CST package and set up its Cx states. Since the _CST object 788 * can change dynamically, our notify handler may call this function 789 * to clean up and probe the new _CST package. 790 */ 791 static int 792 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 793 { 794 struct acpi_cx *cx_ptr; 795 ACPI_STATUS status; 796 ACPI_BUFFER buf; 797 ACPI_OBJECT *top; 798 ACPI_OBJECT *pkg; 799 uint32_t count; 800 int i; 801 #if defined(__i386__) || defined(__amd64__) 802 uint64_t address; 803 int vendor, class, accsize; 804 #endif 805 806 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 807 808 buf.Pointer = NULL; 809 buf.Length = ACPI_ALLOCATE_BUFFER; 810 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 811 if (ACPI_FAILURE(status)) 812 return (ENXIO); 813 814 /* _CST is a package with a count and at least one Cx package. */ 815 top = (ACPI_OBJECT *)buf.Pointer; 816 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 817 device_printf(sc->cpu_dev, "invalid _CST package\n"); 818 AcpiOsFree(buf.Pointer); 819 return (ENXIO); 820 } 821 if (count != top->Package.Count - 1) { 822 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 823 count, top->Package.Count - 1); 824 count = top->Package.Count - 1; 825 } 826 if (count > MAX_CX_STATES) { 827 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 828 count = MAX_CX_STATES; 829 } 830 831 sc->cpu_non_c2 = 0; 832 sc->cpu_non_c3 = 0; 833 sc->cpu_cx_count = 0; 834 cx_ptr = sc->cpu_cx_states; 835 836 /* 837 * C1 has been required since just after ACPI 1.0. 838 * Reserve the first slot for it. 839 */ 840 cx_ptr->type = ACPI_STATE_C0; 841 cx_ptr++; 842 sc->cpu_cx_count++; 843 844 /* Set up all valid states. */ 845 for (i = 0; i < count; i++) { 846 pkg = &top->Package.Elements[i + 1]; 847 if (!ACPI_PKG_VALID(pkg, 4) || 848 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 849 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 850 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 851 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 852 continue; 853 } 854 855 /* Validate the state to see if we should use it. */ 856 switch (cx_ptr->type) { 857 case ACPI_STATE_C1: 858 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 859 #if defined(__i386__) || defined(__amd64__) 860 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 861 &accsize) == 0 && 862 (vendor == CST_FFH_VENDOR_INTEL || vendor == CST_FFH_VENDOR_AMD)) { 863 if (class == CST_FFH_INTEL_CL_C1IO) { 864 /* C1 I/O then Halt */ 865 cx_ptr->res_rid = sc->cpu_cx_count; 866 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 867 cx_ptr->res_rid, address, 1); 868 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 869 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 870 RF_SHAREABLE); 871 if (cx_ptr->p_lvlx == NULL) { 872 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 873 cx_ptr->res_rid); 874 device_printf(sc->cpu_dev, 875 "C1 I/O failed to allocate port %d, " 876 "degrading to C1 Halt", (int)address); 877 } 878 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 879 if (vendor == CST_FFH_VENDOR_INTEL || 880 (vendor == CST_FFH_VENDOR_AMD && cpu_mon_mwait_edx != 0)) 881 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 882 } 883 } 884 #endif 885 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 886 /* This is the first C1 state. Use the reserved slot. */ 887 sc->cpu_cx_states[0] = *cx_ptr; 888 } else { 889 sc->cpu_non_c2 = sc->cpu_cx_count; 890 sc->cpu_non_c3 = sc->cpu_cx_count; 891 cx_ptr++; 892 sc->cpu_cx_count++; 893 } 894 continue; 895 case ACPI_STATE_C2: 896 sc->cpu_non_c3 = sc->cpu_cx_count; 897 break; 898 case ACPI_STATE_C3: 899 default: 900 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 901 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 902 "acpi_cpu%d: C3[%d] not available.\n", 903 device_get_unit(sc->cpu_dev), i)); 904 continue; 905 } 906 break; 907 } 908 909 /* Free up any previous register. */ 910 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 911 912 /* Allocate the control register for C2 or C3. */ 913 #if defined(__i386__) || defined(__amd64__) 914 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 915 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 916 class == CST_FFH_INTEL_CL_MWAIT) { 917 /* Native C State Instruction use (mwait) */ 918 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 919 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 920 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 921 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 922 cx_ptr++; 923 sc->cpu_cx_count++; 924 } else 925 #endif 926 { 927 cx_ptr->res_rid = sc->cpu_cx_count; 928 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 929 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 930 if (cx_ptr->p_lvlx) { 931 cx_ptr->do_mwait = false; 932 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 933 "acpi_cpu%d: Got C%d - %d latency\n", 934 device_get_unit(sc->cpu_dev), cx_ptr->type, 935 cx_ptr->trans_lat)); 936 cx_ptr++; 937 sc->cpu_cx_count++; 938 } 939 } 940 } 941 AcpiOsFree(buf.Pointer); 942 943 /* If C1 state was not found, we need one now. */ 944 cx_ptr = sc->cpu_cx_states; 945 if (cx_ptr->type == ACPI_STATE_C0) { 946 cx_ptr->type = ACPI_STATE_C1; 947 cx_ptr->trans_lat = 0; 948 } 949 950 return (0); 951 } 952 953 /* 954 * Call this *after* all CPUs have been attached. 955 */ 956 static void 957 acpi_cpu_startup(void *arg) 958 { 959 struct acpi_cpu_softc *sc; 960 int i; 961 962 /* 963 * Setup any quirks that might necessary now that we have probed 964 * all the CPUs 965 */ 966 acpi_cpu_quirks(); 967 968 if (cpu_cx_generic) { 969 /* 970 * We are using generic Cx mode, probe for available Cx states 971 * for all processors. 972 */ 973 CPU_FOREACH(i) { 974 if ((sc = cpu_softc[i]) != NULL) 975 acpi_cpu_generic_cx_probe(sc); 976 } 977 } else { 978 /* 979 * We are using _CST mode, remove C3 state if necessary. 980 * As we now know for sure that we will be using _CST mode 981 * install our notify handler. 982 */ 983 CPU_FOREACH(i) { 984 if ((sc = cpu_softc[i]) == NULL) 985 continue; 986 if (cpu_quirks & CPU_QUIRK_NO_C3) { 987 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 988 } 989 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 990 acpi_cpu_notify, sc); 991 } 992 } 993 994 /* Perform Cx final initialization. */ 995 CPU_FOREACH(i) { 996 if ((sc = cpu_softc[i]) != NULL) 997 acpi_cpu_startup_cx(sc); 998 } 999 1000 /* Add a sysctl handler to handle global Cx lowest setting */ 1001 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 1002 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1003 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 1004 "Global lowest Cx sleep state to use"); 1005 1006 /* Take over idling from cpu_idle_default(). */ 1007 cpu_cx_lowest_lim = 0; 1008 CPU_FOREACH(i) { 1009 if ((sc = cpu_softc[i]) != NULL) 1010 enable_idle(sc); 1011 } 1012 #if defined(__i386__) || defined(__amd64__) 1013 cpu_idle_hook = acpi_cpu_idle; 1014 #endif 1015 } 1016 1017 static void 1018 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 1019 { 1020 struct sbuf sb; 1021 int i; 1022 1023 /* 1024 * Set up the list of Cx states 1025 */ 1026 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1027 SBUF_FIXEDLEN); 1028 for (i = 0; i < sc->cpu_cx_count; i++) 1029 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1030 sc->cpu_cx_states[i].trans_lat); 1031 sbuf_trim(&sb); 1032 sbuf_finish(&sb); 1033 } 1034 1035 static void 1036 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1037 { 1038 acpi_cpu_cx_list(sc); 1039 1040 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1041 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1042 OID_AUTO, "cx_supported", CTLFLAG_RD, 1043 sc->cpu_cx_supported, 0, 1044 "Cx/microsecond values for supported Cx states"); 1045 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1046 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1047 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1048 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1049 "lowest Cx sleep state to use"); 1050 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1051 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1052 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1053 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1054 "percent usage for each Cx state"); 1055 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1056 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1057 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1058 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1059 "Cx sleep state counters"); 1060 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1061 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1062 "cx_duration_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1063 (void *)sc, 0, acpi_cpu_duration_counters_sysctl, "A", 1064 "Cx sleep duration cumulative time"); 1065 1066 #if defined(__i386__) || defined(__amd64__) 1067 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1068 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1069 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1070 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods"); 1071 #endif 1072 1073 /* Signal platform that we can handle _CST notification. */ 1074 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1075 ACPI_LOCK(acpi); 1076 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1077 ACPI_UNLOCK(acpi); 1078 } 1079 } 1080 1081 #if defined(__i386__) || defined(__amd64__) 1082 /* 1083 * Idle the CPU in the lowest state possible. This function is called with 1084 * interrupts disabled. Note that once it re-enables interrupts, a task 1085 * switch can occur so do not access shared data (i.e. the softc) after 1086 * interrupts are re-enabled. 1087 */ 1088 static void 1089 acpi_cpu_idle(sbintime_t sbt) 1090 { 1091 struct acpi_cpu_softc *sc; 1092 struct acpi_cx *cx_next; 1093 uint64_t start_ticks, end_ticks; 1094 uint32_t start_time, end_time; 1095 ACPI_STATUS status; 1096 int bm_active, cx_next_idx, i, us; 1097 1098 /* 1099 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1100 * since there is no ACPI processor object for this CPU. This occurs 1101 * for logical CPUs in the HTT case. 1102 */ 1103 sc = cpu_softc[PCPU_GET(cpuid)]; 1104 if (sc == NULL) { 1105 acpi_cpu_c1(); 1106 return; 1107 } 1108 1109 /* If disabled, take the safe path. */ 1110 if (is_idle_disabled(sc)) { 1111 acpi_cpu_c1(); 1112 return; 1113 } 1114 1115 /* Find the lowest state that has small enough latency. */ 1116 us = sc->cpu_prev_sleep; 1117 if (sbt >= 0 && us > (sbt >> 12)) 1118 us = (sbt >> 12); 1119 cx_next_idx = 0; 1120 if (cpu_disable_c2_sleep) 1121 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1122 else if (cpu_disable_c3_sleep) 1123 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1124 else 1125 i = sc->cpu_cx_lowest; 1126 for (; i >= 0; i--) { 1127 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1128 cx_next_idx = i; 1129 break; 1130 } 1131 } 1132 1133 /* 1134 * Check for bus master activity. If there was activity, clear 1135 * the bit and use the lowest non-C3 state. Note that the USB 1136 * driver polling for new devices keeps this bit set all the 1137 * time if USB is loaded. 1138 */ 1139 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1140 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1141 cx_next_idx > sc->cpu_non_c3 && 1142 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) { 1143 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1144 if (ACPI_SUCCESS(status) && bm_active != 0) { 1145 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1146 cx_next_idx = sc->cpu_non_c3; 1147 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1148 } 1149 } 1150 1151 /* Select the next state and update statistics. */ 1152 sc->cpu_cx_stats[cx_next_idx]++; 1153 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1154 1155 /* 1156 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1157 * precisely calculate the time spent in C1 since the place we wake up 1158 * is an ISR. Assume we slept no more then half of quantum, unless 1159 * we are called inside critical section, delaying context switch. 1160 */ 1161 if (cx_next->type == ACPI_STATE_C1) { 1162 start_ticks = cpu_ticks(); 1163 if (cx_next->p_lvlx != NULL) { 1164 /* C1 I/O then Halt */ 1165 CPU_GET_REG(cx_next->p_lvlx, 1); 1166 } 1167 if (cx_next->do_mwait) 1168 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1169 else 1170 acpi_cpu_c1(); 1171 end_ticks = cpu_ticks(); 1172 /* acpi_cpu_c1() returns with interrupts enabled. */ 1173 if (cx_next->do_mwait) 1174 ACPI_ENABLE_IRQS(); 1175 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1176 if (!cx_next->do_mwait && curthread->td_critnest == 0) 1177 end_time = min(end_time, 500000 / hz); 1178 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1179 sc->cpu_cx_duration[cx_next_idx] += end_time; 1180 return; 1181 } 1182 1183 /* 1184 * For C3, disable bus master arbitration if BM control is available. 1185 * CPU may have to wake up to handle it. Otherwise flush the CPU cache. 1186 */ 1187 if (cx_next->type == ACPI_STATE_C3) { 1188 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 1189 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1190 else 1191 ACPI_FLUSH_CPU_CACHE(); 1192 } 1193 1194 /* 1195 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1196 * Use the ACPI timer for measuring sleep time. Since we need to 1197 * get the time very close to the CPU start/stop clock logic, this 1198 * is the only reliable time source. 1199 */ 1200 if (cx_next->type == ACPI_STATE_C3) { 1201 AcpiGetTimer(&start_time); 1202 start_ticks = 0; 1203 } else { 1204 start_time = 0; 1205 start_ticks = cpu_ticks(); 1206 } 1207 if (cx_next->do_mwait) { 1208 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1209 } else { 1210 CPU_GET_REG(cx_next->p_lvlx, 1); 1211 /* 1212 * Read the end time twice. Since it may take an arbitrary time 1213 * to enter the idle state, the first read may be executed before 1214 * the processor has stopped. Doing it again provides enough 1215 * margin that we are certain to have a correct value. 1216 */ 1217 AcpiGetTimer(&end_time); 1218 } 1219 1220 if (cx_next->type == ACPI_STATE_C3) 1221 AcpiGetTimer(&end_time); 1222 else 1223 end_ticks = cpu_ticks(); 1224 1225 /* Enable bus master arbitration. */ 1226 if (cx_next->type == ACPI_STATE_C3 && 1227 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) 1228 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1229 ACPI_ENABLE_IRQS(); 1230 1231 if (cx_next->type == ACPI_STATE_C3) 1232 AcpiGetTimerDuration(start_time, end_time, &end_time); 1233 else 1234 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1235 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1236 sc->cpu_cx_duration[cx_next_idx] += end_time; 1237 } 1238 #endif 1239 1240 /* 1241 * Re-evaluate the _CST object when we are notified that it changed. 1242 */ 1243 static void 1244 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1245 { 1246 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1247 1248 if (notify != ACPI_NOTIFY_CX_STATES) 1249 return; 1250 1251 /* 1252 * C-state data for target CPU is going to be in flux while we execute 1253 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1254 * Also, it may happen that multiple ACPI taskqueues may concurrently 1255 * execute notifications for the same CPU. ACPI_SERIAL is used to 1256 * protect against that. 1257 */ 1258 ACPI_SERIAL_BEGIN(cpu); 1259 disable_idle(sc); 1260 1261 /* Update the list of Cx states. */ 1262 acpi_cpu_cx_cst(sc); 1263 acpi_cpu_cx_list(sc); 1264 acpi_cpu_set_cx_lowest(sc); 1265 1266 enable_idle(sc); 1267 ACPI_SERIAL_END(cpu); 1268 1269 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1270 } 1271 1272 static void 1273 acpi_cpu_quirks(void) 1274 { 1275 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1276 1277 /* 1278 * Bus mastering arbitration control is needed to keep caches coherent 1279 * while sleeping in C3. If it's not present but a working flush cache 1280 * instruction is present, flush the caches before entering C3 instead. 1281 * Otherwise, just disable C3 completely. 1282 */ 1283 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1284 AcpiGbl_FADT.Pm2ControlLength == 0) { 1285 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1286 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1287 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1288 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1289 "acpi_cpu: no BM control, using flush cache method\n")); 1290 } else { 1291 cpu_quirks |= CPU_QUIRK_NO_C3; 1292 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1293 "acpi_cpu: no BM control, C3 not available\n")); 1294 } 1295 } 1296 1297 /* 1298 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1299 * the expensive flush cache instruction. 1300 */ 1301 if (cpu_cx_generic && mp_ncpus > 1) { 1302 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1303 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1304 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1305 } 1306 1307 /* Look for various quirks of the PIIX4 part. */ 1308 acpi_cpu_quirks_piix4(); 1309 } 1310 1311 static void 1312 acpi_cpu_quirks_piix4(void) 1313 { 1314 #ifdef __i386__ 1315 device_t acpi_dev; 1316 uint32_t val; 1317 ACPI_STATUS status; 1318 1319 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1320 if (acpi_dev != NULL) { 1321 switch (pci_get_revid(acpi_dev)) { 1322 /* 1323 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1324 * do not report the BMIDE status to the BM status register and 1325 * others have a livelock bug if Type-F DMA is enabled. Linux 1326 * works around the BMIDE bug by reading the BM status directly 1327 * but we take the simpler approach of disabling C3 for these 1328 * parts. 1329 * 1330 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1331 * Livelock") from the January 2002 PIIX4 specification update. 1332 * Applies to all PIIX4 models. 1333 * 1334 * Also, make sure that all interrupts cause a "Stop Break" 1335 * event to exit from C2 state. 1336 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1337 * should be set to zero, otherwise it causes C2 to short-sleep. 1338 * PIIX4 doesn't properly support C3 and bus master activity 1339 * need not break out of C2. 1340 */ 1341 case PCI_REVISION_A_STEP: 1342 case PCI_REVISION_B_STEP: 1343 case PCI_REVISION_4E: 1344 case PCI_REVISION_4M: 1345 cpu_quirks |= CPU_QUIRK_NO_C3; 1346 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1347 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1348 1349 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1350 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1351 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1352 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1353 val |= PIIX4_STOP_BREAK_MASK; 1354 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1355 } 1356 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1357 if (ACPI_SUCCESS(status) && val != 0) { 1358 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1359 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1360 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1361 } 1362 break; 1363 default: 1364 break; 1365 } 1366 } 1367 #endif 1368 } 1369 1370 static int 1371 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1372 { 1373 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1374 struct sbuf sb; 1375 char buf[128]; 1376 int error, i; 1377 uintmax_t fract, sum, whole; 1378 1379 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1380 sum = 0; 1381 for (i = 0; i < sc->cpu_cx_count; i++) 1382 sum += sc->cpu_cx_stats[i]; 1383 for (i = 0; i < sc->cpu_cx_count; i++) { 1384 if (sum > 0) { 1385 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1386 fract = (whole % sum) * 100; 1387 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1388 (u_int)(fract / sum)); 1389 } else 1390 sbuf_printf(&sb, "0.00%% "); 1391 } 1392 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1393 error = sbuf_finish(&sb); 1394 sbuf_delete(&sb); 1395 return (error); 1396 } 1397 1398 /* 1399 * XXX TODO: actually add support to count each entry/exit 1400 * from the Cx states. 1401 */ 1402 static int 1403 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1404 { 1405 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1406 struct sbuf sb; 1407 char buf[128]; 1408 int error, i; 1409 1410 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1411 for (i = 0; i < sc->cpu_cx_count; i++) { 1412 if (i > 0) 1413 sbuf_putc(&sb, ' '); 1414 sbuf_printf(&sb, "%u", sc->cpu_cx_stats[i]); 1415 } 1416 error = sbuf_finish(&sb); 1417 sbuf_delete(&sb); 1418 return (error); 1419 } 1420 1421 static int 1422 acpi_cpu_duration_counters_sysctl(SYSCTL_HANDLER_ARGS) 1423 { 1424 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1425 struct sbuf sb; 1426 char buf[128]; 1427 int error, i; 1428 1429 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1430 for (i = 0; i < sc->cpu_cx_count; i++) { 1431 if (i > 0) 1432 sbuf_putc(&sb, ' '); 1433 sbuf_printf(&sb, "%ju", (uintmax_t) sc->cpu_cx_duration[i]); 1434 } 1435 error = sbuf_finish(&sb); 1436 sbuf_delete(&sb); 1437 return (error); 1438 } 1439 1440 1441 #if defined(__i386__) || defined(__amd64__) 1442 static int 1443 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1444 { 1445 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1446 struct acpi_cx *cx; 1447 struct sbuf sb; 1448 char buf[128]; 1449 int error, i; 1450 1451 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1452 for (i = 0; i < sc->cpu_cx_count; i++) { 1453 cx = &sc->cpu_cx_states[i]; 1454 if (i > 0) 1455 sbuf_putc(&sb, ' '); 1456 sbuf_printf(&sb, "C%d/", i + 1); 1457 if (cx->do_mwait) { 1458 sbuf_cat(&sb, "mwait"); 1459 if (cx->mwait_hw_coord) 1460 sbuf_cat(&sb, "/hwc"); 1461 if (cx->mwait_bm_avoidance) 1462 sbuf_cat(&sb, "/bma"); 1463 } else if (cx->type == ACPI_STATE_C1) { 1464 sbuf_cat(&sb, "hlt"); 1465 } else { 1466 sbuf_cat(&sb, "io"); 1467 } 1468 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1469 sbuf_cat(&sb, "/iohlt"); 1470 } 1471 error = sbuf_finish(&sb); 1472 sbuf_delete(&sb); 1473 return (error); 1474 } 1475 #endif 1476 1477 static int 1478 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1479 { 1480 int i; 1481 1482 ACPI_SERIAL_ASSERT(cpu); 1483 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1484 1485 /* If not disabling, cache the new lowest non-C3 state. */ 1486 sc->cpu_non_c3 = 0; 1487 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1488 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1489 sc->cpu_non_c3 = i; 1490 break; 1491 } 1492 } 1493 1494 /* Reset the statistics counters. */ 1495 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1496 return (0); 1497 } 1498 1499 static int 1500 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1501 { 1502 struct acpi_cpu_softc *sc; 1503 char state[8]; 1504 int val, error; 1505 1506 sc = (struct acpi_cpu_softc *) arg1; 1507 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1508 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1509 if (error != 0 || req->newptr == NULL) 1510 return (error); 1511 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1512 return (EINVAL); 1513 if (strcasecmp(state, "Cmax") == 0) 1514 val = MAX_CX_STATES; 1515 else { 1516 val = (int) strtol(state + 1, NULL, 10); 1517 if (val < 1 || val > MAX_CX_STATES) 1518 return (EINVAL); 1519 } 1520 1521 ACPI_SERIAL_BEGIN(cpu); 1522 sc->cpu_cx_lowest_lim = val - 1; 1523 acpi_cpu_set_cx_lowest(sc); 1524 ACPI_SERIAL_END(cpu); 1525 1526 return (0); 1527 } 1528 1529 static int 1530 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1531 { 1532 struct acpi_cpu_softc *sc; 1533 char state[8]; 1534 int val, error, i; 1535 1536 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1537 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1538 if (error != 0 || req->newptr == NULL) 1539 return (error); 1540 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1541 return (EINVAL); 1542 if (strcasecmp(state, "Cmax") == 0) 1543 val = MAX_CX_STATES; 1544 else { 1545 val = (int) strtol(state + 1, NULL, 10); 1546 if (val < 1 || val > MAX_CX_STATES) 1547 return (EINVAL); 1548 } 1549 1550 /* Update the new lowest useable Cx state for all CPUs. */ 1551 ACPI_SERIAL_BEGIN(cpu); 1552 cpu_cx_lowest_lim = val - 1; 1553 CPU_FOREACH(i) { 1554 if ((sc = cpu_softc[i]) == NULL) 1555 continue; 1556 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1557 acpi_cpu_set_cx_lowest(sc); 1558 } 1559 ACPI_SERIAL_END(cpu); 1560 1561 return (0); 1562 } 1563