1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 118 119 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 120 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 121 122 #define PCI_VENDOR_INTEL 0x8086 123 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 124 #define PCI_REVISION_A_STEP 0 125 #define PCI_REVISION_B_STEP 1 126 #define PCI_REVISION_4E 2 127 #define PCI_REVISION_4M 3 128 #define PIIX4_DEVACTB_REG 0x58 129 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 130 #define PIIX4_BRLD_EN_IRQ (1<<1) 131 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 132 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 133 #define PIIX4_PCNTRL_BST_EN (1<<10) 134 135 #define CST_FFH_VENDOR_INTEL 1 136 #define CST_FFH_INTEL_CL_C1IO 1 137 #define CST_FFH_INTEL_CL_MWAIT 2 138 #define CST_FFH_MWAIT_HW_COORD 0x0001 139 #define CST_FFH_MWAIT_BM_AVOID 0x0002 140 141 #define CPUDEV_DEVICE_ID "ACPI0007" 142 143 /* Knob to disable acpi_cpu devices */ 144 bool acpi_cpu_disabled = false; 145 146 /* Platform hardware resource information. */ 147 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 148 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 149 static int cpu_quirks; /* Indicate any hardware bugs. */ 150 151 /* Values for sysctl. */ 152 static struct sysctl_ctx_list cpu_sysctl_ctx; 153 static struct sysctl_oid *cpu_sysctl_tree; 154 static int cpu_cx_generic; 155 static int cpu_cx_lowest_lim; 156 157 static struct acpi_cpu_softc **cpu_softc; 158 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 159 160 static int acpi_cpu_probe(device_t dev); 161 static int acpi_cpu_attach(device_t dev); 162 static int acpi_cpu_suspend(device_t dev); 163 static int acpi_cpu_resume(device_t dev); 164 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, 165 u_int *cpu_id); 166 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 167 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 168 int unit); 169 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 170 uintptr_t *result); 171 static int acpi_cpu_shutdown(device_t dev); 172 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 173 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 174 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 175 static void acpi_cpu_startup(void *arg); 176 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 177 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 178 #if defined(__i386__) || defined(__amd64__) 179 static void acpi_cpu_idle(sbintime_t sbt); 180 #endif 181 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 182 static void acpi_cpu_quirks(void); 183 static void acpi_cpu_quirks_piix4(void); 184 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 185 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 186 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 187 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 188 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 189 #if defined(__i386__) || defined(__amd64__) 190 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 191 #endif 192 193 static device_method_t acpi_cpu_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, acpi_cpu_probe), 196 DEVMETHOD(device_attach, acpi_cpu_attach), 197 DEVMETHOD(device_detach, bus_generic_detach), 198 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 199 DEVMETHOD(device_suspend, acpi_cpu_suspend), 200 DEVMETHOD(device_resume, acpi_cpu_resume), 201 202 /* Bus interface */ 203 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 204 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 205 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 206 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 207 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 208 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 209 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 210 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 211 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 212 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 213 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 214 215 DEVMETHOD_END 216 }; 217 218 static driver_t acpi_cpu_driver = { 219 "cpu", 220 acpi_cpu_methods, 221 sizeof(struct acpi_cpu_softc), 222 }; 223 224 static devclass_t acpi_cpu_devclass; 225 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 226 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 227 228 static int 229 acpi_cpu_probe(device_t dev) 230 { 231 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL }; 232 int acpi_id, cpu_id; 233 ACPI_BUFFER buf; 234 ACPI_HANDLE handle; 235 ACPI_OBJECT *obj; 236 ACPI_STATUS status; 237 ACPI_OBJECT_TYPE type; 238 239 if (acpi_disabled("cpu") || acpi_cpu_disabled) 240 return (ENXIO); 241 type = acpi_get_type(dev); 242 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE) 243 return (ENXIO); 244 if (type == ACPI_TYPE_DEVICE && 245 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0) 246 return (ENXIO); 247 248 handle = acpi_get_handle(dev); 249 if (cpu_softc == NULL) 250 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 251 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 252 253 if (type == ACPI_TYPE_PROCESSOR) { 254 /* Get our Processor object. */ 255 buf.Pointer = NULL; 256 buf.Length = ACPI_ALLOCATE_BUFFER; 257 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 258 if (ACPI_FAILURE(status)) { 259 device_printf(dev, "probe failed to get Processor obj - %s\n", 260 AcpiFormatException(status)); 261 return (ENXIO); 262 } 263 obj = (ACPI_OBJECT *)buf.Pointer; 264 if (obj->Type != ACPI_TYPE_PROCESSOR) { 265 device_printf(dev, "Processor object has bad type %d\n", 266 obj->Type); 267 AcpiOsFree(obj); 268 return (ENXIO); 269 } 270 271 /* 272 * Find the processor associated with our unit. We could use the 273 * ProcId as a key, however, some boxes do not have the same values 274 * in their Processor object as the ProcId values in the MADT. 275 */ 276 acpi_id = obj->Processor.ProcId; 277 AcpiOsFree(obj); 278 } else { 279 status = acpi_GetInteger(handle, "_UID", &acpi_id); 280 if (ACPI_FAILURE(status)) { 281 device_printf(dev, "Device object has bad value - %s\n", 282 AcpiFormatException(status)); 283 return (ENXIO); 284 } 285 } 286 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) { 287 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255)) 288 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 289 acpi_name(acpi_get_handle(dev)), acpi_id); 290 return (ENXIO); 291 } 292 293 if (device_set_unit(dev, cpu_id) != 0) 294 return (ENXIO); 295 296 device_set_desc(dev, "ACPI CPU"); 297 298 if (!bootverbose && device_get_unit(dev) != 0) { 299 device_quiet(dev); 300 device_quiet_children(dev); 301 } 302 303 return (BUS_PROBE_DEFAULT); 304 } 305 306 static int 307 acpi_cpu_attach(device_t dev) 308 { 309 ACPI_BUFFER buf; 310 ACPI_OBJECT arg, *obj; 311 ACPI_OBJECT_LIST arglist; 312 struct pcpu *pcpu_data; 313 struct acpi_cpu_softc *sc; 314 struct acpi_softc *acpi_sc; 315 ACPI_STATUS status; 316 u_int features; 317 int cpu_id, drv_count, i; 318 driver_t **drivers; 319 uint32_t cap_set[3]; 320 321 /* UUID needed by _OSC evaluation */ 322 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 323 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 324 0x58, 0x71, 0x39, 0x53 }; 325 326 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 327 328 sc = device_get_softc(dev); 329 sc->cpu_dev = dev; 330 sc->cpu_handle = acpi_get_handle(dev); 331 cpu_id = device_get_unit(dev); 332 cpu_softc[cpu_id] = sc; 333 pcpu_data = pcpu_find(cpu_id); 334 pcpu_data->pc_device = dev; 335 sc->cpu_pcpu = pcpu_data; 336 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 337 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 338 339 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) { 340 buf.Pointer = NULL; 341 buf.Length = ACPI_ALLOCATE_BUFFER; 342 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 343 if (ACPI_FAILURE(status)) { 344 device_printf(dev, "attach failed to get Processor obj - %s\n", 345 AcpiFormatException(status)); 346 return (ENXIO); 347 } 348 obj = (ACPI_OBJECT *)buf.Pointer; 349 sc->cpu_p_blk = obj->Processor.PblkAddress; 350 sc->cpu_p_blk_len = obj->Processor.PblkLength; 351 sc->cpu_acpi_id = obj->Processor.ProcId; 352 AcpiOsFree(obj); 353 } else { 354 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE, 355 ("Unexpected ACPI object")); 356 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id); 357 if (ACPI_FAILURE(status)) { 358 device_printf(dev, "Device object has bad value - %s\n", 359 AcpiFormatException(status)); 360 return (ENXIO); 361 } 362 sc->cpu_p_blk = 0; 363 sc->cpu_p_blk_len = 0; 364 } 365 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 366 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 367 368 /* 369 * If this is the first cpu we attach, create and initialize the generic 370 * resources that will be used by all acpi cpu devices. 371 */ 372 if (device_get_unit(dev) == 0) { 373 /* Assume we won't be using generic Cx mode by default */ 374 cpu_cx_generic = FALSE; 375 376 /* Install hw.acpi.cpu sysctl tree */ 377 acpi_sc = acpi_device_get_parent_softc(dev); 378 sysctl_ctx_init(&cpu_sysctl_ctx); 379 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 380 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 381 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children"); 382 } 383 384 /* 385 * Before calling any CPU methods, collect child driver feature hints 386 * and notify ACPI of them. We support unified SMP power control 387 * so advertise this ourselves. Note this is not the same as independent 388 * SMP control where each CPU can have different settings. 389 */ 390 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 391 ACPI_CAP_C1_IO_HALT; 392 393 #if defined(__i386__) || defined(__amd64__) 394 /* 395 * Ask for MWAIT modes if not disabled and interrupts work 396 * reasonable with MWAIT. 397 */ 398 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 399 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 400 #endif 401 402 if (devclass_get_drivers(device_get_devclass(dev), &drivers, 403 &drv_count) == 0) { 404 for (i = 0; i < drv_count; i++) { 405 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 406 sc->cpu_features |= features; 407 } 408 free(drivers, M_TEMP); 409 } 410 411 /* 412 * CPU capabilities are specified in 413 * Intel Processor Vendor-Specific ACPI Interface Specification. 414 */ 415 if (sc->cpu_features) { 416 cap_set[1] = sc->cpu_features; 417 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 418 cap_set, false); 419 if (ACPI_SUCCESS(status)) { 420 if (cap_set[0] != 0) 421 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 422 } 423 else { 424 arglist.Pointer = &arg; 425 arglist.Count = 1; 426 arg.Type = ACPI_TYPE_BUFFER; 427 arg.Buffer.Length = sizeof(cap_set); 428 arg.Buffer.Pointer = (uint8_t *)cap_set; 429 cap_set[0] = 1; /* revision */ 430 cap_set[1] = 1; /* number of capabilities integers */ 431 cap_set[2] = sc->cpu_features; 432 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 433 } 434 } 435 436 /* Probe for Cx state support. */ 437 acpi_cpu_cx_probe(sc); 438 439 return (0); 440 } 441 442 static void 443 acpi_cpu_postattach(void *unused __unused) 444 { 445 struct acpi_cpu_softc *sc; 446 int attached = 0, i; 447 448 if (cpu_softc == NULL) 449 return; 450 451 bus_topo_lock(); 452 CPU_FOREACH(i) { 453 if ((sc = cpu_softc[i]) != NULL) 454 bus_generic_probe(sc->cpu_dev); 455 } 456 CPU_FOREACH(i) { 457 if ((sc = cpu_softc[i]) != NULL) { 458 bus_generic_attach(sc->cpu_dev); 459 attached = 1; 460 } 461 } 462 bus_topo_unlock(); 463 464 if (attached) { 465 #ifdef EARLY_AP_STARTUP 466 acpi_cpu_startup(NULL); 467 #else 468 /* Queue post cpu-probing task handler */ 469 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 470 #endif 471 } 472 } 473 474 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 475 acpi_cpu_postattach, NULL); 476 477 static void 478 disable_idle(struct acpi_cpu_softc *sc) 479 { 480 cpuset_t cpuset; 481 482 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 483 sc->cpu_disable_idle = TRUE; 484 485 /* 486 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 487 * Note that this code depends on the fact that the rendezvous IPI 488 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 489 * is called and executed in such a context with interrupts being re-enabled 490 * right before return. 491 */ 492 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 493 smp_no_rendezvous_barrier, NULL); 494 } 495 496 static void 497 enable_idle(struct acpi_cpu_softc *sc) 498 { 499 500 sc->cpu_disable_idle = FALSE; 501 } 502 503 #if defined(__i386__) || defined(__amd64__) 504 static int 505 is_idle_disabled(struct acpi_cpu_softc *sc) 506 { 507 508 return (sc->cpu_disable_idle); 509 } 510 #endif 511 512 /* 513 * Disable any entry to the idle function during suspend and re-enable it 514 * during resume. 515 */ 516 static int 517 acpi_cpu_suspend(device_t dev) 518 { 519 int error; 520 521 error = bus_generic_suspend(dev); 522 if (error) 523 return (error); 524 disable_idle(device_get_softc(dev)); 525 return (0); 526 } 527 528 static int 529 acpi_cpu_resume(device_t dev) 530 { 531 532 enable_idle(device_get_softc(dev)); 533 return (bus_generic_resume(dev)); 534 } 535 536 /* 537 * Find the processor associated with a given ACPI ID. 538 */ 539 static int 540 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id) 541 { 542 struct pcpu *pc; 543 u_int i; 544 545 CPU_FOREACH(i) { 546 pc = pcpu_find(i); 547 if (pc->pc_acpi_id == acpi_id) { 548 *cpu_id = pc->pc_cpuid; 549 return (0); 550 } 551 } 552 553 /* 554 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 555 * UP box) use the ACPI ID from the first processor we find. 556 */ 557 if (mp_ncpus == 1) { 558 pc = pcpu_find(0); 559 if (pc->pc_acpi_id == 0xffffffff) 560 pc->pc_acpi_id = acpi_id; 561 *cpu_id = 0; 562 return (0); 563 } 564 565 return (ESRCH); 566 } 567 568 static struct resource_list * 569 acpi_cpu_get_rlist(device_t dev, device_t child) 570 { 571 struct acpi_cpu_device *ad; 572 573 ad = device_get_ivars(child); 574 if (ad == NULL) 575 return (NULL); 576 return (&ad->ad_rl); 577 } 578 579 static device_t 580 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 581 { 582 struct acpi_cpu_device *ad; 583 device_t child; 584 585 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 586 return (NULL); 587 588 resource_list_init(&ad->ad_rl); 589 590 child = device_add_child_ordered(dev, order, name, unit); 591 if (child != NULL) 592 device_set_ivars(child, ad); 593 else 594 free(ad, M_TEMP); 595 return (child); 596 } 597 598 static int 599 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 600 { 601 struct acpi_cpu_softc *sc; 602 603 sc = device_get_softc(dev); 604 switch (index) { 605 case ACPI_IVAR_HANDLE: 606 *result = (uintptr_t)sc->cpu_handle; 607 break; 608 case CPU_IVAR_PCPU: 609 *result = (uintptr_t)sc->cpu_pcpu; 610 break; 611 #if defined(__amd64__) || defined(__i386__) 612 case CPU_IVAR_NOMINAL_MHZ: 613 if (tsc_is_invariant) { 614 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 615 break; 616 } 617 /* FALLTHROUGH */ 618 #endif 619 default: 620 return (ENOENT); 621 } 622 return (0); 623 } 624 625 static int 626 acpi_cpu_shutdown(device_t dev) 627 { 628 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 629 630 /* Allow children to shutdown first. */ 631 bus_generic_shutdown(dev); 632 633 /* 634 * Disable any entry to the idle function. 635 */ 636 disable_idle(device_get_softc(dev)); 637 638 /* 639 * CPU devices are not truly detached and remain referenced, 640 * so their resources are not freed. 641 */ 642 643 return_VALUE (0); 644 } 645 646 static void 647 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 648 { 649 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 650 651 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 652 sc->cpu_prev_sleep = 1000000; 653 sc->cpu_cx_lowest = 0; 654 sc->cpu_cx_lowest_lim = 0; 655 656 /* 657 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 658 * any, we'll revert to generic FADT/P_BLK Cx control method which will 659 * be handled by acpi_cpu_startup. We need to defer to after having 660 * probed all the cpus in the system before probing for generic Cx 661 * states as we may already have found cpus with valid _CST packages 662 */ 663 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 664 /* 665 * We were unable to find a _CST package for this cpu or there 666 * was an error parsing it. Switch back to generic mode. 667 */ 668 cpu_cx_generic = TRUE; 669 if (bootverbose) 670 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 671 } 672 673 /* 674 * TODO: _CSD Package should be checked here. 675 */ 676 } 677 678 static void 679 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 680 { 681 ACPI_GENERIC_ADDRESS gas; 682 struct acpi_cx *cx_ptr; 683 684 sc->cpu_cx_count = 0; 685 cx_ptr = sc->cpu_cx_states; 686 687 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 688 sc->cpu_prev_sleep = 1000000; 689 690 /* C1 has been required since just after ACPI 1.0 */ 691 cx_ptr->type = ACPI_STATE_C1; 692 cx_ptr->trans_lat = 0; 693 cx_ptr++; 694 sc->cpu_non_c2 = sc->cpu_cx_count; 695 sc->cpu_non_c3 = sc->cpu_cx_count; 696 sc->cpu_cx_count++; 697 698 /* 699 * The spec says P_BLK must be 6 bytes long. However, some systems 700 * use it to indicate a fractional set of features present so we 701 * take 5 as C2. Some may also have a value of 7 to indicate 702 * another C3 but most use _CST for this (as required) and having 703 * "only" C1-C3 is not a hardship. 704 */ 705 if (sc->cpu_p_blk_len < 5) 706 return; 707 708 /* Validate and allocate resources for C2 (P_LVL2). */ 709 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 710 gas.BitWidth = 8; 711 if (AcpiGbl_FADT.C2Latency <= 100) { 712 gas.Address = sc->cpu_p_blk + 4; 713 cx_ptr->res_rid = 0; 714 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 715 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 716 if (cx_ptr->p_lvlx != NULL) { 717 cx_ptr->type = ACPI_STATE_C2; 718 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 719 cx_ptr++; 720 sc->cpu_non_c3 = sc->cpu_cx_count; 721 sc->cpu_cx_count++; 722 } 723 } 724 if (sc->cpu_p_blk_len < 6) 725 return; 726 727 /* Validate and allocate resources for C3 (P_LVL3). */ 728 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 729 gas.Address = sc->cpu_p_blk + 5; 730 cx_ptr->res_rid = 1; 731 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 732 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 733 if (cx_ptr->p_lvlx != NULL) { 734 cx_ptr->type = ACPI_STATE_C3; 735 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 736 cx_ptr++; 737 sc->cpu_cx_count++; 738 } 739 } 740 } 741 742 #if defined(__i386__) || defined(__amd64__) 743 static void 744 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 745 { 746 747 cx_ptr->do_mwait = true; 748 cx_ptr->mwait_hint = address & 0xffffffff; 749 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 750 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 751 } 752 #endif 753 754 static void 755 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 756 { 757 758 if (cx_ptr->p_lvlx == NULL) 759 return; 760 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 761 cx_ptr->p_lvlx); 762 cx_ptr->p_lvlx = NULL; 763 } 764 765 /* 766 * Parse a _CST package and set up its Cx states. Since the _CST object 767 * can change dynamically, our notify handler may call this function 768 * to clean up and probe the new _CST package. 769 */ 770 static int 771 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 772 { 773 struct acpi_cx *cx_ptr; 774 ACPI_STATUS status; 775 ACPI_BUFFER buf; 776 ACPI_OBJECT *top; 777 ACPI_OBJECT *pkg; 778 uint32_t count; 779 int i; 780 #if defined(__i386__) || defined(__amd64__) 781 uint64_t address; 782 int vendor, class, accsize; 783 #endif 784 785 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 786 787 buf.Pointer = NULL; 788 buf.Length = ACPI_ALLOCATE_BUFFER; 789 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 790 if (ACPI_FAILURE(status)) 791 return (ENXIO); 792 793 /* _CST is a package with a count and at least one Cx package. */ 794 top = (ACPI_OBJECT *)buf.Pointer; 795 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 796 device_printf(sc->cpu_dev, "invalid _CST package\n"); 797 AcpiOsFree(buf.Pointer); 798 return (ENXIO); 799 } 800 if (count != top->Package.Count - 1) { 801 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 802 count, top->Package.Count - 1); 803 count = top->Package.Count - 1; 804 } 805 if (count > MAX_CX_STATES) { 806 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 807 count = MAX_CX_STATES; 808 } 809 810 sc->cpu_non_c2 = 0; 811 sc->cpu_non_c3 = 0; 812 sc->cpu_cx_count = 0; 813 cx_ptr = sc->cpu_cx_states; 814 815 /* 816 * C1 has been required since just after ACPI 1.0. 817 * Reserve the first slot for it. 818 */ 819 cx_ptr->type = ACPI_STATE_C0; 820 cx_ptr++; 821 sc->cpu_cx_count++; 822 823 /* Set up all valid states. */ 824 for (i = 0; i < count; i++) { 825 pkg = &top->Package.Elements[i + 1]; 826 if (!ACPI_PKG_VALID(pkg, 4) || 827 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 828 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 829 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 830 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 831 continue; 832 } 833 834 /* Validate the state to see if we should use it. */ 835 switch (cx_ptr->type) { 836 case ACPI_STATE_C1: 837 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 838 #if defined(__i386__) || defined(__amd64__) 839 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 840 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 841 if (class == CST_FFH_INTEL_CL_C1IO) { 842 /* C1 I/O then Halt */ 843 cx_ptr->res_rid = sc->cpu_cx_count; 844 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 845 cx_ptr->res_rid, address, 1); 846 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 847 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 848 RF_SHAREABLE); 849 if (cx_ptr->p_lvlx == NULL) { 850 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 851 cx_ptr->res_rid); 852 device_printf(sc->cpu_dev, 853 "C1 I/O failed to allocate port %d, " 854 "degrading to C1 Halt", (int)address); 855 } 856 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 857 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 858 } 859 } 860 #endif 861 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 862 /* This is the first C1 state. Use the reserved slot. */ 863 sc->cpu_cx_states[0] = *cx_ptr; 864 } else { 865 sc->cpu_non_c2 = sc->cpu_cx_count; 866 sc->cpu_non_c3 = sc->cpu_cx_count; 867 cx_ptr++; 868 sc->cpu_cx_count++; 869 } 870 continue; 871 case ACPI_STATE_C2: 872 sc->cpu_non_c3 = sc->cpu_cx_count; 873 break; 874 case ACPI_STATE_C3: 875 default: 876 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 877 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 878 "acpi_cpu%d: C3[%d] not available.\n", 879 device_get_unit(sc->cpu_dev), i)); 880 continue; 881 } 882 break; 883 } 884 885 /* Free up any previous register. */ 886 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 887 888 /* Allocate the control register for C2 or C3. */ 889 #if defined(__i386__) || defined(__amd64__) 890 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 891 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 892 class == CST_FFH_INTEL_CL_MWAIT) { 893 /* Native C State Instruction use (mwait) */ 894 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 895 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 896 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 897 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 898 cx_ptr++; 899 sc->cpu_cx_count++; 900 } else 901 #endif 902 { 903 cx_ptr->res_rid = sc->cpu_cx_count; 904 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 905 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 906 if (cx_ptr->p_lvlx) { 907 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 908 "acpi_cpu%d: Got C%d - %d latency\n", 909 device_get_unit(sc->cpu_dev), cx_ptr->type, 910 cx_ptr->trans_lat)); 911 cx_ptr++; 912 sc->cpu_cx_count++; 913 } 914 } 915 } 916 AcpiOsFree(buf.Pointer); 917 918 /* If C1 state was not found, we need one now. */ 919 cx_ptr = sc->cpu_cx_states; 920 if (cx_ptr->type == ACPI_STATE_C0) { 921 cx_ptr->type = ACPI_STATE_C1; 922 cx_ptr->trans_lat = 0; 923 } 924 925 return (0); 926 } 927 928 /* 929 * Call this *after* all CPUs have been attached. 930 */ 931 static void 932 acpi_cpu_startup(void *arg) 933 { 934 struct acpi_cpu_softc *sc; 935 int i; 936 937 /* 938 * Setup any quirks that might necessary now that we have probed 939 * all the CPUs 940 */ 941 acpi_cpu_quirks(); 942 943 if (cpu_cx_generic) { 944 /* 945 * We are using generic Cx mode, probe for available Cx states 946 * for all processors. 947 */ 948 CPU_FOREACH(i) { 949 if ((sc = cpu_softc[i]) != NULL) 950 acpi_cpu_generic_cx_probe(sc); 951 } 952 } else { 953 /* 954 * We are using _CST mode, remove C3 state if necessary. 955 * As we now know for sure that we will be using _CST mode 956 * install our notify handler. 957 */ 958 CPU_FOREACH(i) { 959 if ((sc = cpu_softc[i]) == NULL) 960 continue; 961 if (cpu_quirks & CPU_QUIRK_NO_C3) { 962 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 963 } 964 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 965 acpi_cpu_notify, sc); 966 } 967 } 968 969 /* Perform Cx final initialization. */ 970 CPU_FOREACH(i) { 971 if ((sc = cpu_softc[i]) != NULL) 972 acpi_cpu_startup_cx(sc); 973 } 974 975 /* Add a sysctl handler to handle global Cx lowest setting */ 976 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 977 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 978 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 979 "Global lowest Cx sleep state to use"); 980 981 /* Take over idling from cpu_idle_default(). */ 982 cpu_cx_lowest_lim = 0; 983 CPU_FOREACH(i) { 984 if ((sc = cpu_softc[i]) != NULL) 985 enable_idle(sc); 986 } 987 #if defined(__i386__) || defined(__amd64__) 988 cpu_idle_hook = acpi_cpu_idle; 989 #endif 990 } 991 992 static void 993 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 994 { 995 struct sbuf sb; 996 int i; 997 998 /* 999 * Set up the list of Cx states 1000 */ 1001 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1002 SBUF_FIXEDLEN); 1003 for (i = 0; i < sc->cpu_cx_count; i++) 1004 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1005 sc->cpu_cx_states[i].trans_lat); 1006 sbuf_trim(&sb); 1007 sbuf_finish(&sb); 1008 } 1009 1010 static void 1011 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1012 { 1013 acpi_cpu_cx_list(sc); 1014 1015 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1016 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1017 OID_AUTO, "cx_supported", CTLFLAG_RD, 1018 sc->cpu_cx_supported, 0, 1019 "Cx/microsecond values for supported Cx states"); 1020 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1021 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1022 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1023 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1024 "lowest Cx sleep state to use"); 1025 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1026 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1027 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1028 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1029 "percent usage for each Cx state"); 1030 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1031 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1032 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1033 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1034 "Cx sleep state counters"); 1035 #if defined(__i386__) || defined(__amd64__) 1036 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1037 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1038 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1039 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods"); 1040 #endif 1041 1042 /* Signal platform that we can handle _CST notification. */ 1043 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1044 ACPI_LOCK(acpi); 1045 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1046 ACPI_UNLOCK(acpi); 1047 } 1048 } 1049 1050 #if defined(__i386__) || defined(__amd64__) 1051 /* 1052 * Idle the CPU in the lowest state possible. This function is called with 1053 * interrupts disabled. Note that once it re-enables interrupts, a task 1054 * switch can occur so do not access shared data (i.e. the softc) after 1055 * interrupts are re-enabled. 1056 */ 1057 static void 1058 acpi_cpu_idle(sbintime_t sbt) 1059 { 1060 struct acpi_cpu_softc *sc; 1061 struct acpi_cx *cx_next; 1062 uint64_t start_ticks, end_ticks; 1063 uint32_t start_time, end_time; 1064 ACPI_STATUS status; 1065 int bm_active, cx_next_idx, i, us; 1066 1067 /* 1068 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1069 * since there is no ACPI processor object for this CPU. This occurs 1070 * for logical CPUs in the HTT case. 1071 */ 1072 sc = cpu_softc[PCPU_GET(cpuid)]; 1073 if (sc == NULL) { 1074 acpi_cpu_c1(); 1075 return; 1076 } 1077 1078 /* If disabled, take the safe path. */ 1079 if (is_idle_disabled(sc)) { 1080 acpi_cpu_c1(); 1081 return; 1082 } 1083 1084 /* Find the lowest state that has small enough latency. */ 1085 us = sc->cpu_prev_sleep; 1086 if (sbt >= 0 && us > (sbt >> 12)) 1087 us = (sbt >> 12); 1088 cx_next_idx = 0; 1089 if (cpu_disable_c2_sleep) 1090 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1091 else if (cpu_disable_c3_sleep) 1092 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1093 else 1094 i = sc->cpu_cx_lowest; 1095 for (; i >= 0; i--) { 1096 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1097 cx_next_idx = i; 1098 break; 1099 } 1100 } 1101 1102 /* 1103 * Check for bus master activity. If there was activity, clear 1104 * the bit and use the lowest non-C3 state. Note that the USB 1105 * driver polling for new devices keeps this bit set all the 1106 * time if USB is loaded. 1107 */ 1108 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1109 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1110 cx_next_idx > sc->cpu_non_c3 && 1111 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) { 1112 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1113 if (ACPI_SUCCESS(status) && bm_active != 0) { 1114 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1115 cx_next_idx = sc->cpu_non_c3; 1116 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1117 } 1118 } 1119 1120 /* Select the next state and update statistics. */ 1121 sc->cpu_cx_stats[cx_next_idx]++; 1122 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1123 1124 /* 1125 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1126 * precisely calculate the time spent in C1 since the place we wake up 1127 * is an ISR. Assume we slept no more then half of quantum, unless 1128 * we are called inside critical section, delaying context switch. 1129 */ 1130 if (cx_next->type == ACPI_STATE_C1) { 1131 start_ticks = cpu_ticks(); 1132 if (cx_next->p_lvlx != NULL) { 1133 /* C1 I/O then Halt */ 1134 CPU_GET_REG(cx_next->p_lvlx, 1); 1135 } 1136 if (cx_next->do_mwait) 1137 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1138 else 1139 acpi_cpu_c1(); 1140 end_ticks = cpu_ticks(); 1141 /* acpi_cpu_c1() returns with interrupts enabled. */ 1142 if (cx_next->do_mwait) 1143 ACPI_ENABLE_IRQS(); 1144 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1145 if (!cx_next->do_mwait && curthread->td_critnest == 0) 1146 end_time = min(end_time, 500000 / hz); 1147 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1148 return; 1149 } 1150 1151 /* 1152 * For C3, disable bus master arbitration and enable bus master wake 1153 * if BM control is available, otherwise flush the CPU cache. 1154 */ 1155 if (cx_next->type == ACPI_STATE_C3) { 1156 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1157 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1158 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1159 } else 1160 ACPI_FLUSH_CPU_CACHE(); 1161 } 1162 1163 /* 1164 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1165 * Use the ACPI timer for measuring sleep time. Since we need to 1166 * get the time very close to the CPU start/stop clock logic, this 1167 * is the only reliable time source. 1168 */ 1169 if (cx_next->type == ACPI_STATE_C3) { 1170 AcpiGetTimer(&start_time); 1171 start_ticks = 0; 1172 } else { 1173 start_time = 0; 1174 start_ticks = cpu_ticks(); 1175 } 1176 if (cx_next->do_mwait) { 1177 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1178 } else { 1179 CPU_GET_REG(cx_next->p_lvlx, 1); 1180 /* 1181 * Read the end time twice. Since it may take an arbitrary time 1182 * to enter the idle state, the first read may be executed before 1183 * the processor has stopped. Doing it again provides enough 1184 * margin that we are certain to have a correct value. 1185 */ 1186 AcpiGetTimer(&end_time); 1187 } 1188 1189 if (cx_next->type == ACPI_STATE_C3) 1190 AcpiGetTimer(&end_time); 1191 else 1192 end_ticks = cpu_ticks(); 1193 1194 /* Enable bus master arbitration and disable bus master wakeup. */ 1195 if (cx_next->type == ACPI_STATE_C3 && 1196 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1197 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1198 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1199 } 1200 ACPI_ENABLE_IRQS(); 1201 1202 if (cx_next->type == ACPI_STATE_C3) 1203 AcpiGetTimerDuration(start_time, end_time, &end_time); 1204 else 1205 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1206 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1207 } 1208 #endif 1209 1210 /* 1211 * Re-evaluate the _CST object when we are notified that it changed. 1212 */ 1213 static void 1214 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1215 { 1216 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1217 1218 if (notify != ACPI_NOTIFY_CX_STATES) 1219 return; 1220 1221 /* 1222 * C-state data for target CPU is going to be in flux while we execute 1223 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1224 * Also, it may happen that multiple ACPI taskqueues may concurrently 1225 * execute notifications for the same CPU. ACPI_SERIAL is used to 1226 * protect against that. 1227 */ 1228 ACPI_SERIAL_BEGIN(cpu); 1229 disable_idle(sc); 1230 1231 /* Update the list of Cx states. */ 1232 acpi_cpu_cx_cst(sc); 1233 acpi_cpu_cx_list(sc); 1234 acpi_cpu_set_cx_lowest(sc); 1235 1236 enable_idle(sc); 1237 ACPI_SERIAL_END(cpu); 1238 1239 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1240 } 1241 1242 static void 1243 acpi_cpu_quirks(void) 1244 { 1245 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1246 1247 /* 1248 * Bus mastering arbitration control is needed to keep caches coherent 1249 * while sleeping in C3. If it's not present but a working flush cache 1250 * instruction is present, flush the caches before entering C3 instead. 1251 * Otherwise, just disable C3 completely. 1252 */ 1253 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1254 AcpiGbl_FADT.Pm2ControlLength == 0) { 1255 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1256 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1257 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1258 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1259 "acpi_cpu: no BM control, using flush cache method\n")); 1260 } else { 1261 cpu_quirks |= CPU_QUIRK_NO_C3; 1262 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1263 "acpi_cpu: no BM control, C3 not available\n")); 1264 } 1265 } 1266 1267 /* 1268 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1269 * the expensive flush cache instruction. 1270 */ 1271 if (cpu_cx_generic && mp_ncpus > 1) { 1272 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1273 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1274 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1275 } 1276 1277 /* Look for various quirks of the PIIX4 part. */ 1278 acpi_cpu_quirks_piix4(); 1279 } 1280 1281 static void 1282 acpi_cpu_quirks_piix4(void) 1283 { 1284 #ifdef __i386__ 1285 device_t acpi_dev; 1286 uint32_t val; 1287 ACPI_STATUS status; 1288 1289 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1290 if (acpi_dev != NULL) { 1291 switch (pci_get_revid(acpi_dev)) { 1292 /* 1293 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1294 * do not report the BMIDE status to the BM status register and 1295 * others have a livelock bug if Type-F DMA is enabled. Linux 1296 * works around the BMIDE bug by reading the BM status directly 1297 * but we take the simpler approach of disabling C3 for these 1298 * parts. 1299 * 1300 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1301 * Livelock") from the January 2002 PIIX4 specification update. 1302 * Applies to all PIIX4 models. 1303 * 1304 * Also, make sure that all interrupts cause a "Stop Break" 1305 * event to exit from C2 state. 1306 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1307 * should be set to zero, otherwise it causes C2 to short-sleep. 1308 * PIIX4 doesn't properly support C3 and bus master activity 1309 * need not break out of C2. 1310 */ 1311 case PCI_REVISION_A_STEP: 1312 case PCI_REVISION_B_STEP: 1313 case PCI_REVISION_4E: 1314 case PCI_REVISION_4M: 1315 cpu_quirks |= CPU_QUIRK_NO_C3; 1316 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1317 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1318 1319 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1320 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1321 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1322 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1323 val |= PIIX4_STOP_BREAK_MASK; 1324 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1325 } 1326 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1327 if (ACPI_SUCCESS(status) && val != 0) { 1328 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1329 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1330 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1331 } 1332 break; 1333 default: 1334 break; 1335 } 1336 } 1337 #endif 1338 } 1339 1340 static int 1341 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1342 { 1343 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1344 struct sbuf sb; 1345 char buf[128]; 1346 int error, i; 1347 uintmax_t fract, sum, whole; 1348 1349 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1350 sum = 0; 1351 for (i = 0; i < sc->cpu_cx_count; i++) 1352 sum += sc->cpu_cx_stats[i]; 1353 for (i = 0; i < sc->cpu_cx_count; i++) { 1354 if (sum > 0) { 1355 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1356 fract = (whole % sum) * 100; 1357 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1358 (u_int)(fract / sum)); 1359 } else 1360 sbuf_printf(&sb, "0.00%% "); 1361 } 1362 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1363 error = sbuf_finish(&sb); 1364 sbuf_delete(&sb); 1365 return (error); 1366 } 1367 1368 /* 1369 * XXX TODO: actually add support to count each entry/exit 1370 * from the Cx states. 1371 */ 1372 static int 1373 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1374 { 1375 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1376 struct sbuf sb; 1377 char buf[128]; 1378 int error, i; 1379 1380 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1381 for (i = 0; i < sc->cpu_cx_count; i++) { 1382 if (i > 0) 1383 sbuf_putc(&sb, ' '); 1384 sbuf_printf(&sb, "%u", sc->cpu_cx_stats[i]); 1385 } 1386 error = sbuf_finish(&sb); 1387 sbuf_delete(&sb); 1388 return (error); 1389 } 1390 1391 #if defined(__i386__) || defined(__amd64__) 1392 static int 1393 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1394 { 1395 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1396 struct acpi_cx *cx; 1397 struct sbuf sb; 1398 char buf[128]; 1399 int error, i; 1400 1401 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1402 for (i = 0; i < sc->cpu_cx_count; i++) { 1403 cx = &sc->cpu_cx_states[i]; 1404 if (i > 0) 1405 sbuf_putc(&sb, ' '); 1406 sbuf_printf(&sb, "C%d/", i + 1); 1407 if (cx->do_mwait) { 1408 sbuf_cat(&sb, "mwait"); 1409 if (cx->mwait_hw_coord) 1410 sbuf_cat(&sb, "/hwc"); 1411 if (cx->mwait_bm_avoidance) 1412 sbuf_cat(&sb, "/bma"); 1413 } else if (cx->type == ACPI_STATE_C1) { 1414 sbuf_cat(&sb, "hlt"); 1415 } else { 1416 sbuf_cat(&sb, "io"); 1417 } 1418 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1419 sbuf_cat(&sb, "/iohlt"); 1420 } 1421 error = sbuf_finish(&sb); 1422 sbuf_delete(&sb); 1423 return (error); 1424 } 1425 #endif 1426 1427 static int 1428 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1429 { 1430 int i; 1431 1432 ACPI_SERIAL_ASSERT(cpu); 1433 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1434 1435 /* If not disabling, cache the new lowest non-C3 state. */ 1436 sc->cpu_non_c3 = 0; 1437 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1438 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1439 sc->cpu_non_c3 = i; 1440 break; 1441 } 1442 } 1443 1444 /* Reset the statistics counters. */ 1445 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1446 return (0); 1447 } 1448 1449 static int 1450 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1451 { 1452 struct acpi_cpu_softc *sc; 1453 char state[8]; 1454 int val, error; 1455 1456 sc = (struct acpi_cpu_softc *) arg1; 1457 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1458 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1459 if (error != 0 || req->newptr == NULL) 1460 return (error); 1461 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1462 return (EINVAL); 1463 if (strcasecmp(state, "Cmax") == 0) 1464 val = MAX_CX_STATES; 1465 else { 1466 val = (int) strtol(state + 1, NULL, 10); 1467 if (val < 1 || val > MAX_CX_STATES) 1468 return (EINVAL); 1469 } 1470 1471 ACPI_SERIAL_BEGIN(cpu); 1472 sc->cpu_cx_lowest_lim = val - 1; 1473 acpi_cpu_set_cx_lowest(sc); 1474 ACPI_SERIAL_END(cpu); 1475 1476 return (0); 1477 } 1478 1479 static int 1480 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1481 { 1482 struct acpi_cpu_softc *sc; 1483 char state[8]; 1484 int val, error, i; 1485 1486 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1487 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1488 if (error != 0 || req->newptr == NULL) 1489 return (error); 1490 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1491 return (EINVAL); 1492 if (strcasecmp(state, "Cmax") == 0) 1493 val = MAX_CX_STATES; 1494 else { 1495 val = (int) strtol(state + 1, NULL, 10); 1496 if (val < 1 || val > MAX_CX_STATES) 1497 return (EINVAL); 1498 } 1499 1500 /* Update the new lowest useable Cx state for all CPUs. */ 1501 ACPI_SERIAL_BEGIN(cpu); 1502 cpu_cx_lowest_lim = val - 1; 1503 CPU_FOREACH(i) { 1504 if ((sc = cpu_softc[i]) == NULL) 1505 continue; 1506 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1507 acpi_cpu_set_cx_lowest(sc); 1508 } 1509 ACPI_SERIAL_END(cpu); 1510 1511 return (0); 1512 } 1513