1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sbuf.h> 42 #include <sys/smp.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <machine/atomic.h> 46 #include <machine/bus.h> 47 #if defined(__amd64__) || defined(__i386__) 48 #include <machine/clock.h> 49 #endif 50 #include <sys/rman.h> 51 52 #include <contrib/dev/acpica/include/acpi.h> 53 #include <contrib/dev/acpica/include/accommon.h> 54 55 #include <dev/acpica/acpivar.h> 56 57 /* 58 * Support for ACPI Processor devices, including C[1-3] sleep states. 59 */ 60 61 /* Hooks for the ACPI CA debugging infrastructure */ 62 #define _COMPONENT ACPI_PROCESSOR 63 ACPI_MODULE_NAME("PROCESSOR") 64 65 struct acpi_cx { 66 struct resource *p_lvlx; /* Register to read to enter state. */ 67 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 68 uint32_t trans_lat; /* Transition latency (usec). */ 69 uint32_t power; /* Power consumed (mW). */ 70 int res_type; /* Resource type for p_lvlx. */ 71 }; 72 #define MAX_CX_STATES 8 73 74 struct acpi_cpu_softc { 75 device_t cpu_dev; 76 ACPI_HANDLE cpu_handle; 77 struct pcpu *cpu_pcpu; 78 uint32_t cpu_acpi_id; /* ACPI processor id */ 79 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 80 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 81 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 82 int cpu_cx_count; /* Number of valid Cx states. */ 83 int cpu_prev_sleep;/* Last idle sleep duration. */ 84 int cpu_features; /* Child driver supported features. */ 85 /* Runtime state. */ 86 int cpu_non_c3; /* Index of lowest non-C3 state. */ 87 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 88 /* Values for sysctl. */ 89 struct sysctl_ctx_list cpu_sysctl_ctx; 90 struct sysctl_oid *cpu_sysctl_tree; 91 int cpu_cx_lowest; 92 char cpu_cx_supported[64]; 93 int cpu_rid; 94 }; 95 96 struct acpi_cpu_device { 97 struct resource_list ad_rl; 98 }; 99 100 #define CPU_GET_REG(reg, width) \ 101 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 102 rman_get_bushandle((reg)), 0)) 103 #define CPU_SET_REG(reg, width, val) \ 104 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 105 rman_get_bushandle((reg)), 0, (val))) 106 107 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 108 109 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 110 111 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 112 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 113 114 #define PCI_VENDOR_INTEL 0x8086 115 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 116 #define PCI_REVISION_A_STEP 0 117 #define PCI_REVISION_B_STEP 1 118 #define PCI_REVISION_4E 2 119 #define PCI_REVISION_4M 3 120 #define PIIX4_DEVACTB_REG 0x58 121 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 122 #define PIIX4_BRLD_EN_IRQ (1<<1) 123 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 124 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 125 #define PIIX4_PCNTRL_BST_EN (1<<10) 126 127 /* Platform hardware resource information. */ 128 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 129 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 130 static int cpu_quirks; /* Indicate any hardware bugs. */ 131 132 /* Runtime state. */ 133 static int cpu_disable_idle; /* Disable entry to idle function */ 134 static int cpu_cx_count; /* Number of valid Cx states */ 135 136 /* Values for sysctl. */ 137 static struct sysctl_ctx_list cpu_sysctl_ctx; 138 static struct sysctl_oid *cpu_sysctl_tree; 139 static int cpu_cx_generic; 140 static int cpu_cx_lowest; 141 142 static device_t *cpu_devices; 143 static int cpu_ndevices; 144 static struct acpi_cpu_softc **cpu_softc; 145 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 146 147 static int acpi_cpu_probe(device_t dev); 148 static int acpi_cpu_attach(device_t dev); 149 static int acpi_cpu_suspend(device_t dev); 150 static int acpi_cpu_resume(device_t dev); 151 static int acpi_pcpu_get_id(uint32_t idx, uint32_t *acpi_id, 152 uint32_t *cpu_id); 153 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 154 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 155 int unit); 156 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 157 uintptr_t *result); 158 static int acpi_cpu_shutdown(device_t dev); 159 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 160 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 161 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 162 static void acpi_cpu_startup(void *arg); 163 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 164 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 165 static void acpi_cpu_idle(void); 166 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 167 static int acpi_cpu_quirks(void); 168 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 169 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val); 170 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 171 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 172 173 static device_method_t acpi_cpu_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, acpi_cpu_probe), 176 DEVMETHOD(device_attach, acpi_cpu_attach), 177 DEVMETHOD(device_detach, bus_generic_detach), 178 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 179 DEVMETHOD(device_suspend, acpi_cpu_suspend), 180 DEVMETHOD(device_resume, acpi_cpu_resume), 181 182 /* Bus interface */ 183 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 184 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 185 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 186 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 187 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 188 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 189 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 190 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 191 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 192 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 193 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 194 195 DEVMETHOD_END 196 }; 197 198 static driver_t acpi_cpu_driver = { 199 "cpu", 200 acpi_cpu_methods, 201 sizeof(struct acpi_cpu_softc), 202 }; 203 204 static devclass_t acpi_cpu_devclass; 205 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 206 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 207 208 static int 209 acpi_cpu_probe(device_t dev) 210 { 211 int acpi_id, cpu_id; 212 ACPI_BUFFER buf; 213 ACPI_HANDLE handle; 214 ACPI_OBJECT *obj; 215 ACPI_STATUS status; 216 217 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 218 return (ENXIO); 219 220 handle = acpi_get_handle(dev); 221 if (cpu_softc == NULL) 222 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 223 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 224 225 /* Get our Processor object. */ 226 buf.Pointer = NULL; 227 buf.Length = ACPI_ALLOCATE_BUFFER; 228 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 229 if (ACPI_FAILURE(status)) { 230 device_printf(dev, "probe failed to get Processor obj - %s\n", 231 AcpiFormatException(status)); 232 return (ENXIO); 233 } 234 obj = (ACPI_OBJECT *)buf.Pointer; 235 if (obj->Type != ACPI_TYPE_PROCESSOR) { 236 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 237 AcpiOsFree(obj); 238 return (ENXIO); 239 } 240 241 /* 242 * Find the processor associated with our unit. We could use the 243 * ProcId as a key, however, some boxes do not have the same values 244 * in their Processor object as the ProcId values in the MADT. 245 */ 246 acpi_id = obj->Processor.ProcId; 247 AcpiOsFree(obj); 248 if (acpi_pcpu_get_id(device_get_unit(dev), &acpi_id, &cpu_id) != 0) 249 return (ENXIO); 250 251 /* 252 * Check if we already probed this processor. We scan the bus twice 253 * so it's possible we've already seen this one. 254 */ 255 if (cpu_softc[cpu_id] != NULL) 256 return (ENXIO); 257 258 /* Mark this processor as in-use and save our derived id for attach. */ 259 cpu_softc[cpu_id] = (void *)1; 260 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 261 device_set_desc(dev, "ACPI CPU"); 262 263 return (0); 264 } 265 266 static int 267 acpi_cpu_attach(device_t dev) 268 { 269 ACPI_BUFFER buf; 270 ACPI_OBJECT arg[4], *obj; 271 ACPI_OBJECT_LIST arglist; 272 struct pcpu *pcpu_data; 273 struct acpi_cpu_softc *sc; 274 struct acpi_softc *acpi_sc; 275 ACPI_STATUS status; 276 u_int features; 277 int cpu_id, drv_count, i; 278 driver_t **drivers; 279 uint32_t cap_set[3]; 280 281 /* UUID needed by _OSC evaluation */ 282 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 283 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 284 0x58, 0x71, 0x39, 0x53 }; 285 286 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 287 288 sc = device_get_softc(dev); 289 sc->cpu_dev = dev; 290 sc->cpu_handle = acpi_get_handle(dev); 291 cpu_id = (int)(intptr_t)acpi_get_private(dev); 292 cpu_softc[cpu_id] = sc; 293 pcpu_data = pcpu_find(cpu_id); 294 pcpu_data->pc_device = dev; 295 sc->cpu_pcpu = pcpu_data; 296 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 297 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 298 299 buf.Pointer = NULL; 300 buf.Length = ACPI_ALLOCATE_BUFFER; 301 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 302 if (ACPI_FAILURE(status)) { 303 device_printf(dev, "attach failed to get Processor obj - %s\n", 304 AcpiFormatException(status)); 305 return (ENXIO); 306 } 307 obj = (ACPI_OBJECT *)buf.Pointer; 308 sc->cpu_p_blk = obj->Processor.PblkAddress; 309 sc->cpu_p_blk_len = obj->Processor.PblkLength; 310 sc->cpu_acpi_id = obj->Processor.ProcId; 311 AcpiOsFree(obj); 312 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 313 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 314 315 /* 316 * If this is the first cpu we attach, create and initialize the generic 317 * resources that will be used by all acpi cpu devices. 318 */ 319 if (device_get_unit(dev) == 0) { 320 /* Assume we won't be using generic Cx mode by default */ 321 cpu_cx_generic = FALSE; 322 323 /* Install hw.acpi.cpu sysctl tree */ 324 acpi_sc = acpi_device_get_parent_softc(dev); 325 sysctl_ctx_init(&cpu_sysctl_ctx); 326 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 327 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 328 CTLFLAG_RD, 0, "node for CPU children"); 329 330 /* Queue post cpu-probing task handler */ 331 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 332 } 333 334 /* 335 * Before calling any CPU methods, collect child driver feature hints 336 * and notify ACPI of them. We support unified SMP power control 337 * so advertise this ourselves. Note this is not the same as independent 338 * SMP control where each CPU can have different settings. 339 */ 340 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3; 341 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 342 for (i = 0; i < drv_count; i++) { 343 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 344 sc->cpu_features |= features; 345 } 346 free(drivers, M_TEMP); 347 } 348 349 /* 350 * CPU capabilities are specified in 351 * Intel Processor Vendor-Specific ACPI Interface Specification. 352 */ 353 if (sc->cpu_features) { 354 arglist.Pointer = arg; 355 arglist.Count = 4; 356 arg[0].Type = ACPI_TYPE_BUFFER; 357 arg[0].Buffer.Length = sizeof(cpu_oscuuid); 358 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */ 359 arg[1].Type = ACPI_TYPE_INTEGER; 360 arg[1].Integer.Value = 1; /* revision */ 361 arg[2].Type = ACPI_TYPE_INTEGER; 362 arg[2].Integer.Value = 1; /* count */ 363 arg[3].Type = ACPI_TYPE_BUFFER; 364 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */ 365 arg[3].Buffer.Pointer = (uint8_t *)cap_set; 366 cap_set[0] = 0; /* status */ 367 cap_set[1] = sc->cpu_features; 368 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL); 369 if (ACPI_SUCCESS(status)) { 370 if (cap_set[0] != 0) 371 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 372 } 373 else { 374 arglist.Pointer = arg; 375 arglist.Count = 1; 376 arg[0].Type = ACPI_TYPE_BUFFER; 377 arg[0].Buffer.Length = sizeof(cap_set); 378 arg[0].Buffer.Pointer = (uint8_t *)cap_set; 379 cap_set[0] = 1; /* revision */ 380 cap_set[1] = 1; /* number of capabilities integers */ 381 cap_set[2] = sc->cpu_features; 382 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 383 } 384 } 385 386 /* Probe for Cx state support. */ 387 acpi_cpu_cx_probe(sc); 388 389 return (0); 390 } 391 392 static void 393 acpi_cpu_postattach(void *unused __unused) 394 { 395 device_t *devices; 396 int err; 397 int i, n; 398 399 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 400 if (err != 0) { 401 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 402 return; 403 } 404 for (i = 0; i < n; i++) 405 bus_generic_probe(devices[i]); 406 for (i = 0; i < n; i++) 407 bus_generic_attach(devices[i]); 408 free(devices, M_TEMP); 409 } 410 411 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 412 acpi_cpu_postattach, NULL); 413 414 /* 415 * Disable any entry to the idle function during suspend and re-enable it 416 * during resume. 417 */ 418 static int 419 acpi_cpu_suspend(device_t dev) 420 { 421 int error; 422 423 error = bus_generic_suspend(dev); 424 if (error) 425 return (error); 426 cpu_disable_idle = TRUE; 427 return (0); 428 } 429 430 static int 431 acpi_cpu_resume(device_t dev) 432 { 433 434 cpu_disable_idle = FALSE; 435 return (bus_generic_resume(dev)); 436 } 437 438 /* 439 * Find the nth present CPU and return its pc_cpuid as well as set the 440 * pc_acpi_id from the most reliable source. 441 */ 442 static int 443 acpi_pcpu_get_id(uint32_t idx, uint32_t *acpi_id, uint32_t *cpu_id) 444 { 445 struct pcpu *pcpu_data; 446 uint32_t i; 447 448 KASSERT(acpi_id != NULL, ("Null acpi_id")); 449 KASSERT(cpu_id != NULL, ("Null cpu_id")); 450 CPU_FOREACH(i) { 451 pcpu_data = pcpu_find(i); 452 KASSERT(pcpu_data != NULL, ("no pcpu data for %d", i)); 453 if (idx-- == 0) { 454 /* 455 * If pc_acpi_id was not initialized (e.g., a non-APIC UP box) 456 * override it with the value from the ASL. Otherwise, if the 457 * two don't match, prefer the MADT-derived value. Finally, 458 * return the pc_cpuid to reference this processor. 459 */ 460 if (pcpu_data->pc_acpi_id == 0xffffffff) 461 pcpu_data->pc_acpi_id = *acpi_id; 462 else if (pcpu_data->pc_acpi_id != *acpi_id) 463 *acpi_id = pcpu_data->pc_acpi_id; 464 *cpu_id = pcpu_data->pc_cpuid; 465 return (0); 466 } 467 } 468 469 return (ESRCH); 470 } 471 472 static struct resource_list * 473 acpi_cpu_get_rlist(device_t dev, device_t child) 474 { 475 struct acpi_cpu_device *ad; 476 477 ad = device_get_ivars(child); 478 if (ad == NULL) 479 return (NULL); 480 return (&ad->ad_rl); 481 } 482 483 static device_t 484 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 485 { 486 struct acpi_cpu_device *ad; 487 device_t child; 488 489 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 490 return (NULL); 491 492 resource_list_init(&ad->ad_rl); 493 494 child = device_add_child_ordered(dev, order, name, unit); 495 if (child != NULL) 496 device_set_ivars(child, ad); 497 else 498 free(ad, M_TEMP); 499 return (child); 500 } 501 502 static int 503 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 504 { 505 struct acpi_cpu_softc *sc; 506 507 sc = device_get_softc(dev); 508 switch (index) { 509 case ACPI_IVAR_HANDLE: 510 *result = (uintptr_t)sc->cpu_handle; 511 break; 512 case CPU_IVAR_PCPU: 513 *result = (uintptr_t)sc->cpu_pcpu; 514 break; 515 #if defined(__amd64__) || defined(__i386__) 516 case CPU_IVAR_NOMINAL_MHZ: 517 if (tsc_is_invariant) { 518 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 519 break; 520 } 521 /* FALLTHROUGH */ 522 #endif 523 default: 524 return (ENOENT); 525 } 526 return (0); 527 } 528 529 static int 530 acpi_cpu_shutdown(device_t dev) 531 { 532 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 533 534 /* Allow children to shutdown first. */ 535 bus_generic_shutdown(dev); 536 537 /* 538 * Disable any entry to the idle function. There is a small race where 539 * an idle thread have passed this check but not gone to sleep. This 540 * is ok since device_shutdown() does not free the softc, otherwise 541 * we'd have to be sure all threads were evicted before returning. 542 */ 543 cpu_disable_idle = TRUE; 544 545 return_VALUE (0); 546 } 547 548 static void 549 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 550 { 551 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 552 553 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 554 sc->cpu_prev_sleep = 1000000; 555 sc->cpu_cx_lowest = 0; 556 557 /* 558 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 559 * any, we'll revert to generic FADT/P_BLK Cx control method which will 560 * be handled by acpi_cpu_startup. We need to defer to after having 561 * probed all the cpus in the system before probing for generic Cx 562 * states as we may already have found cpus with valid _CST packages 563 */ 564 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 565 /* 566 * We were unable to find a _CST package for this cpu or there 567 * was an error parsing it. Switch back to generic mode. 568 */ 569 cpu_cx_generic = TRUE; 570 if (bootverbose) 571 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 572 } 573 574 /* 575 * TODO: _CSD Package should be checked here. 576 */ 577 } 578 579 static void 580 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 581 { 582 ACPI_GENERIC_ADDRESS gas; 583 struct acpi_cx *cx_ptr; 584 585 sc->cpu_cx_count = 0; 586 cx_ptr = sc->cpu_cx_states; 587 588 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 589 sc->cpu_prev_sleep = 1000000; 590 591 /* C1 has been required since just after ACPI 1.0 */ 592 cx_ptr->type = ACPI_STATE_C1; 593 cx_ptr->trans_lat = 0; 594 cx_ptr++; 595 sc->cpu_cx_count++; 596 597 /* 598 * The spec says P_BLK must be 6 bytes long. However, some systems 599 * use it to indicate a fractional set of features present so we 600 * take 5 as C2. Some may also have a value of 7 to indicate 601 * another C3 but most use _CST for this (as required) and having 602 * "only" C1-C3 is not a hardship. 603 */ 604 if (sc->cpu_p_blk_len < 5) 605 return; 606 607 /* Validate and allocate resources for C2 (P_LVL2). */ 608 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 609 gas.BitWidth = 8; 610 if (AcpiGbl_FADT.C2Latency <= 100) { 611 gas.Address = sc->cpu_p_blk + 4; 612 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, 613 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 614 if (cx_ptr->p_lvlx != NULL) { 615 sc->cpu_rid++; 616 cx_ptr->type = ACPI_STATE_C2; 617 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 618 cx_ptr++; 619 sc->cpu_cx_count++; 620 } 621 } 622 if (sc->cpu_p_blk_len < 6) 623 return; 624 625 /* Validate and allocate resources for C3 (P_LVL3). */ 626 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 627 gas.Address = sc->cpu_p_blk + 5; 628 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas, 629 &cx_ptr->p_lvlx, RF_SHAREABLE); 630 if (cx_ptr->p_lvlx != NULL) { 631 sc->cpu_rid++; 632 cx_ptr->type = ACPI_STATE_C3; 633 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 634 cx_ptr++; 635 sc->cpu_cx_count++; 636 } 637 } 638 } 639 640 /* 641 * Parse a _CST package and set up its Cx states. Since the _CST object 642 * can change dynamically, our notify handler may call this function 643 * to clean up and probe the new _CST package. 644 */ 645 static int 646 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 647 { 648 struct acpi_cx *cx_ptr; 649 ACPI_STATUS status; 650 ACPI_BUFFER buf; 651 ACPI_OBJECT *top; 652 ACPI_OBJECT *pkg; 653 uint32_t count; 654 int i; 655 656 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 657 658 buf.Pointer = NULL; 659 buf.Length = ACPI_ALLOCATE_BUFFER; 660 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 661 if (ACPI_FAILURE(status)) 662 return (ENXIO); 663 664 /* _CST is a package with a count and at least one Cx package. */ 665 top = (ACPI_OBJECT *)buf.Pointer; 666 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 667 device_printf(sc->cpu_dev, "invalid _CST package\n"); 668 AcpiOsFree(buf.Pointer); 669 return (ENXIO); 670 } 671 if (count != top->Package.Count - 1) { 672 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 673 count, top->Package.Count - 1); 674 count = top->Package.Count - 1; 675 } 676 if (count > MAX_CX_STATES) { 677 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 678 count = MAX_CX_STATES; 679 } 680 681 sc->cpu_non_c3 = 0; 682 sc->cpu_cx_count = 0; 683 cx_ptr = sc->cpu_cx_states; 684 685 /* 686 * C1 has been required since just after ACPI 1.0. 687 * Reserve the first slot for it. 688 */ 689 cx_ptr->type = ACPI_STATE_C0; 690 cx_ptr++; 691 sc->cpu_cx_count++; 692 693 /* Set up all valid states. */ 694 for (i = 0; i < count; i++) { 695 pkg = &top->Package.Elements[i + 1]; 696 if (!ACPI_PKG_VALID(pkg, 4) || 697 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 698 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 699 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 700 701 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 702 continue; 703 } 704 705 /* Validate the state to see if we should use it. */ 706 switch (cx_ptr->type) { 707 case ACPI_STATE_C1: 708 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 709 /* This is the first C1 state. Use the reserved slot. */ 710 sc->cpu_cx_states[0] = *cx_ptr; 711 } else { 712 sc->cpu_non_c3 = i; 713 cx_ptr++; 714 sc->cpu_cx_count++; 715 } 716 continue; 717 case ACPI_STATE_C2: 718 sc->cpu_non_c3 = i; 719 break; 720 case ACPI_STATE_C3: 721 default: 722 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 723 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 724 "acpi_cpu%d: C3[%d] not available.\n", 725 device_get_unit(sc->cpu_dev), i)); 726 continue; 727 } 728 break; 729 } 730 731 #ifdef notyet 732 /* Free up any previous register. */ 733 if (cx_ptr->p_lvlx != NULL) { 734 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx); 735 cx_ptr->p_lvlx = NULL; 736 } 737 #endif 738 739 /* Allocate the control register for C2 or C3. */ 740 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &sc->cpu_rid, 741 &cx_ptr->p_lvlx, RF_SHAREABLE); 742 if (cx_ptr->p_lvlx) { 743 sc->cpu_rid++; 744 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 745 "acpi_cpu%d: Got C%d - %d latency\n", 746 device_get_unit(sc->cpu_dev), cx_ptr->type, 747 cx_ptr->trans_lat)); 748 cx_ptr++; 749 sc->cpu_cx_count++; 750 } 751 } 752 AcpiOsFree(buf.Pointer); 753 754 /* If C1 state was not found, we need one now. */ 755 cx_ptr = sc->cpu_cx_states; 756 if (cx_ptr->type == ACPI_STATE_C0) { 757 cx_ptr->type = ACPI_STATE_C1; 758 cx_ptr->trans_lat = 0; 759 } 760 761 return (0); 762 } 763 764 /* 765 * Call this *after* all CPUs have been attached. 766 */ 767 static void 768 acpi_cpu_startup(void *arg) 769 { 770 struct acpi_cpu_softc *sc; 771 int i; 772 773 /* Get set of CPU devices */ 774 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 775 776 /* 777 * Setup any quirks that might necessary now that we have probed 778 * all the CPUs 779 */ 780 acpi_cpu_quirks(); 781 782 cpu_cx_count = 0; 783 if (cpu_cx_generic) { 784 /* 785 * We are using generic Cx mode, probe for available Cx states 786 * for all processors. 787 */ 788 for (i = 0; i < cpu_ndevices; i++) { 789 sc = device_get_softc(cpu_devices[i]); 790 acpi_cpu_generic_cx_probe(sc); 791 if (sc->cpu_cx_count > cpu_cx_count) 792 cpu_cx_count = sc->cpu_cx_count; 793 } 794 795 /* 796 * Find the highest Cx state common to all CPUs 797 * in the system, taking quirks into account. 798 */ 799 for (i = 0; i < cpu_ndevices; i++) { 800 sc = device_get_softc(cpu_devices[i]); 801 if (sc->cpu_cx_count < cpu_cx_count) 802 cpu_cx_count = sc->cpu_cx_count; 803 } 804 } else { 805 /* 806 * We are using _CST mode, remove C3 state if necessary. 807 * Update the largest Cx state supported in the global cpu_cx_count. 808 * It will be used in the global Cx sysctl handler. 809 * As we now know for sure that we will be using _CST mode 810 * install our notify handler. 811 */ 812 for (i = 0; i < cpu_ndevices; i++) { 813 sc = device_get_softc(cpu_devices[i]); 814 if (cpu_quirks & CPU_QUIRK_NO_C3) { 815 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 816 } 817 if (sc->cpu_cx_count > cpu_cx_count) 818 cpu_cx_count = sc->cpu_cx_count; 819 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 820 acpi_cpu_notify, sc); 821 } 822 } 823 824 /* Perform Cx final initialization. */ 825 for (i = 0; i < cpu_ndevices; i++) { 826 sc = device_get_softc(cpu_devices[i]); 827 acpi_cpu_startup_cx(sc); 828 } 829 830 /* Add a sysctl handler to handle global Cx lowest setting */ 831 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 832 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 833 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 834 "Global lowest Cx sleep state to use"); 835 836 /* Take over idling from cpu_idle_default(). */ 837 cpu_cx_lowest = 0; 838 cpu_disable_idle = FALSE; 839 cpu_idle_hook = acpi_cpu_idle; 840 } 841 842 static void 843 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 844 { 845 struct sbuf sb; 846 int i; 847 848 /* 849 * Set up the list of Cx states 850 */ 851 sc->cpu_non_c3 = 0; 852 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 853 SBUF_FIXEDLEN); 854 for (i = 0; i < sc->cpu_cx_count; i++) { 855 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat); 856 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) 857 sc->cpu_non_c3 = i; 858 else 859 cpu_can_deep_sleep = 1; 860 } 861 sbuf_trim(&sb); 862 sbuf_finish(&sb); 863 } 864 865 static void 866 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 867 { 868 acpi_cpu_cx_list(sc); 869 870 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 871 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 872 OID_AUTO, "cx_supported", CTLFLAG_RD, 873 sc->cpu_cx_supported, 0, 874 "Cx/microsecond values for supported Cx states"); 875 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 876 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 877 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 878 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 879 "lowest Cx sleep state to use"); 880 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 881 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 882 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 883 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 884 "percent usage for each Cx state"); 885 886 #ifdef notyet 887 /* Signal platform that we can handle _CST notification. */ 888 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 889 ACPI_LOCK(acpi); 890 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 891 ACPI_UNLOCK(acpi); 892 } 893 #endif 894 } 895 896 /* 897 * Idle the CPU in the lowest state possible. This function is called with 898 * interrupts disabled. Note that once it re-enables interrupts, a task 899 * switch can occur so do not access shared data (i.e. the softc) after 900 * interrupts are re-enabled. 901 */ 902 static void 903 acpi_cpu_idle() 904 { 905 struct acpi_cpu_softc *sc; 906 struct acpi_cx *cx_next; 907 uint32_t start_time, end_time; 908 int bm_active, cx_next_idx, i; 909 910 /* If disabled, return immediately. */ 911 if (cpu_disable_idle) { 912 ACPI_ENABLE_IRQS(); 913 return; 914 } 915 916 /* 917 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 918 * since there is no ACPI processor object for this CPU. This occurs 919 * for logical CPUs in the HTT case. 920 */ 921 sc = cpu_softc[PCPU_GET(cpuid)]; 922 if (sc == NULL) { 923 acpi_cpu_c1(); 924 return; 925 } 926 927 /* Find the lowest state that has small enough latency. */ 928 cx_next_idx = 0; 929 if (cpu_disable_deep_sleep) 930 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 931 else 932 i = sc->cpu_cx_lowest; 933 for (; i >= 0; i--) { 934 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) { 935 cx_next_idx = i; 936 break; 937 } 938 } 939 940 /* 941 * Check for bus master activity. If there was activity, clear 942 * the bit and use the lowest non-C3 state. Note that the USB 943 * driver polling for new devices keeps this bit set all the 944 * time if USB is loaded. 945 */ 946 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 947 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 948 if (bm_active != 0) { 949 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 950 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3); 951 } 952 } 953 954 /* Select the next state and update statistics. */ 955 cx_next = &sc->cpu_cx_states[cx_next_idx]; 956 sc->cpu_cx_stats[cx_next_idx]++; 957 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 958 959 /* 960 * Execute HLT (or equivalent) and wait for an interrupt. We can't 961 * precisely calculate the time spent in C1 since the place we wake up 962 * is an ISR. Assume we slept no more then half of quantum, unless 963 * we are called inside critical section, delaying context switch. 964 */ 965 if (cx_next->type == ACPI_STATE_C1) { 966 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 967 acpi_cpu_c1(); 968 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 969 end_time = PM_USEC(acpi_TimerDelta(end_time, start_time)); 970 if (curthread->td_critnest == 0) 971 end_time = min(end_time, 500000 / hz); 972 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 973 return; 974 } 975 976 /* 977 * For C3, disable bus master arbitration and enable bus master wake 978 * if BM control is available, otherwise flush the CPU cache. 979 */ 980 if (cx_next->type == ACPI_STATE_C3) { 981 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 982 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 983 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 984 } else 985 ACPI_FLUSH_CPU_CACHE(); 986 } 987 988 /* 989 * Read from P_LVLx to enter C2(+), checking time spent asleep. 990 * Use the ACPI timer for measuring sleep time. Since we need to 991 * get the time very close to the CPU start/stop clock logic, this 992 * is the only reliable time source. 993 */ 994 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 995 CPU_GET_REG(cx_next->p_lvlx, 1); 996 997 /* 998 * Read the end time twice. Since it may take an arbitrary time 999 * to enter the idle state, the first read may be executed before 1000 * the processor has stopped. Doing it again provides enough 1001 * margin that we are certain to have a correct value. 1002 */ 1003 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1004 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1005 1006 /* Enable bus master arbitration and disable bus master wakeup. */ 1007 if (cx_next->type == ACPI_STATE_C3 && 1008 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1009 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1010 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1011 } 1012 ACPI_ENABLE_IRQS(); 1013 1014 /* Find the actual time asleep in microseconds. */ 1015 end_time = acpi_TimerDelta(end_time, start_time); 1016 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1017 } 1018 1019 /* 1020 * Re-evaluate the _CST object when we are notified that it changed. 1021 * 1022 * XXX Re-evaluation disabled until locking is done. 1023 */ 1024 static void 1025 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1026 { 1027 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1028 struct acpi_cpu_softc *isc; 1029 int i; 1030 1031 if (notify != ACPI_NOTIFY_CX_STATES) 1032 return; 1033 1034 /* Update the list of Cx states. */ 1035 acpi_cpu_cx_cst(sc); 1036 acpi_cpu_cx_list(sc); 1037 1038 /* Update the new lowest useable Cx state for all CPUs. */ 1039 ACPI_SERIAL_BEGIN(cpu); 1040 cpu_cx_count = 0; 1041 for (i = 0; i < cpu_ndevices; i++) { 1042 isc = device_get_softc(cpu_devices[i]); 1043 if (isc->cpu_cx_count > cpu_cx_count) 1044 cpu_cx_count = isc->cpu_cx_count; 1045 } 1046 if (sc->cpu_cx_lowest < cpu_cx_lowest) 1047 acpi_cpu_set_cx_lowest(sc, min(cpu_cx_lowest, sc->cpu_cx_count - 1)); 1048 ACPI_SERIAL_END(cpu); 1049 } 1050 1051 static int 1052 acpi_cpu_quirks(void) 1053 { 1054 device_t acpi_dev; 1055 uint32_t val; 1056 1057 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1058 1059 /* 1060 * Bus mastering arbitration control is needed to keep caches coherent 1061 * while sleeping in C3. If it's not present but a working flush cache 1062 * instruction is present, flush the caches before entering C3 instead. 1063 * Otherwise, just disable C3 completely. 1064 */ 1065 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1066 AcpiGbl_FADT.Pm2ControlLength == 0) { 1067 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1068 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1069 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1070 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1071 "acpi_cpu: no BM control, using flush cache method\n")); 1072 } else { 1073 cpu_quirks |= CPU_QUIRK_NO_C3; 1074 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1075 "acpi_cpu: no BM control, C3 not available\n")); 1076 } 1077 } 1078 1079 /* 1080 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1081 * the expensive flush cache instruction. 1082 */ 1083 if (cpu_cx_generic && mp_ncpus > 1) { 1084 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1085 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1086 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1087 } 1088 1089 /* Look for various quirks of the PIIX4 part. */ 1090 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1091 if (acpi_dev != NULL) { 1092 switch (pci_get_revid(acpi_dev)) { 1093 /* 1094 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1095 * do not report the BMIDE status to the BM status register and 1096 * others have a livelock bug if Type-F DMA is enabled. Linux 1097 * works around the BMIDE bug by reading the BM status directly 1098 * but we take the simpler approach of disabling C3 for these 1099 * parts. 1100 * 1101 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1102 * Livelock") from the January 2002 PIIX4 specification update. 1103 * Applies to all PIIX4 models. 1104 * 1105 * Also, make sure that all interrupts cause a "Stop Break" 1106 * event to exit from C2 state. 1107 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1108 * should be set to zero, otherwise it causes C2 to short-sleep. 1109 * PIIX4 doesn't properly support C3 and bus master activity 1110 * need not break out of C2. 1111 */ 1112 case PCI_REVISION_A_STEP: 1113 case PCI_REVISION_B_STEP: 1114 case PCI_REVISION_4E: 1115 case PCI_REVISION_4M: 1116 cpu_quirks |= CPU_QUIRK_NO_C3; 1117 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1118 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1119 1120 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1121 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1122 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1123 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1124 val |= PIIX4_STOP_BREAK_MASK; 1125 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1126 } 1127 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1128 if (val) { 1129 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1130 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1131 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1132 } 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 1139 return (0); 1140 } 1141 1142 static int 1143 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1144 { 1145 struct acpi_cpu_softc *sc; 1146 struct sbuf sb; 1147 char buf[128]; 1148 int i; 1149 uintmax_t fract, sum, whole; 1150 1151 sc = (struct acpi_cpu_softc *) arg1; 1152 sum = 0; 1153 for (i = 0; i < sc->cpu_cx_count; i++) 1154 sum += sc->cpu_cx_stats[i]; 1155 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1156 for (i = 0; i < sc->cpu_cx_count; i++) { 1157 if (sum > 0) { 1158 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1159 fract = (whole % sum) * 100; 1160 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1161 (u_int)(fract / sum)); 1162 } else 1163 sbuf_printf(&sb, "0.00%% "); 1164 } 1165 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1166 sbuf_trim(&sb); 1167 sbuf_finish(&sb); 1168 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1169 sbuf_delete(&sb); 1170 1171 return (0); 1172 } 1173 1174 static int 1175 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val) 1176 { 1177 int i; 1178 1179 ACPI_SERIAL_ASSERT(cpu); 1180 sc->cpu_cx_lowest = val; 1181 1182 /* If not disabling, cache the new lowest non-C3 state. */ 1183 sc->cpu_non_c3 = 0; 1184 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1185 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1186 sc->cpu_non_c3 = i; 1187 break; 1188 } 1189 } 1190 1191 /* Reset the statistics counters. */ 1192 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1193 return (0); 1194 } 1195 1196 static int 1197 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1198 { 1199 struct acpi_cpu_softc *sc; 1200 char state[8]; 1201 int val, error; 1202 1203 sc = (struct acpi_cpu_softc *) arg1; 1204 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1); 1205 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1206 if (error != 0 || req->newptr == NULL) 1207 return (error); 1208 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1209 return (EINVAL); 1210 val = (int) strtol(state + 1, NULL, 10) - 1; 1211 if (val < 0 || val > sc->cpu_cx_count - 1) 1212 return (EINVAL); 1213 1214 ACPI_SERIAL_BEGIN(cpu); 1215 acpi_cpu_set_cx_lowest(sc, val); 1216 ACPI_SERIAL_END(cpu); 1217 1218 return (0); 1219 } 1220 1221 static int 1222 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1223 { 1224 struct acpi_cpu_softc *sc; 1225 char state[8]; 1226 int val, error, i; 1227 1228 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1229 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1230 if (error != 0 || req->newptr == NULL) 1231 return (error); 1232 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1233 return (EINVAL); 1234 val = (int) strtol(state + 1, NULL, 10) - 1; 1235 if (val < 0 || val > cpu_cx_count - 1) 1236 return (EINVAL); 1237 cpu_cx_lowest = val; 1238 1239 /* Update the new lowest useable Cx state for all CPUs. */ 1240 ACPI_SERIAL_BEGIN(cpu); 1241 for (i = 0; i < cpu_ndevices; i++) { 1242 sc = device_get_softc(cpu_devices[i]); 1243 acpi_cpu_set_cx_lowest(sc, min(val, sc->cpu_cx_count - 1)); 1244 } 1245 ACPI_SERIAL_END(cpu); 1246 1247 return (0); 1248 } 1249