1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 118 119 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 120 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 121 122 #define PCI_VENDOR_INTEL 0x8086 123 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 124 #define PCI_REVISION_A_STEP 0 125 #define PCI_REVISION_B_STEP 1 126 #define PCI_REVISION_4E 2 127 #define PCI_REVISION_4M 3 128 #define PIIX4_DEVACTB_REG 0x58 129 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 130 #define PIIX4_BRLD_EN_IRQ (1<<1) 131 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 132 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 133 #define PIIX4_PCNTRL_BST_EN (1<<10) 134 135 #define CST_FFH_VENDOR_INTEL 1 136 #define CST_FFH_INTEL_CL_C1IO 1 137 #define CST_FFH_INTEL_CL_MWAIT 2 138 #define CST_FFH_MWAIT_HW_COORD 0x0001 139 #define CST_FFH_MWAIT_BM_AVOID 0x0002 140 141 #define CPUDEV_DEVICE_ID "ACPI0007" 142 143 /* Knob to disable acpi_cpu devices */ 144 bool acpi_cpu_disabled = false; 145 146 /* Platform hardware resource information. */ 147 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 148 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 149 static int cpu_quirks; /* Indicate any hardware bugs. */ 150 151 /* Values for sysctl. */ 152 static struct sysctl_ctx_list cpu_sysctl_ctx; 153 static struct sysctl_oid *cpu_sysctl_tree; 154 static int cpu_cx_generic; 155 static int cpu_cx_lowest_lim; 156 157 static struct acpi_cpu_softc **cpu_softc; 158 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 159 160 static int acpi_cpu_probe(device_t dev); 161 static int acpi_cpu_attach(device_t dev); 162 static int acpi_cpu_suspend(device_t dev); 163 static int acpi_cpu_resume(device_t dev); 164 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, 165 u_int *cpu_id); 166 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 167 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 168 int unit); 169 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 170 uintptr_t *result); 171 static int acpi_cpu_shutdown(device_t dev); 172 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 173 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 174 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 175 static void acpi_cpu_startup(void *arg); 176 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 177 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 178 #if defined(__i386__) || defined(__amd64__) 179 static void acpi_cpu_idle(sbintime_t sbt); 180 #endif 181 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 182 static void acpi_cpu_quirks(void); 183 static void acpi_cpu_quirks_piix4(void); 184 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 185 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 186 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 187 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 188 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 189 #if defined(__i386__) || defined(__amd64__) 190 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 191 #endif 192 193 static device_method_t acpi_cpu_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, acpi_cpu_probe), 196 DEVMETHOD(device_attach, acpi_cpu_attach), 197 DEVMETHOD(device_detach, bus_generic_detach), 198 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 199 DEVMETHOD(device_suspend, acpi_cpu_suspend), 200 DEVMETHOD(device_resume, acpi_cpu_resume), 201 202 /* Bus interface */ 203 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 204 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 205 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 206 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 207 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 208 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 209 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 210 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 211 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 212 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 213 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 214 215 DEVMETHOD_END 216 }; 217 218 static driver_t acpi_cpu_driver = { 219 "cpu", 220 acpi_cpu_methods, 221 sizeof(struct acpi_cpu_softc), 222 }; 223 224 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, 0, 0); 225 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 226 227 static int 228 acpi_cpu_probe(device_t dev) 229 { 230 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL }; 231 int acpi_id, cpu_id; 232 ACPI_BUFFER buf; 233 ACPI_HANDLE handle; 234 ACPI_OBJECT *obj; 235 ACPI_STATUS status; 236 ACPI_OBJECT_TYPE type; 237 238 if (acpi_disabled("cpu") || acpi_cpu_disabled) 239 return (ENXIO); 240 type = acpi_get_type(dev); 241 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE) 242 return (ENXIO); 243 if (type == ACPI_TYPE_DEVICE && 244 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0) 245 return (ENXIO); 246 247 handle = acpi_get_handle(dev); 248 if (cpu_softc == NULL) 249 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 250 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 251 252 if (type == ACPI_TYPE_PROCESSOR) { 253 /* Get our Processor object. */ 254 buf.Pointer = NULL; 255 buf.Length = ACPI_ALLOCATE_BUFFER; 256 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 257 if (ACPI_FAILURE(status)) { 258 device_printf(dev, "probe failed to get Processor obj - %s\n", 259 AcpiFormatException(status)); 260 return (ENXIO); 261 } 262 obj = (ACPI_OBJECT *)buf.Pointer; 263 if (obj->Type != ACPI_TYPE_PROCESSOR) { 264 device_printf(dev, "Processor object has bad type %d\n", 265 obj->Type); 266 AcpiOsFree(obj); 267 return (ENXIO); 268 } 269 270 /* 271 * Find the processor associated with our unit. We could use the 272 * ProcId as a key, however, some boxes do not have the same values 273 * in their Processor object as the ProcId values in the MADT. 274 */ 275 acpi_id = obj->Processor.ProcId; 276 AcpiOsFree(obj); 277 } else { 278 status = acpi_GetInteger(handle, "_UID", &acpi_id); 279 if (ACPI_FAILURE(status)) { 280 device_printf(dev, "Device object has bad value - %s\n", 281 AcpiFormatException(status)); 282 return (ENXIO); 283 } 284 } 285 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) { 286 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255)) 287 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 288 acpi_name(acpi_get_handle(dev)), acpi_id); 289 return (ENXIO); 290 } 291 292 if (device_set_unit(dev, cpu_id) != 0) 293 return (ENXIO); 294 295 device_set_desc(dev, "ACPI CPU"); 296 297 if (!bootverbose && device_get_unit(dev) != 0) { 298 device_quiet(dev); 299 device_quiet_children(dev); 300 } 301 302 return (BUS_PROBE_DEFAULT); 303 } 304 305 static int 306 acpi_cpu_attach(device_t dev) 307 { 308 ACPI_BUFFER buf; 309 ACPI_OBJECT arg, *obj; 310 ACPI_OBJECT_LIST arglist; 311 struct pcpu *pcpu_data; 312 struct acpi_cpu_softc *sc; 313 struct acpi_softc *acpi_sc; 314 ACPI_STATUS status; 315 u_int features; 316 int cpu_id, drv_count, i; 317 driver_t **drivers; 318 uint32_t cap_set[3]; 319 320 /* UUID needed by _OSC evaluation */ 321 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 322 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 323 0x58, 0x71, 0x39, 0x53 }; 324 325 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 326 327 sc = device_get_softc(dev); 328 sc->cpu_dev = dev; 329 sc->cpu_handle = acpi_get_handle(dev); 330 cpu_id = device_get_unit(dev); 331 cpu_softc[cpu_id] = sc; 332 pcpu_data = pcpu_find(cpu_id); 333 pcpu_data->pc_device = dev; 334 sc->cpu_pcpu = pcpu_data; 335 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 336 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 337 338 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) { 339 buf.Pointer = NULL; 340 buf.Length = ACPI_ALLOCATE_BUFFER; 341 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 342 if (ACPI_FAILURE(status)) { 343 device_printf(dev, "attach failed to get Processor obj - %s\n", 344 AcpiFormatException(status)); 345 return (ENXIO); 346 } 347 obj = (ACPI_OBJECT *)buf.Pointer; 348 sc->cpu_p_blk = obj->Processor.PblkAddress; 349 sc->cpu_p_blk_len = obj->Processor.PblkLength; 350 sc->cpu_acpi_id = obj->Processor.ProcId; 351 AcpiOsFree(obj); 352 } else { 353 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE, 354 ("Unexpected ACPI object")); 355 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id); 356 if (ACPI_FAILURE(status)) { 357 device_printf(dev, "Device object has bad value - %s\n", 358 AcpiFormatException(status)); 359 return (ENXIO); 360 } 361 sc->cpu_p_blk = 0; 362 sc->cpu_p_blk_len = 0; 363 } 364 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 365 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 366 367 /* 368 * If this is the first cpu we attach, create and initialize the generic 369 * resources that will be used by all acpi cpu devices. 370 */ 371 if (device_get_unit(dev) == 0) { 372 /* Assume we won't be using generic Cx mode by default */ 373 cpu_cx_generic = FALSE; 374 375 /* Install hw.acpi.cpu sysctl tree */ 376 acpi_sc = acpi_device_get_parent_softc(dev); 377 sysctl_ctx_init(&cpu_sysctl_ctx); 378 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 379 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 380 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children"); 381 } 382 383 /* 384 * Before calling any CPU methods, collect child driver feature hints 385 * and notify ACPI of them. We support unified SMP power control 386 * so advertise this ourselves. Note this is not the same as independent 387 * SMP control where each CPU can have different settings. 388 */ 389 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 390 ACPI_CAP_C1_IO_HALT; 391 392 #if defined(__i386__) || defined(__amd64__) 393 /* 394 * Ask for MWAIT modes if not disabled and interrupts work 395 * reasonable with MWAIT. 396 */ 397 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 398 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 399 #endif 400 401 if (devclass_get_drivers(device_get_devclass(dev), &drivers, 402 &drv_count) == 0) { 403 for (i = 0; i < drv_count; i++) { 404 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 405 sc->cpu_features |= features; 406 } 407 free(drivers, M_TEMP); 408 } 409 410 /* 411 * CPU capabilities are specified in 412 * Intel Processor Vendor-Specific ACPI Interface Specification. 413 */ 414 if (sc->cpu_features) { 415 cap_set[1] = sc->cpu_features; 416 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 417 cap_set, false); 418 if (ACPI_SUCCESS(status)) { 419 if (cap_set[0] != 0) 420 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 421 } 422 else { 423 arglist.Pointer = &arg; 424 arglist.Count = 1; 425 arg.Type = ACPI_TYPE_BUFFER; 426 arg.Buffer.Length = sizeof(cap_set); 427 arg.Buffer.Pointer = (uint8_t *)cap_set; 428 cap_set[0] = 1; /* revision */ 429 cap_set[1] = 1; /* number of capabilities integers */ 430 cap_set[2] = sc->cpu_features; 431 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 432 } 433 } 434 435 /* Probe for Cx state support. */ 436 acpi_cpu_cx_probe(sc); 437 438 return (0); 439 } 440 441 static void 442 acpi_cpu_postattach(void *unused __unused) 443 { 444 struct acpi_cpu_softc *sc; 445 int attached = 0, i; 446 447 if (cpu_softc == NULL) 448 return; 449 450 bus_topo_lock(); 451 CPU_FOREACH(i) { 452 if ((sc = cpu_softc[i]) != NULL) 453 bus_generic_probe(sc->cpu_dev); 454 } 455 CPU_FOREACH(i) { 456 if ((sc = cpu_softc[i]) != NULL) { 457 bus_generic_attach(sc->cpu_dev); 458 attached = 1; 459 } 460 } 461 bus_topo_unlock(); 462 463 if (attached) { 464 #ifdef EARLY_AP_STARTUP 465 acpi_cpu_startup(NULL); 466 #else 467 /* Queue post cpu-probing task handler */ 468 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 469 #endif 470 } 471 } 472 473 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 474 acpi_cpu_postattach, NULL); 475 476 static void 477 disable_idle(struct acpi_cpu_softc *sc) 478 { 479 cpuset_t cpuset; 480 481 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 482 sc->cpu_disable_idle = TRUE; 483 484 /* 485 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 486 * Note that this code depends on the fact that the rendezvous IPI 487 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 488 * is called and executed in such a context with interrupts being re-enabled 489 * right before return. 490 */ 491 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 492 smp_no_rendezvous_barrier, NULL); 493 } 494 495 static void 496 enable_idle(struct acpi_cpu_softc *sc) 497 { 498 499 sc->cpu_disable_idle = FALSE; 500 } 501 502 #if defined(__i386__) || defined(__amd64__) 503 static int 504 is_idle_disabled(struct acpi_cpu_softc *sc) 505 { 506 507 return (sc->cpu_disable_idle); 508 } 509 #endif 510 511 /* 512 * Disable any entry to the idle function during suspend and re-enable it 513 * during resume. 514 */ 515 static int 516 acpi_cpu_suspend(device_t dev) 517 { 518 int error; 519 520 error = bus_generic_suspend(dev); 521 if (error) 522 return (error); 523 disable_idle(device_get_softc(dev)); 524 return (0); 525 } 526 527 static int 528 acpi_cpu_resume(device_t dev) 529 { 530 531 enable_idle(device_get_softc(dev)); 532 return (bus_generic_resume(dev)); 533 } 534 535 /* 536 * Find the processor associated with a given ACPI ID. 537 */ 538 static int 539 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id) 540 { 541 struct pcpu *pc; 542 u_int i; 543 544 CPU_FOREACH(i) { 545 pc = pcpu_find(i); 546 if (pc->pc_acpi_id == acpi_id) { 547 *cpu_id = pc->pc_cpuid; 548 return (0); 549 } 550 } 551 552 /* 553 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 554 * UP box) use the ACPI ID from the first processor we find. 555 */ 556 if (mp_ncpus == 1) { 557 pc = pcpu_find(0); 558 if (pc->pc_acpi_id == 0xffffffff) 559 pc->pc_acpi_id = acpi_id; 560 *cpu_id = 0; 561 return (0); 562 } 563 564 return (ESRCH); 565 } 566 567 static struct resource_list * 568 acpi_cpu_get_rlist(device_t dev, device_t child) 569 { 570 struct acpi_cpu_device *ad; 571 572 ad = device_get_ivars(child); 573 if (ad == NULL) 574 return (NULL); 575 return (&ad->ad_rl); 576 } 577 578 static device_t 579 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 580 { 581 struct acpi_cpu_device *ad; 582 device_t child; 583 584 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 585 return (NULL); 586 587 resource_list_init(&ad->ad_rl); 588 589 child = device_add_child_ordered(dev, order, name, unit); 590 if (child != NULL) 591 device_set_ivars(child, ad); 592 else 593 free(ad, M_TEMP); 594 return (child); 595 } 596 597 static int 598 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 599 { 600 struct acpi_cpu_softc *sc; 601 602 sc = device_get_softc(dev); 603 switch (index) { 604 case ACPI_IVAR_HANDLE: 605 *result = (uintptr_t)sc->cpu_handle; 606 break; 607 case CPU_IVAR_PCPU: 608 *result = (uintptr_t)sc->cpu_pcpu; 609 break; 610 #if defined(__amd64__) || defined(__i386__) 611 case CPU_IVAR_NOMINAL_MHZ: 612 if (tsc_is_invariant) { 613 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 614 break; 615 } 616 /* FALLTHROUGH */ 617 #endif 618 default: 619 return (ENOENT); 620 } 621 return (0); 622 } 623 624 static int 625 acpi_cpu_shutdown(device_t dev) 626 { 627 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 628 629 /* Allow children to shutdown first. */ 630 bus_generic_shutdown(dev); 631 632 /* 633 * Disable any entry to the idle function. 634 */ 635 disable_idle(device_get_softc(dev)); 636 637 /* 638 * CPU devices are not truly detached and remain referenced, 639 * so their resources are not freed. 640 */ 641 642 return_VALUE (0); 643 } 644 645 static void 646 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 647 { 648 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 649 650 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 651 sc->cpu_prev_sleep = 1000000; 652 sc->cpu_cx_lowest = 0; 653 sc->cpu_cx_lowest_lim = 0; 654 655 /* 656 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 657 * any, we'll revert to generic FADT/P_BLK Cx control method which will 658 * be handled by acpi_cpu_startup. We need to defer to after having 659 * probed all the cpus in the system before probing for generic Cx 660 * states as we may already have found cpus with valid _CST packages 661 */ 662 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 663 /* 664 * We were unable to find a _CST package for this cpu or there 665 * was an error parsing it. Switch back to generic mode. 666 */ 667 cpu_cx_generic = TRUE; 668 if (bootverbose) 669 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 670 } 671 672 /* 673 * TODO: _CSD Package should be checked here. 674 */ 675 } 676 677 static void 678 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 679 { 680 ACPI_GENERIC_ADDRESS gas; 681 struct acpi_cx *cx_ptr; 682 683 sc->cpu_cx_count = 0; 684 cx_ptr = sc->cpu_cx_states; 685 686 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 687 sc->cpu_prev_sleep = 1000000; 688 689 /* C1 has been required since just after ACPI 1.0 */ 690 cx_ptr->type = ACPI_STATE_C1; 691 cx_ptr->trans_lat = 0; 692 cx_ptr++; 693 sc->cpu_non_c2 = sc->cpu_cx_count; 694 sc->cpu_non_c3 = sc->cpu_cx_count; 695 sc->cpu_cx_count++; 696 697 /* 698 * The spec says P_BLK must be 6 bytes long. However, some systems 699 * use it to indicate a fractional set of features present so we 700 * take 5 as C2. Some may also have a value of 7 to indicate 701 * another C3 but most use _CST for this (as required) and having 702 * "only" C1-C3 is not a hardship. 703 */ 704 if (sc->cpu_p_blk_len < 5) 705 return; 706 707 /* Validate and allocate resources for C2 (P_LVL2). */ 708 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 709 gas.BitWidth = 8; 710 if (AcpiGbl_FADT.C2Latency <= 100) { 711 gas.Address = sc->cpu_p_blk + 4; 712 cx_ptr->res_rid = 0; 713 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 714 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 715 if (cx_ptr->p_lvlx != NULL) { 716 cx_ptr->type = ACPI_STATE_C2; 717 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 718 cx_ptr++; 719 sc->cpu_non_c3 = sc->cpu_cx_count; 720 sc->cpu_cx_count++; 721 } 722 } 723 if (sc->cpu_p_blk_len < 6) 724 return; 725 726 /* Validate and allocate resources for C3 (P_LVL3). */ 727 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 728 gas.Address = sc->cpu_p_blk + 5; 729 cx_ptr->res_rid = 1; 730 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 731 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 732 if (cx_ptr->p_lvlx != NULL) { 733 cx_ptr->type = ACPI_STATE_C3; 734 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 735 cx_ptr++; 736 sc->cpu_cx_count++; 737 } 738 } 739 } 740 741 #if defined(__i386__) || defined(__amd64__) 742 static void 743 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 744 { 745 746 cx_ptr->do_mwait = true; 747 cx_ptr->mwait_hint = address & 0xffffffff; 748 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 749 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 750 } 751 #endif 752 753 static void 754 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 755 { 756 757 if (cx_ptr->p_lvlx == NULL) 758 return; 759 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 760 cx_ptr->p_lvlx); 761 cx_ptr->p_lvlx = NULL; 762 } 763 764 /* 765 * Parse a _CST package and set up its Cx states. Since the _CST object 766 * can change dynamically, our notify handler may call this function 767 * to clean up and probe the new _CST package. 768 */ 769 static int 770 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 771 { 772 struct acpi_cx *cx_ptr; 773 ACPI_STATUS status; 774 ACPI_BUFFER buf; 775 ACPI_OBJECT *top; 776 ACPI_OBJECT *pkg; 777 uint32_t count; 778 int i; 779 #if defined(__i386__) || defined(__amd64__) 780 uint64_t address; 781 int vendor, class, accsize; 782 #endif 783 784 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 785 786 buf.Pointer = NULL; 787 buf.Length = ACPI_ALLOCATE_BUFFER; 788 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 789 if (ACPI_FAILURE(status)) 790 return (ENXIO); 791 792 /* _CST is a package with a count and at least one Cx package. */ 793 top = (ACPI_OBJECT *)buf.Pointer; 794 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 795 device_printf(sc->cpu_dev, "invalid _CST package\n"); 796 AcpiOsFree(buf.Pointer); 797 return (ENXIO); 798 } 799 if (count != top->Package.Count - 1) { 800 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 801 count, top->Package.Count - 1); 802 count = top->Package.Count - 1; 803 } 804 if (count > MAX_CX_STATES) { 805 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 806 count = MAX_CX_STATES; 807 } 808 809 sc->cpu_non_c2 = 0; 810 sc->cpu_non_c3 = 0; 811 sc->cpu_cx_count = 0; 812 cx_ptr = sc->cpu_cx_states; 813 814 /* 815 * C1 has been required since just after ACPI 1.0. 816 * Reserve the first slot for it. 817 */ 818 cx_ptr->type = ACPI_STATE_C0; 819 cx_ptr++; 820 sc->cpu_cx_count++; 821 822 /* Set up all valid states. */ 823 for (i = 0; i < count; i++) { 824 pkg = &top->Package.Elements[i + 1]; 825 if (!ACPI_PKG_VALID(pkg, 4) || 826 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 827 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 828 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 829 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 830 continue; 831 } 832 833 /* Validate the state to see if we should use it. */ 834 switch (cx_ptr->type) { 835 case ACPI_STATE_C1: 836 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 837 #if defined(__i386__) || defined(__amd64__) 838 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 839 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 840 if (class == CST_FFH_INTEL_CL_C1IO) { 841 /* C1 I/O then Halt */ 842 cx_ptr->res_rid = sc->cpu_cx_count; 843 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 844 cx_ptr->res_rid, address, 1); 845 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 846 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 847 RF_SHAREABLE); 848 if (cx_ptr->p_lvlx == NULL) { 849 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 850 cx_ptr->res_rid); 851 device_printf(sc->cpu_dev, 852 "C1 I/O failed to allocate port %d, " 853 "degrading to C1 Halt", (int)address); 854 } 855 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 856 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 857 } 858 } 859 #endif 860 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 861 /* This is the first C1 state. Use the reserved slot. */ 862 sc->cpu_cx_states[0] = *cx_ptr; 863 } else { 864 sc->cpu_non_c2 = sc->cpu_cx_count; 865 sc->cpu_non_c3 = sc->cpu_cx_count; 866 cx_ptr++; 867 sc->cpu_cx_count++; 868 } 869 continue; 870 case ACPI_STATE_C2: 871 sc->cpu_non_c3 = sc->cpu_cx_count; 872 break; 873 case ACPI_STATE_C3: 874 default: 875 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 876 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 877 "acpi_cpu%d: C3[%d] not available.\n", 878 device_get_unit(sc->cpu_dev), i)); 879 continue; 880 } 881 break; 882 } 883 884 /* Free up any previous register. */ 885 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 886 887 /* Allocate the control register for C2 or C3. */ 888 #if defined(__i386__) || defined(__amd64__) 889 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 890 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 891 class == CST_FFH_INTEL_CL_MWAIT) { 892 /* Native C State Instruction use (mwait) */ 893 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 894 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 895 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 896 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 897 cx_ptr++; 898 sc->cpu_cx_count++; 899 } else 900 #endif 901 { 902 cx_ptr->res_rid = sc->cpu_cx_count; 903 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 904 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 905 if (cx_ptr->p_lvlx) { 906 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 907 "acpi_cpu%d: Got C%d - %d latency\n", 908 device_get_unit(sc->cpu_dev), cx_ptr->type, 909 cx_ptr->trans_lat)); 910 cx_ptr++; 911 sc->cpu_cx_count++; 912 } 913 } 914 } 915 AcpiOsFree(buf.Pointer); 916 917 /* If C1 state was not found, we need one now. */ 918 cx_ptr = sc->cpu_cx_states; 919 if (cx_ptr->type == ACPI_STATE_C0) { 920 cx_ptr->type = ACPI_STATE_C1; 921 cx_ptr->trans_lat = 0; 922 } 923 924 return (0); 925 } 926 927 /* 928 * Call this *after* all CPUs have been attached. 929 */ 930 static void 931 acpi_cpu_startup(void *arg) 932 { 933 struct acpi_cpu_softc *sc; 934 int i; 935 936 /* 937 * Setup any quirks that might necessary now that we have probed 938 * all the CPUs 939 */ 940 acpi_cpu_quirks(); 941 942 if (cpu_cx_generic) { 943 /* 944 * We are using generic Cx mode, probe for available Cx states 945 * for all processors. 946 */ 947 CPU_FOREACH(i) { 948 if ((sc = cpu_softc[i]) != NULL) 949 acpi_cpu_generic_cx_probe(sc); 950 } 951 } else { 952 /* 953 * We are using _CST mode, remove C3 state if necessary. 954 * As we now know for sure that we will be using _CST mode 955 * install our notify handler. 956 */ 957 CPU_FOREACH(i) { 958 if ((sc = cpu_softc[i]) == NULL) 959 continue; 960 if (cpu_quirks & CPU_QUIRK_NO_C3) { 961 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 962 } 963 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 964 acpi_cpu_notify, sc); 965 } 966 } 967 968 /* Perform Cx final initialization. */ 969 CPU_FOREACH(i) { 970 if ((sc = cpu_softc[i]) != NULL) 971 acpi_cpu_startup_cx(sc); 972 } 973 974 /* Add a sysctl handler to handle global Cx lowest setting */ 975 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 976 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 977 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 978 "Global lowest Cx sleep state to use"); 979 980 /* Take over idling from cpu_idle_default(). */ 981 cpu_cx_lowest_lim = 0; 982 CPU_FOREACH(i) { 983 if ((sc = cpu_softc[i]) != NULL) 984 enable_idle(sc); 985 } 986 #if defined(__i386__) || defined(__amd64__) 987 cpu_idle_hook = acpi_cpu_idle; 988 #endif 989 } 990 991 static void 992 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 993 { 994 struct sbuf sb; 995 int i; 996 997 /* 998 * Set up the list of Cx states 999 */ 1000 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1001 SBUF_FIXEDLEN); 1002 for (i = 0; i < sc->cpu_cx_count; i++) 1003 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1004 sc->cpu_cx_states[i].trans_lat); 1005 sbuf_trim(&sb); 1006 sbuf_finish(&sb); 1007 } 1008 1009 static void 1010 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1011 { 1012 acpi_cpu_cx_list(sc); 1013 1014 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1015 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1016 OID_AUTO, "cx_supported", CTLFLAG_RD, 1017 sc->cpu_cx_supported, 0, 1018 "Cx/microsecond values for supported Cx states"); 1019 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1020 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1021 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1022 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1023 "lowest Cx sleep state to use"); 1024 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1025 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1026 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1027 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1028 "percent usage for each Cx state"); 1029 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1030 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1031 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1032 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1033 "Cx sleep state counters"); 1034 #if defined(__i386__) || defined(__amd64__) 1035 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1036 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1037 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1038 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods"); 1039 #endif 1040 1041 /* Signal platform that we can handle _CST notification. */ 1042 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1043 ACPI_LOCK(acpi); 1044 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1045 ACPI_UNLOCK(acpi); 1046 } 1047 } 1048 1049 #if defined(__i386__) || defined(__amd64__) 1050 /* 1051 * Idle the CPU in the lowest state possible. This function is called with 1052 * interrupts disabled. Note that once it re-enables interrupts, a task 1053 * switch can occur so do not access shared data (i.e. the softc) after 1054 * interrupts are re-enabled. 1055 */ 1056 static void 1057 acpi_cpu_idle(sbintime_t sbt) 1058 { 1059 struct acpi_cpu_softc *sc; 1060 struct acpi_cx *cx_next; 1061 uint64_t start_ticks, end_ticks; 1062 uint32_t start_time, end_time; 1063 ACPI_STATUS status; 1064 int bm_active, cx_next_idx, i, us; 1065 1066 /* 1067 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1068 * since there is no ACPI processor object for this CPU. This occurs 1069 * for logical CPUs in the HTT case. 1070 */ 1071 sc = cpu_softc[PCPU_GET(cpuid)]; 1072 if (sc == NULL) { 1073 acpi_cpu_c1(); 1074 return; 1075 } 1076 1077 /* If disabled, take the safe path. */ 1078 if (is_idle_disabled(sc)) { 1079 acpi_cpu_c1(); 1080 return; 1081 } 1082 1083 /* Find the lowest state that has small enough latency. */ 1084 us = sc->cpu_prev_sleep; 1085 if (sbt >= 0 && us > (sbt >> 12)) 1086 us = (sbt >> 12); 1087 cx_next_idx = 0; 1088 if (cpu_disable_c2_sleep) 1089 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1090 else if (cpu_disable_c3_sleep) 1091 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1092 else 1093 i = sc->cpu_cx_lowest; 1094 for (; i >= 0; i--) { 1095 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1096 cx_next_idx = i; 1097 break; 1098 } 1099 } 1100 1101 /* 1102 * Check for bus master activity. If there was activity, clear 1103 * the bit and use the lowest non-C3 state. Note that the USB 1104 * driver polling for new devices keeps this bit set all the 1105 * time if USB is loaded. 1106 */ 1107 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1108 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1109 cx_next_idx > sc->cpu_non_c3 && 1110 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) { 1111 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1112 if (ACPI_SUCCESS(status) && bm_active != 0) { 1113 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1114 cx_next_idx = sc->cpu_non_c3; 1115 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1116 } 1117 } 1118 1119 /* Select the next state and update statistics. */ 1120 sc->cpu_cx_stats[cx_next_idx]++; 1121 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1122 1123 /* 1124 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1125 * precisely calculate the time spent in C1 since the place we wake up 1126 * is an ISR. Assume we slept no more then half of quantum, unless 1127 * we are called inside critical section, delaying context switch. 1128 */ 1129 if (cx_next->type == ACPI_STATE_C1) { 1130 start_ticks = cpu_ticks(); 1131 if (cx_next->p_lvlx != NULL) { 1132 /* C1 I/O then Halt */ 1133 CPU_GET_REG(cx_next->p_lvlx, 1); 1134 } 1135 if (cx_next->do_mwait) 1136 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1137 else 1138 acpi_cpu_c1(); 1139 end_ticks = cpu_ticks(); 1140 /* acpi_cpu_c1() returns with interrupts enabled. */ 1141 if (cx_next->do_mwait) 1142 ACPI_ENABLE_IRQS(); 1143 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1144 if (!cx_next->do_mwait && curthread->td_critnest == 0) 1145 end_time = min(end_time, 500000 / hz); 1146 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1147 return; 1148 } 1149 1150 /* 1151 * For C3, disable bus master arbitration and enable bus master wake 1152 * if BM control is available, otherwise flush the CPU cache. 1153 */ 1154 if (cx_next->type == ACPI_STATE_C3) { 1155 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1156 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1157 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1158 } else 1159 ACPI_FLUSH_CPU_CACHE(); 1160 } 1161 1162 /* 1163 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1164 * Use the ACPI timer for measuring sleep time. Since we need to 1165 * get the time very close to the CPU start/stop clock logic, this 1166 * is the only reliable time source. 1167 */ 1168 if (cx_next->type == ACPI_STATE_C3) { 1169 AcpiGetTimer(&start_time); 1170 start_ticks = 0; 1171 } else { 1172 start_time = 0; 1173 start_ticks = cpu_ticks(); 1174 } 1175 if (cx_next->do_mwait) { 1176 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1177 } else { 1178 CPU_GET_REG(cx_next->p_lvlx, 1); 1179 /* 1180 * Read the end time twice. Since it may take an arbitrary time 1181 * to enter the idle state, the first read may be executed before 1182 * the processor has stopped. Doing it again provides enough 1183 * margin that we are certain to have a correct value. 1184 */ 1185 AcpiGetTimer(&end_time); 1186 } 1187 1188 if (cx_next->type == ACPI_STATE_C3) 1189 AcpiGetTimer(&end_time); 1190 else 1191 end_ticks = cpu_ticks(); 1192 1193 /* Enable bus master arbitration and disable bus master wakeup. */ 1194 if (cx_next->type == ACPI_STATE_C3 && 1195 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1196 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1197 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1198 } 1199 ACPI_ENABLE_IRQS(); 1200 1201 if (cx_next->type == ACPI_STATE_C3) 1202 AcpiGetTimerDuration(start_time, end_time, &end_time); 1203 else 1204 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1205 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1206 } 1207 #endif 1208 1209 /* 1210 * Re-evaluate the _CST object when we are notified that it changed. 1211 */ 1212 static void 1213 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1214 { 1215 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1216 1217 if (notify != ACPI_NOTIFY_CX_STATES) 1218 return; 1219 1220 /* 1221 * C-state data for target CPU is going to be in flux while we execute 1222 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1223 * Also, it may happen that multiple ACPI taskqueues may concurrently 1224 * execute notifications for the same CPU. ACPI_SERIAL is used to 1225 * protect against that. 1226 */ 1227 ACPI_SERIAL_BEGIN(cpu); 1228 disable_idle(sc); 1229 1230 /* Update the list of Cx states. */ 1231 acpi_cpu_cx_cst(sc); 1232 acpi_cpu_cx_list(sc); 1233 acpi_cpu_set_cx_lowest(sc); 1234 1235 enable_idle(sc); 1236 ACPI_SERIAL_END(cpu); 1237 1238 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1239 } 1240 1241 static void 1242 acpi_cpu_quirks(void) 1243 { 1244 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1245 1246 /* 1247 * Bus mastering arbitration control is needed to keep caches coherent 1248 * while sleeping in C3. If it's not present but a working flush cache 1249 * instruction is present, flush the caches before entering C3 instead. 1250 * Otherwise, just disable C3 completely. 1251 */ 1252 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1253 AcpiGbl_FADT.Pm2ControlLength == 0) { 1254 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1255 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1256 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1257 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1258 "acpi_cpu: no BM control, using flush cache method\n")); 1259 } else { 1260 cpu_quirks |= CPU_QUIRK_NO_C3; 1261 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1262 "acpi_cpu: no BM control, C3 not available\n")); 1263 } 1264 } 1265 1266 /* 1267 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1268 * the expensive flush cache instruction. 1269 */ 1270 if (cpu_cx_generic && mp_ncpus > 1) { 1271 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1272 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1273 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1274 } 1275 1276 /* Look for various quirks of the PIIX4 part. */ 1277 acpi_cpu_quirks_piix4(); 1278 } 1279 1280 static void 1281 acpi_cpu_quirks_piix4(void) 1282 { 1283 #ifdef __i386__ 1284 device_t acpi_dev; 1285 uint32_t val; 1286 ACPI_STATUS status; 1287 1288 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1289 if (acpi_dev != NULL) { 1290 switch (pci_get_revid(acpi_dev)) { 1291 /* 1292 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1293 * do not report the BMIDE status to the BM status register and 1294 * others have a livelock bug if Type-F DMA is enabled. Linux 1295 * works around the BMIDE bug by reading the BM status directly 1296 * but we take the simpler approach of disabling C3 for these 1297 * parts. 1298 * 1299 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1300 * Livelock") from the January 2002 PIIX4 specification update. 1301 * Applies to all PIIX4 models. 1302 * 1303 * Also, make sure that all interrupts cause a "Stop Break" 1304 * event to exit from C2 state. 1305 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1306 * should be set to zero, otherwise it causes C2 to short-sleep. 1307 * PIIX4 doesn't properly support C3 and bus master activity 1308 * need not break out of C2. 1309 */ 1310 case PCI_REVISION_A_STEP: 1311 case PCI_REVISION_B_STEP: 1312 case PCI_REVISION_4E: 1313 case PCI_REVISION_4M: 1314 cpu_quirks |= CPU_QUIRK_NO_C3; 1315 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1316 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1317 1318 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1319 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1320 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1321 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1322 val |= PIIX4_STOP_BREAK_MASK; 1323 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1324 } 1325 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1326 if (ACPI_SUCCESS(status) && val != 0) { 1327 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1328 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1329 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1330 } 1331 break; 1332 default: 1333 break; 1334 } 1335 } 1336 #endif 1337 } 1338 1339 static int 1340 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1341 { 1342 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1343 struct sbuf sb; 1344 char buf[128]; 1345 int error, i; 1346 uintmax_t fract, sum, whole; 1347 1348 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1349 sum = 0; 1350 for (i = 0; i < sc->cpu_cx_count; i++) 1351 sum += sc->cpu_cx_stats[i]; 1352 for (i = 0; i < sc->cpu_cx_count; i++) { 1353 if (sum > 0) { 1354 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1355 fract = (whole % sum) * 100; 1356 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1357 (u_int)(fract / sum)); 1358 } else 1359 sbuf_printf(&sb, "0.00%% "); 1360 } 1361 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1362 error = sbuf_finish(&sb); 1363 sbuf_delete(&sb); 1364 return (error); 1365 } 1366 1367 /* 1368 * XXX TODO: actually add support to count each entry/exit 1369 * from the Cx states. 1370 */ 1371 static int 1372 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1373 { 1374 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1375 struct sbuf sb; 1376 char buf[128]; 1377 int error, i; 1378 1379 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1380 for (i = 0; i < sc->cpu_cx_count; i++) { 1381 if (i > 0) 1382 sbuf_putc(&sb, ' '); 1383 sbuf_printf(&sb, "%u", sc->cpu_cx_stats[i]); 1384 } 1385 error = sbuf_finish(&sb); 1386 sbuf_delete(&sb); 1387 return (error); 1388 } 1389 1390 #if defined(__i386__) || defined(__amd64__) 1391 static int 1392 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1393 { 1394 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)arg1; 1395 struct acpi_cx *cx; 1396 struct sbuf sb; 1397 char buf[128]; 1398 int error, i; 1399 1400 sbuf_new_for_sysctl(&sb, buf, sizeof(buf), req); 1401 for (i = 0; i < sc->cpu_cx_count; i++) { 1402 cx = &sc->cpu_cx_states[i]; 1403 if (i > 0) 1404 sbuf_putc(&sb, ' '); 1405 sbuf_printf(&sb, "C%d/", i + 1); 1406 if (cx->do_mwait) { 1407 sbuf_cat(&sb, "mwait"); 1408 if (cx->mwait_hw_coord) 1409 sbuf_cat(&sb, "/hwc"); 1410 if (cx->mwait_bm_avoidance) 1411 sbuf_cat(&sb, "/bma"); 1412 } else if (cx->type == ACPI_STATE_C1) { 1413 sbuf_cat(&sb, "hlt"); 1414 } else { 1415 sbuf_cat(&sb, "io"); 1416 } 1417 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1418 sbuf_cat(&sb, "/iohlt"); 1419 } 1420 error = sbuf_finish(&sb); 1421 sbuf_delete(&sb); 1422 return (error); 1423 } 1424 #endif 1425 1426 static int 1427 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1428 { 1429 int i; 1430 1431 ACPI_SERIAL_ASSERT(cpu); 1432 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1433 1434 /* If not disabling, cache the new lowest non-C3 state. */ 1435 sc->cpu_non_c3 = 0; 1436 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1437 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1438 sc->cpu_non_c3 = i; 1439 break; 1440 } 1441 } 1442 1443 /* Reset the statistics counters. */ 1444 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1445 return (0); 1446 } 1447 1448 static int 1449 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1450 { 1451 struct acpi_cpu_softc *sc; 1452 char state[8]; 1453 int val, error; 1454 1455 sc = (struct acpi_cpu_softc *) arg1; 1456 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1457 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1458 if (error != 0 || req->newptr == NULL) 1459 return (error); 1460 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1461 return (EINVAL); 1462 if (strcasecmp(state, "Cmax") == 0) 1463 val = MAX_CX_STATES; 1464 else { 1465 val = (int) strtol(state + 1, NULL, 10); 1466 if (val < 1 || val > MAX_CX_STATES) 1467 return (EINVAL); 1468 } 1469 1470 ACPI_SERIAL_BEGIN(cpu); 1471 sc->cpu_cx_lowest_lim = val - 1; 1472 acpi_cpu_set_cx_lowest(sc); 1473 ACPI_SERIAL_END(cpu); 1474 1475 return (0); 1476 } 1477 1478 static int 1479 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1480 { 1481 struct acpi_cpu_softc *sc; 1482 char state[8]; 1483 int val, error, i; 1484 1485 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1486 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1487 if (error != 0 || req->newptr == NULL) 1488 return (error); 1489 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1490 return (EINVAL); 1491 if (strcasecmp(state, "Cmax") == 0) 1492 val = MAX_CX_STATES; 1493 else { 1494 val = (int) strtol(state + 1, NULL, 10); 1495 if (val < 1 || val > MAX_CX_STATES) 1496 return (EINVAL); 1497 } 1498 1499 /* Update the new lowest useable Cx state for all CPUs. */ 1500 ACPI_SERIAL_BEGIN(cpu); 1501 cpu_cx_lowest_lim = val - 1; 1502 CPU_FOREACH(i) { 1503 if ((sc = cpu_softc[i]) == NULL) 1504 continue; 1505 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1506 acpi_cpu_set_cx_lowest(sc); 1507 } 1508 ACPI_SERIAL_END(cpu); 1509 1510 return (0); 1511 } 1512