1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #include <machine/specialreg.h> 51 #include <machine/md_var.h> 52 #endif 53 #include <sys/rman.h> 54 55 #include <contrib/dev/acpica/include/acpi.h> 56 #include <contrib/dev/acpica/include/accommon.h> 57 58 #include <dev/acpica/acpivar.h> 59 60 /* 61 * Support for ACPI Processor devices, including C[1-3] sleep states. 62 */ 63 64 /* Hooks for the ACPI CA debugging infrastructure */ 65 #define _COMPONENT ACPI_PROCESSOR 66 ACPI_MODULE_NAME("PROCESSOR") 67 68 struct acpi_cx { 69 struct resource *p_lvlx; /* Register to read to enter state. */ 70 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 71 uint32_t trans_lat; /* Transition latency (usec). */ 72 uint32_t power; /* Power consumed (mW). */ 73 int res_type; /* Resource type for p_lvlx. */ 74 int res_rid; /* Resource ID for p_lvlx. */ 75 bool do_mwait; 76 uint32_t mwait_hint; 77 bool mwait_hw_coord; 78 bool mwait_bm_avoidance; 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cpu_softc { 83 device_t cpu_dev; 84 ACPI_HANDLE cpu_handle; 85 struct pcpu *cpu_pcpu; 86 uint32_t cpu_acpi_id; /* ACPI processor id */ 87 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 89 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 90 int cpu_cx_count; /* Number of valid Cx states. */ 91 int cpu_prev_sleep;/* Last idle sleep duration. */ 92 int cpu_features; /* Child driver supported features. */ 93 /* Runtime state. */ 94 int cpu_non_c2; /* Index of lowest non-C2 state. */ 95 int cpu_non_c3; /* Index of lowest non-C3 state. */ 96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 struct sysctl_ctx_list cpu_sysctl_ctx; 99 struct sysctl_oid *cpu_sysctl_tree; 100 int cpu_cx_lowest; 101 int cpu_cx_lowest_lim; 102 int cpu_disable_idle; /* Disable entry to idle function */ 103 char cpu_cx_supported[64]; 104 }; 105 106 struct acpi_cpu_device { 107 struct resource_list ad_rl; 108 }; 109 110 #define CPU_GET_REG(reg, width) \ 111 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 112 rman_get_bushandle((reg)), 0)) 113 #define CPU_SET_REG(reg, width, val) \ 114 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 115 rman_get_bushandle((reg)), 0, (val))) 116 117 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 118 119 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 120 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 121 122 #define PCI_VENDOR_INTEL 0x8086 123 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 124 #define PCI_REVISION_A_STEP 0 125 #define PCI_REVISION_B_STEP 1 126 #define PCI_REVISION_4E 2 127 #define PCI_REVISION_4M 3 128 #define PIIX4_DEVACTB_REG 0x58 129 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 130 #define PIIX4_BRLD_EN_IRQ (1<<1) 131 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 132 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 133 #define PIIX4_PCNTRL_BST_EN (1<<10) 134 135 #define CST_FFH_VENDOR_INTEL 1 136 #define CST_FFH_INTEL_CL_C1IO 1 137 #define CST_FFH_INTEL_CL_MWAIT 2 138 #define CST_FFH_MWAIT_HW_COORD 0x0001 139 #define CST_FFH_MWAIT_BM_AVOID 0x0002 140 141 #define CPUDEV_DEVICE_ID "ACPI0007" 142 143 /* Knob to disable acpi_cpu devices */ 144 bool acpi_cpu_disabled = false; 145 146 /* Platform hardware resource information. */ 147 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 148 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 149 static int cpu_quirks; /* Indicate any hardware bugs. */ 150 151 /* Values for sysctl. */ 152 static struct sysctl_ctx_list cpu_sysctl_ctx; 153 static struct sysctl_oid *cpu_sysctl_tree; 154 static int cpu_cx_generic; 155 static int cpu_cx_lowest_lim; 156 157 static device_t *cpu_devices; 158 static int cpu_ndevices; 159 static struct acpi_cpu_softc **cpu_softc; 160 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 161 162 static int acpi_cpu_probe(device_t dev); 163 static int acpi_cpu_attach(device_t dev); 164 static int acpi_cpu_suspend(device_t dev); 165 static int acpi_cpu_resume(device_t dev); 166 static int acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, 167 u_int *cpu_id); 168 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 169 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 170 int unit); 171 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 172 uintptr_t *result); 173 static int acpi_cpu_shutdown(device_t dev); 174 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 175 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 176 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 177 static void acpi_cpu_startup(void *arg); 178 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 179 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 180 #if defined(__i386__) || defined(__amd64__) 181 static void acpi_cpu_idle(sbintime_t sbt); 182 #endif 183 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 184 static void acpi_cpu_quirks(void); 185 static void acpi_cpu_quirks_piix4(void); 186 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 187 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 188 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 189 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 190 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 191 #if defined(__i386__) || defined(__amd64__) 192 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS); 193 #endif 194 195 static device_method_t acpi_cpu_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_probe, acpi_cpu_probe), 198 DEVMETHOD(device_attach, acpi_cpu_attach), 199 DEVMETHOD(device_detach, bus_generic_detach), 200 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 201 DEVMETHOD(device_suspend, acpi_cpu_suspend), 202 DEVMETHOD(device_resume, acpi_cpu_resume), 203 204 /* Bus interface */ 205 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 206 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 207 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 208 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 209 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 210 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 211 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 212 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 213 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 214 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 215 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 216 217 DEVMETHOD_END 218 }; 219 220 static driver_t acpi_cpu_driver = { 221 "cpu", 222 acpi_cpu_methods, 223 sizeof(struct acpi_cpu_softc), 224 }; 225 226 static devclass_t acpi_cpu_devclass; 227 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 228 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 229 230 static int 231 acpi_cpu_probe(device_t dev) 232 { 233 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL }; 234 int acpi_id, cpu_id; 235 ACPI_BUFFER buf; 236 ACPI_HANDLE handle; 237 ACPI_OBJECT *obj; 238 ACPI_STATUS status; 239 ACPI_OBJECT_TYPE type; 240 241 if (acpi_disabled("cpu") || acpi_cpu_disabled) 242 return (ENXIO); 243 type = acpi_get_type(dev); 244 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE) 245 return (ENXIO); 246 if (type == ACPI_TYPE_DEVICE && 247 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids, NULL) >= 0) 248 return (ENXIO); 249 250 handle = acpi_get_handle(dev); 251 if (cpu_softc == NULL) 252 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 253 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 254 255 if (type == ACPI_TYPE_PROCESSOR) { 256 /* Get our Processor object. */ 257 buf.Pointer = NULL; 258 buf.Length = ACPI_ALLOCATE_BUFFER; 259 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 260 if (ACPI_FAILURE(status)) { 261 device_printf(dev, "probe failed to get Processor obj - %s\n", 262 AcpiFormatException(status)); 263 return (ENXIO); 264 } 265 obj = (ACPI_OBJECT *)buf.Pointer; 266 if (obj->Type != ACPI_TYPE_PROCESSOR) { 267 device_printf(dev, "Processor object has bad type %d\n", 268 obj->Type); 269 AcpiOsFree(obj); 270 return (ENXIO); 271 } 272 273 /* 274 * Find the processor associated with our unit. We could use the 275 * ProcId as a key, however, some boxes do not have the same values 276 * in their Processor object as the ProcId values in the MADT. 277 */ 278 acpi_id = obj->Processor.ProcId; 279 AcpiOsFree(obj); 280 } else { 281 status = acpi_GetInteger(handle, "_UID", &acpi_id); 282 if (ACPI_FAILURE(status)) { 283 device_printf(dev, "Device object has bad value - %s\n", 284 AcpiFormatException(status)); 285 return (ENXIO); 286 } 287 } 288 if (acpi_pcpu_get_id(dev, acpi_id, &cpu_id) != 0) { 289 if (bootverbose && (type != ACPI_TYPE_PROCESSOR || acpi_id != 255)) 290 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 291 acpi_name(acpi_get_handle(dev)), acpi_id); 292 return (ENXIO); 293 } 294 295 if (device_set_unit(dev, cpu_id) != 0) 296 return (ENXIO); 297 298 device_set_desc(dev, "ACPI CPU"); 299 300 if (!bootverbose && device_get_unit(dev) != 0) { 301 device_quiet(dev); 302 device_quiet_children(dev); 303 } 304 305 return (0); 306 } 307 308 static int 309 acpi_cpu_attach(device_t dev) 310 { 311 ACPI_BUFFER buf; 312 ACPI_OBJECT arg, *obj; 313 ACPI_OBJECT_LIST arglist; 314 struct pcpu *pcpu_data; 315 struct acpi_cpu_softc *sc; 316 struct acpi_softc *acpi_sc; 317 ACPI_STATUS status; 318 u_int features; 319 int cpu_id, drv_count, i; 320 driver_t **drivers; 321 uint32_t cap_set[3]; 322 323 /* UUID needed by _OSC evaluation */ 324 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 325 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 326 0x58, 0x71, 0x39, 0x53 }; 327 328 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 329 330 sc = device_get_softc(dev); 331 sc->cpu_dev = dev; 332 sc->cpu_handle = acpi_get_handle(dev); 333 cpu_id = device_get_unit(dev); 334 cpu_softc[cpu_id] = sc; 335 pcpu_data = pcpu_find(cpu_id); 336 pcpu_data->pc_device = dev; 337 sc->cpu_pcpu = pcpu_data; 338 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 339 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 340 341 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) { 342 buf.Pointer = NULL; 343 buf.Length = ACPI_ALLOCATE_BUFFER; 344 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 345 if (ACPI_FAILURE(status)) { 346 device_printf(dev, "attach failed to get Processor obj - %s\n", 347 AcpiFormatException(status)); 348 return (ENXIO); 349 } 350 obj = (ACPI_OBJECT *)buf.Pointer; 351 sc->cpu_p_blk = obj->Processor.PblkAddress; 352 sc->cpu_p_blk_len = obj->Processor.PblkLength; 353 sc->cpu_acpi_id = obj->Processor.ProcId; 354 AcpiOsFree(obj); 355 } else { 356 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE, 357 ("Unexpected ACPI object")); 358 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id); 359 if (ACPI_FAILURE(status)) { 360 device_printf(dev, "Device object has bad value - %s\n", 361 AcpiFormatException(status)); 362 return (ENXIO); 363 } 364 sc->cpu_p_blk = 0; 365 sc->cpu_p_blk_len = 0; 366 } 367 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 368 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 369 370 /* 371 * If this is the first cpu we attach, create and initialize the generic 372 * resources that will be used by all acpi cpu devices. 373 */ 374 if (device_get_unit(dev) == 0) { 375 /* Assume we won't be using generic Cx mode by default */ 376 cpu_cx_generic = FALSE; 377 378 /* Install hw.acpi.cpu sysctl tree */ 379 acpi_sc = acpi_device_get_parent_softc(dev); 380 sysctl_ctx_init(&cpu_sysctl_ctx); 381 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 382 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 383 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "node for CPU children"); 384 } 385 386 /* 387 * Before calling any CPU methods, collect child driver feature hints 388 * and notify ACPI of them. We support unified SMP power control 389 * so advertise this ourselves. Note this is not the same as independent 390 * SMP control where each CPU can have different settings. 391 */ 392 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 | 393 ACPI_CAP_C1_IO_HALT; 394 395 #if defined(__i386__) || defined(__amd64__) 396 /* 397 * Ask for MWAIT modes if not disabled and interrupts work 398 * reasonable with MWAIT. 399 */ 400 if (!acpi_disabled("mwait") && cpu_mwait_usable()) 401 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE; 402 #endif 403 404 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 405 for (i = 0; i < drv_count; i++) { 406 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 407 sc->cpu_features |= features; 408 } 409 free(drivers, M_TEMP); 410 } 411 412 /* 413 * CPU capabilities are specified in 414 * Intel Processor Vendor-Specific ACPI Interface Specification. 415 */ 416 if (sc->cpu_features) { 417 cap_set[1] = sc->cpu_features; 418 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set, 419 cap_set, false); 420 if (ACPI_SUCCESS(status)) { 421 if (cap_set[0] != 0) 422 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 423 } 424 else { 425 arglist.Pointer = &arg; 426 arglist.Count = 1; 427 arg.Type = ACPI_TYPE_BUFFER; 428 arg.Buffer.Length = sizeof(cap_set); 429 arg.Buffer.Pointer = (uint8_t *)cap_set; 430 cap_set[0] = 1; /* revision */ 431 cap_set[1] = 1; /* number of capabilities integers */ 432 cap_set[2] = sc->cpu_features; 433 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 434 } 435 } 436 437 /* Probe for Cx state support. */ 438 acpi_cpu_cx_probe(sc); 439 440 return (0); 441 } 442 443 static void 444 acpi_cpu_postattach(void *unused __unused) 445 { 446 device_t *devices; 447 int err; 448 int i, n; 449 int attached; 450 451 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 452 if (err != 0) { 453 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 454 return; 455 } 456 attached = 0; 457 for (i = 0; i < n; i++) 458 if (device_is_attached(devices[i]) && 459 device_get_driver(devices[i]) == &acpi_cpu_driver) 460 attached = 1; 461 for (i = 0; i < n; i++) 462 bus_generic_probe(devices[i]); 463 for (i = 0; i < n; i++) 464 bus_generic_attach(devices[i]); 465 free(devices, M_TEMP); 466 467 if (attached) { 468 #ifdef EARLY_AP_STARTUP 469 acpi_cpu_startup(NULL); 470 #else 471 /* Queue post cpu-probing task handler */ 472 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 473 #endif 474 } 475 } 476 477 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 478 acpi_cpu_postattach, NULL); 479 480 static void 481 disable_idle(struct acpi_cpu_softc *sc) 482 { 483 cpuset_t cpuset; 484 485 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 486 sc->cpu_disable_idle = TRUE; 487 488 /* 489 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 490 * Note that this code depends on the fact that the rendezvous IPI 491 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 492 * is called and executed in such a context with interrupts being re-enabled 493 * right before return. 494 */ 495 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL, 496 smp_no_rendezvous_barrier, NULL); 497 } 498 499 static void 500 enable_idle(struct acpi_cpu_softc *sc) 501 { 502 503 sc->cpu_disable_idle = FALSE; 504 } 505 506 #if defined(__i386__) || defined(__amd64__) 507 static int 508 is_idle_disabled(struct acpi_cpu_softc *sc) 509 { 510 511 return (sc->cpu_disable_idle); 512 } 513 #endif 514 515 /* 516 * Disable any entry to the idle function during suspend and re-enable it 517 * during resume. 518 */ 519 static int 520 acpi_cpu_suspend(device_t dev) 521 { 522 int error; 523 524 error = bus_generic_suspend(dev); 525 if (error) 526 return (error); 527 disable_idle(device_get_softc(dev)); 528 return (0); 529 } 530 531 static int 532 acpi_cpu_resume(device_t dev) 533 { 534 535 enable_idle(device_get_softc(dev)); 536 return (bus_generic_resume(dev)); 537 } 538 539 /* 540 * Find the processor associated with a given ACPI ID. 541 */ 542 static int 543 acpi_pcpu_get_id(device_t dev, uint32_t acpi_id, u_int *cpu_id) 544 { 545 struct pcpu *pc; 546 u_int i; 547 548 CPU_FOREACH(i) { 549 pc = pcpu_find(i); 550 if (pc->pc_acpi_id == acpi_id) { 551 *cpu_id = pc->pc_cpuid; 552 return (0); 553 } 554 } 555 556 /* 557 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 558 * UP box) use the ACPI ID from the first processor we find. 559 */ 560 if (mp_ncpus == 1) { 561 pc = pcpu_find(0); 562 if (pc->pc_acpi_id == 0xffffffff) 563 pc->pc_acpi_id = acpi_id; 564 *cpu_id = 0; 565 return (0); 566 } 567 568 return (ESRCH); 569 } 570 571 static struct resource_list * 572 acpi_cpu_get_rlist(device_t dev, device_t child) 573 { 574 struct acpi_cpu_device *ad; 575 576 ad = device_get_ivars(child); 577 if (ad == NULL) 578 return (NULL); 579 return (&ad->ad_rl); 580 } 581 582 static device_t 583 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 584 { 585 struct acpi_cpu_device *ad; 586 device_t child; 587 588 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 589 return (NULL); 590 591 resource_list_init(&ad->ad_rl); 592 593 child = device_add_child_ordered(dev, order, name, unit); 594 if (child != NULL) 595 device_set_ivars(child, ad); 596 else 597 free(ad, M_TEMP); 598 return (child); 599 } 600 601 static int 602 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 603 { 604 struct acpi_cpu_softc *sc; 605 606 sc = device_get_softc(dev); 607 switch (index) { 608 case ACPI_IVAR_HANDLE: 609 *result = (uintptr_t)sc->cpu_handle; 610 break; 611 case CPU_IVAR_PCPU: 612 *result = (uintptr_t)sc->cpu_pcpu; 613 break; 614 #if defined(__amd64__) || defined(__i386__) 615 case CPU_IVAR_NOMINAL_MHZ: 616 if (tsc_is_invariant) { 617 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 618 break; 619 } 620 /* FALLTHROUGH */ 621 #endif 622 default: 623 return (ENOENT); 624 } 625 return (0); 626 } 627 628 static int 629 acpi_cpu_shutdown(device_t dev) 630 { 631 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 632 633 /* Allow children to shutdown first. */ 634 bus_generic_shutdown(dev); 635 636 /* 637 * Disable any entry to the idle function. 638 */ 639 disable_idle(device_get_softc(dev)); 640 641 /* 642 * CPU devices are not truly detached and remain referenced, 643 * so their resources are not freed. 644 */ 645 646 return_VALUE (0); 647 } 648 649 static void 650 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 651 { 652 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 653 654 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 655 sc->cpu_prev_sleep = 1000000; 656 sc->cpu_cx_lowest = 0; 657 sc->cpu_cx_lowest_lim = 0; 658 659 /* 660 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 661 * any, we'll revert to generic FADT/P_BLK Cx control method which will 662 * be handled by acpi_cpu_startup. We need to defer to after having 663 * probed all the cpus in the system before probing for generic Cx 664 * states as we may already have found cpus with valid _CST packages 665 */ 666 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 667 /* 668 * We were unable to find a _CST package for this cpu or there 669 * was an error parsing it. Switch back to generic mode. 670 */ 671 cpu_cx_generic = TRUE; 672 if (bootverbose) 673 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 674 } 675 676 /* 677 * TODO: _CSD Package should be checked here. 678 */ 679 } 680 681 static void 682 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 683 { 684 ACPI_GENERIC_ADDRESS gas; 685 struct acpi_cx *cx_ptr; 686 687 sc->cpu_cx_count = 0; 688 cx_ptr = sc->cpu_cx_states; 689 690 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 691 sc->cpu_prev_sleep = 1000000; 692 693 /* C1 has been required since just after ACPI 1.0 */ 694 cx_ptr->type = ACPI_STATE_C1; 695 cx_ptr->trans_lat = 0; 696 cx_ptr++; 697 sc->cpu_non_c2 = sc->cpu_cx_count; 698 sc->cpu_non_c3 = sc->cpu_cx_count; 699 sc->cpu_cx_count++; 700 701 /* 702 * The spec says P_BLK must be 6 bytes long. However, some systems 703 * use it to indicate a fractional set of features present so we 704 * take 5 as C2. Some may also have a value of 7 to indicate 705 * another C3 but most use _CST for this (as required) and having 706 * "only" C1-C3 is not a hardship. 707 */ 708 if (sc->cpu_p_blk_len < 5) 709 return; 710 711 /* Validate and allocate resources for C2 (P_LVL2). */ 712 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 713 gas.BitWidth = 8; 714 if (AcpiGbl_FADT.C2Latency <= 100) { 715 gas.Address = sc->cpu_p_blk + 4; 716 cx_ptr->res_rid = 0; 717 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 718 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 719 if (cx_ptr->p_lvlx != NULL) { 720 cx_ptr->type = ACPI_STATE_C2; 721 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 722 cx_ptr++; 723 sc->cpu_non_c3 = sc->cpu_cx_count; 724 sc->cpu_cx_count++; 725 } 726 } 727 if (sc->cpu_p_blk_len < 6) 728 return; 729 730 /* Validate and allocate resources for C3 (P_LVL3). */ 731 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 732 gas.Address = sc->cpu_p_blk + 5; 733 cx_ptr->res_rid = 1; 734 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 735 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 736 if (cx_ptr->p_lvlx != NULL) { 737 cx_ptr->type = ACPI_STATE_C3; 738 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 739 cx_ptr++; 740 sc->cpu_cx_count++; 741 } 742 } 743 } 744 745 #if defined(__i386__) || defined(__amd64__) 746 static void 747 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize) 748 { 749 750 cx_ptr->do_mwait = true; 751 cx_ptr->mwait_hint = address & 0xffffffff; 752 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0; 753 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0; 754 } 755 #endif 756 757 static void 758 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr) 759 { 760 761 if (cx_ptr->p_lvlx == NULL) 762 return; 763 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 764 cx_ptr->p_lvlx); 765 cx_ptr->p_lvlx = NULL; 766 } 767 768 /* 769 * Parse a _CST package and set up its Cx states. Since the _CST object 770 * can change dynamically, our notify handler may call this function 771 * to clean up and probe the new _CST package. 772 */ 773 static int 774 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 775 { 776 struct acpi_cx *cx_ptr; 777 ACPI_STATUS status; 778 ACPI_BUFFER buf; 779 ACPI_OBJECT *top; 780 ACPI_OBJECT *pkg; 781 uint32_t count; 782 int i; 783 #if defined(__i386__) || defined(__amd64__) 784 uint64_t address; 785 int vendor, class, accsize; 786 #endif 787 788 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 789 790 buf.Pointer = NULL; 791 buf.Length = ACPI_ALLOCATE_BUFFER; 792 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 793 if (ACPI_FAILURE(status)) 794 return (ENXIO); 795 796 /* _CST is a package with a count and at least one Cx package. */ 797 top = (ACPI_OBJECT *)buf.Pointer; 798 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 799 device_printf(sc->cpu_dev, "invalid _CST package\n"); 800 AcpiOsFree(buf.Pointer); 801 return (ENXIO); 802 } 803 if (count != top->Package.Count - 1) { 804 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 805 count, top->Package.Count - 1); 806 count = top->Package.Count - 1; 807 } 808 if (count > MAX_CX_STATES) { 809 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 810 count = MAX_CX_STATES; 811 } 812 813 sc->cpu_non_c2 = 0; 814 sc->cpu_non_c3 = 0; 815 sc->cpu_cx_count = 0; 816 cx_ptr = sc->cpu_cx_states; 817 818 /* 819 * C1 has been required since just after ACPI 1.0. 820 * Reserve the first slot for it. 821 */ 822 cx_ptr->type = ACPI_STATE_C0; 823 cx_ptr++; 824 sc->cpu_cx_count++; 825 826 /* Set up all valid states. */ 827 for (i = 0; i < count; i++) { 828 pkg = &top->Package.Elements[i + 1]; 829 if (!ACPI_PKG_VALID(pkg, 4) || 830 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 831 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 832 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 833 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 834 continue; 835 } 836 837 /* Validate the state to see if we should use it. */ 838 switch (cx_ptr->type) { 839 case ACPI_STATE_C1: 840 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 841 #if defined(__i386__) || defined(__amd64__) 842 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 843 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) { 844 if (class == CST_FFH_INTEL_CL_C1IO) { 845 /* C1 I/O then Halt */ 846 cx_ptr->res_rid = sc->cpu_cx_count; 847 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT, 848 cx_ptr->res_rid, address, 1); 849 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev, 850 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE | 851 RF_SHAREABLE); 852 if (cx_ptr->p_lvlx == NULL) { 853 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT, 854 cx_ptr->res_rid); 855 device_printf(sc->cpu_dev, 856 "C1 I/O failed to allocate port %d, " 857 "degrading to C1 Halt", (int)address); 858 } 859 } else if (class == CST_FFH_INTEL_CL_MWAIT) { 860 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 861 } 862 } 863 #endif 864 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 865 /* This is the first C1 state. Use the reserved slot. */ 866 sc->cpu_cx_states[0] = *cx_ptr; 867 } else { 868 sc->cpu_non_c2 = sc->cpu_cx_count; 869 sc->cpu_non_c3 = sc->cpu_cx_count; 870 cx_ptr++; 871 sc->cpu_cx_count++; 872 } 873 continue; 874 case ACPI_STATE_C2: 875 sc->cpu_non_c3 = sc->cpu_cx_count; 876 break; 877 case ACPI_STATE_C3: 878 default: 879 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 880 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 881 "acpi_cpu%d: C3[%d] not available.\n", 882 device_get_unit(sc->cpu_dev), i)); 883 continue; 884 } 885 break; 886 } 887 888 /* Free up any previous register. */ 889 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr); 890 891 /* Allocate the control register for C2 or C3. */ 892 #if defined(__i386__) || defined(__amd64__) 893 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address, 894 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL && 895 class == CST_FFH_INTEL_CL_MWAIT) { 896 /* Native C State Instruction use (mwait) */ 897 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize); 898 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 899 "acpi_cpu%d: Got C%d/mwait - %d latency\n", 900 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat)); 901 cx_ptr++; 902 sc->cpu_cx_count++; 903 } else 904 #endif 905 { 906 cx_ptr->res_rid = sc->cpu_cx_count; 907 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, 908 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE); 909 if (cx_ptr->p_lvlx) { 910 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 911 "acpi_cpu%d: Got C%d - %d latency\n", 912 device_get_unit(sc->cpu_dev), cx_ptr->type, 913 cx_ptr->trans_lat)); 914 cx_ptr++; 915 sc->cpu_cx_count++; 916 } 917 } 918 } 919 AcpiOsFree(buf.Pointer); 920 921 /* If C1 state was not found, we need one now. */ 922 cx_ptr = sc->cpu_cx_states; 923 if (cx_ptr->type == ACPI_STATE_C0) { 924 cx_ptr->type = ACPI_STATE_C1; 925 cx_ptr->trans_lat = 0; 926 } 927 928 return (0); 929 } 930 931 /* 932 * Call this *after* all CPUs have been attached. 933 */ 934 static void 935 acpi_cpu_startup(void *arg) 936 { 937 struct acpi_cpu_softc *sc; 938 int i; 939 940 /* Get set of CPU devices */ 941 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 942 943 /* 944 * Setup any quirks that might necessary now that we have probed 945 * all the CPUs 946 */ 947 acpi_cpu_quirks(); 948 949 if (cpu_cx_generic) { 950 /* 951 * We are using generic Cx mode, probe for available Cx states 952 * for all processors. 953 */ 954 for (i = 0; i < cpu_ndevices; i++) { 955 sc = device_get_softc(cpu_devices[i]); 956 acpi_cpu_generic_cx_probe(sc); 957 } 958 } else { 959 /* 960 * We are using _CST mode, remove C3 state if necessary. 961 * As we now know for sure that we will be using _CST mode 962 * install our notify handler. 963 */ 964 for (i = 0; i < cpu_ndevices; i++) { 965 sc = device_get_softc(cpu_devices[i]); 966 if (cpu_quirks & CPU_QUIRK_NO_C3) { 967 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1); 968 } 969 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 970 acpi_cpu_notify, sc); 971 } 972 } 973 974 /* Perform Cx final initialization. */ 975 for (i = 0; i < cpu_ndevices; i++) { 976 sc = device_get_softc(cpu_devices[i]); 977 acpi_cpu_startup_cx(sc); 978 } 979 980 /* Add a sysctl handler to handle global Cx lowest setting */ 981 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 982 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 983 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 984 "Global lowest Cx sleep state to use"); 985 986 /* Take over idling from cpu_idle_default(). */ 987 cpu_cx_lowest_lim = 0; 988 for (i = 0; i < cpu_ndevices; i++) { 989 sc = device_get_softc(cpu_devices[i]); 990 enable_idle(sc); 991 } 992 #if defined(__i386__) || defined(__amd64__) 993 cpu_idle_hook = acpi_cpu_idle; 994 #endif 995 } 996 997 static void 998 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 999 { 1000 struct sbuf sb; 1001 int i; 1002 1003 /* 1004 * Set up the list of Cx states 1005 */ 1006 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 1007 SBUF_FIXEDLEN); 1008 for (i = 0; i < sc->cpu_cx_count; i++) 1009 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 1010 sc->cpu_cx_states[i].trans_lat); 1011 sbuf_trim(&sb); 1012 sbuf_finish(&sb); 1013 } 1014 1015 static void 1016 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 1017 { 1018 acpi_cpu_cx_list(sc); 1019 1020 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 1021 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 1022 OID_AUTO, "cx_supported", CTLFLAG_RD, 1023 sc->cpu_cx_supported, 0, 1024 "Cx/microsecond values for supported Cx states"); 1025 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1026 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1027 "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1028 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 1029 "lowest Cx sleep state to use"); 1030 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1031 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1032 "cx_usage", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 1033 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 1034 "percent usage for each Cx state"); 1035 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1036 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1037 "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 1038 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 1039 "Cx sleep state counters"); 1040 #if defined(__i386__) || defined(__amd64__) 1041 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 1042 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), OID_AUTO, 1043 "cx_method", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 1044 (void *)sc, 0, acpi_cpu_method_sysctl, "A", "Cx entrance methods"); 1045 #endif 1046 1047 /* Signal platform that we can handle _CST notification. */ 1048 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 1049 ACPI_LOCK(acpi); 1050 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 1051 ACPI_UNLOCK(acpi); 1052 } 1053 } 1054 1055 #if defined(__i386__) || defined(__amd64__) 1056 /* 1057 * Idle the CPU in the lowest state possible. This function is called with 1058 * interrupts disabled. Note that once it re-enables interrupts, a task 1059 * switch can occur so do not access shared data (i.e. the softc) after 1060 * interrupts are re-enabled. 1061 */ 1062 static void 1063 acpi_cpu_idle(sbintime_t sbt) 1064 { 1065 struct acpi_cpu_softc *sc; 1066 struct acpi_cx *cx_next; 1067 uint64_t start_ticks, end_ticks; 1068 uint32_t start_time, end_time; 1069 ACPI_STATUS status; 1070 int bm_active, cx_next_idx, i, us; 1071 1072 /* 1073 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 1074 * since there is no ACPI processor object for this CPU. This occurs 1075 * for logical CPUs in the HTT case. 1076 */ 1077 sc = cpu_softc[PCPU_GET(cpuid)]; 1078 if (sc == NULL) { 1079 acpi_cpu_c1(); 1080 return; 1081 } 1082 1083 /* If disabled, take the safe path. */ 1084 if (is_idle_disabled(sc)) { 1085 acpi_cpu_c1(); 1086 return; 1087 } 1088 1089 /* Find the lowest state that has small enough latency. */ 1090 us = sc->cpu_prev_sleep; 1091 if (sbt >= 0 && us > (sbt >> 12)) 1092 us = (sbt >> 12); 1093 cx_next_idx = 0; 1094 if (cpu_disable_c2_sleep) 1095 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2); 1096 else if (cpu_disable_c3_sleep) 1097 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 1098 else 1099 i = sc->cpu_cx_lowest; 1100 for (; i >= 0; i--) { 1101 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1102 cx_next_idx = i; 1103 break; 1104 } 1105 } 1106 1107 /* 1108 * Check for bus master activity. If there was activity, clear 1109 * the bit and use the lowest non-C3 state. Note that the USB 1110 * driver polling for new devices keeps this bit set all the 1111 * time if USB is loaded. 1112 */ 1113 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1114 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1115 cx_next_idx > sc->cpu_non_c3 && 1116 (!cx_next->do_mwait || cx_next->mwait_bm_avoidance)) { 1117 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1118 if (ACPI_SUCCESS(status) && bm_active != 0) { 1119 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1120 cx_next_idx = sc->cpu_non_c3; 1121 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1122 } 1123 } 1124 1125 /* Select the next state and update statistics. */ 1126 sc->cpu_cx_stats[cx_next_idx]++; 1127 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1128 1129 /* 1130 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1131 * precisely calculate the time spent in C1 since the place we wake up 1132 * is an ISR. Assume we slept no more then half of quantum, unless 1133 * we are called inside critical section, delaying context switch. 1134 */ 1135 if (cx_next->type == ACPI_STATE_C1) { 1136 start_ticks = cpu_ticks(); 1137 if (cx_next->p_lvlx != NULL) { 1138 /* C1 I/O then Halt */ 1139 CPU_GET_REG(cx_next->p_lvlx, 1); 1140 } 1141 if (cx_next->do_mwait) 1142 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1143 else 1144 acpi_cpu_c1(); 1145 end_ticks = cpu_ticks(); 1146 /* acpi_cpu_c1() returns with interrupts enabled. */ 1147 if (cx_next->do_mwait) 1148 ACPI_ENABLE_IRQS(); 1149 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1150 if (!cx_next->do_mwait && curthread->td_critnest == 0) 1151 end_time = min(end_time, 500000 / hz); 1152 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1153 return; 1154 } 1155 1156 /* 1157 * For C3, disable bus master arbitration and enable bus master wake 1158 * if BM control is available, otherwise flush the CPU cache. 1159 */ 1160 if (cx_next->type == ACPI_STATE_C3) { 1161 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1162 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1163 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1164 } else 1165 ACPI_FLUSH_CPU_CACHE(); 1166 } 1167 1168 /* 1169 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1170 * Use the ACPI timer for measuring sleep time. Since we need to 1171 * get the time very close to the CPU start/stop clock logic, this 1172 * is the only reliable time source. 1173 */ 1174 if (cx_next->type == ACPI_STATE_C3) { 1175 AcpiGetTimer(&start_time); 1176 start_ticks = 0; 1177 } else { 1178 start_time = 0; 1179 start_ticks = cpu_ticks(); 1180 } 1181 if (cx_next->do_mwait) { 1182 acpi_cpu_idle_mwait(cx_next->mwait_hint); 1183 } else { 1184 CPU_GET_REG(cx_next->p_lvlx, 1); 1185 /* 1186 * Read the end time twice. Since it may take an arbitrary time 1187 * to enter the idle state, the first read may be executed before 1188 * the processor has stopped. Doing it again provides enough 1189 * margin that we are certain to have a correct value. 1190 */ 1191 AcpiGetTimer(&end_time); 1192 } 1193 1194 if (cx_next->type == ACPI_STATE_C3) 1195 AcpiGetTimer(&end_time); 1196 else 1197 end_ticks = cpu_ticks(); 1198 1199 /* Enable bus master arbitration and disable bus master wakeup. */ 1200 if (cx_next->type == ACPI_STATE_C3 && 1201 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1202 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1203 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1204 } 1205 ACPI_ENABLE_IRQS(); 1206 1207 if (cx_next->type == ACPI_STATE_C3) 1208 AcpiGetTimerDuration(start_time, end_time, &end_time); 1209 else 1210 end_time = ((end_ticks - start_ticks) << 20) / cpu_tickrate(); 1211 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1212 } 1213 #endif 1214 1215 /* 1216 * Re-evaluate the _CST object when we are notified that it changed. 1217 */ 1218 static void 1219 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1220 { 1221 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1222 1223 if (notify != ACPI_NOTIFY_CX_STATES) 1224 return; 1225 1226 /* 1227 * C-state data for target CPU is going to be in flux while we execute 1228 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1229 * Also, it may happen that multiple ACPI taskqueues may concurrently 1230 * execute notifications for the same CPU. ACPI_SERIAL is used to 1231 * protect against that. 1232 */ 1233 ACPI_SERIAL_BEGIN(cpu); 1234 disable_idle(sc); 1235 1236 /* Update the list of Cx states. */ 1237 acpi_cpu_cx_cst(sc); 1238 acpi_cpu_cx_list(sc); 1239 acpi_cpu_set_cx_lowest(sc); 1240 1241 enable_idle(sc); 1242 ACPI_SERIAL_END(cpu); 1243 1244 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1245 } 1246 1247 static void 1248 acpi_cpu_quirks(void) 1249 { 1250 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1251 1252 /* 1253 * Bus mastering arbitration control is needed to keep caches coherent 1254 * while sleeping in C3. If it's not present but a working flush cache 1255 * instruction is present, flush the caches before entering C3 instead. 1256 * Otherwise, just disable C3 completely. 1257 */ 1258 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1259 AcpiGbl_FADT.Pm2ControlLength == 0) { 1260 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1261 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1262 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1263 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1264 "acpi_cpu: no BM control, using flush cache method\n")); 1265 } else { 1266 cpu_quirks |= CPU_QUIRK_NO_C3; 1267 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1268 "acpi_cpu: no BM control, C3 not available\n")); 1269 } 1270 } 1271 1272 /* 1273 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1274 * the expensive flush cache instruction. 1275 */ 1276 if (cpu_cx_generic && mp_ncpus > 1) { 1277 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1278 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1279 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1280 } 1281 1282 /* Look for various quirks of the PIIX4 part. */ 1283 acpi_cpu_quirks_piix4(); 1284 } 1285 1286 static void 1287 acpi_cpu_quirks_piix4(void) 1288 { 1289 #ifdef __i386__ 1290 device_t acpi_dev; 1291 uint32_t val; 1292 ACPI_STATUS status; 1293 1294 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1295 if (acpi_dev != NULL) { 1296 switch (pci_get_revid(acpi_dev)) { 1297 /* 1298 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1299 * do not report the BMIDE status to the BM status register and 1300 * others have a livelock bug if Type-F DMA is enabled. Linux 1301 * works around the BMIDE bug by reading the BM status directly 1302 * but we take the simpler approach of disabling C3 for these 1303 * parts. 1304 * 1305 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1306 * Livelock") from the January 2002 PIIX4 specification update. 1307 * Applies to all PIIX4 models. 1308 * 1309 * Also, make sure that all interrupts cause a "Stop Break" 1310 * event to exit from C2 state. 1311 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1312 * should be set to zero, otherwise it causes C2 to short-sleep. 1313 * PIIX4 doesn't properly support C3 and bus master activity 1314 * need not break out of C2. 1315 */ 1316 case PCI_REVISION_A_STEP: 1317 case PCI_REVISION_B_STEP: 1318 case PCI_REVISION_4E: 1319 case PCI_REVISION_4M: 1320 cpu_quirks |= CPU_QUIRK_NO_C3; 1321 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1322 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1323 1324 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1325 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1326 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1327 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1328 val |= PIIX4_STOP_BREAK_MASK; 1329 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1330 } 1331 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1332 if (ACPI_SUCCESS(status) && val != 0) { 1333 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1334 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1335 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1336 } 1337 break; 1338 default: 1339 break; 1340 } 1341 } 1342 #endif 1343 } 1344 1345 static int 1346 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1347 { 1348 struct acpi_cpu_softc *sc; 1349 struct sbuf sb; 1350 char buf[128]; 1351 int i; 1352 uintmax_t fract, sum, whole; 1353 1354 sc = (struct acpi_cpu_softc *) arg1; 1355 sum = 0; 1356 for (i = 0; i < sc->cpu_cx_count; i++) 1357 sum += sc->cpu_cx_stats[i]; 1358 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1359 for (i = 0; i < sc->cpu_cx_count; i++) { 1360 if (sum > 0) { 1361 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1362 fract = (whole % sum) * 100; 1363 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1364 (u_int)(fract / sum)); 1365 } else 1366 sbuf_printf(&sb, "0.00%% "); 1367 } 1368 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1369 sbuf_trim(&sb); 1370 sbuf_finish(&sb); 1371 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1372 sbuf_delete(&sb); 1373 1374 return (0); 1375 } 1376 1377 /* 1378 * XXX TODO: actually add support to count each entry/exit 1379 * from the Cx states. 1380 */ 1381 static int 1382 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1383 { 1384 struct acpi_cpu_softc *sc; 1385 struct sbuf sb; 1386 char buf[128]; 1387 int i; 1388 1389 sc = (struct acpi_cpu_softc *) arg1; 1390 1391 /* Print out the raw counters */ 1392 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1393 1394 for (i = 0; i < sc->cpu_cx_count; i++) { 1395 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]); 1396 } 1397 1398 sbuf_trim(&sb); 1399 sbuf_finish(&sb); 1400 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1401 sbuf_delete(&sb); 1402 1403 return (0); 1404 } 1405 1406 #if defined(__i386__) || defined(__amd64__) 1407 static int 1408 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS) 1409 { 1410 struct acpi_cpu_softc *sc; 1411 struct acpi_cx *cx; 1412 struct sbuf sb; 1413 char buf[128]; 1414 int i; 1415 1416 sc = (struct acpi_cpu_softc *)arg1; 1417 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1418 for (i = 0; i < sc->cpu_cx_count; i++) { 1419 cx = &sc->cpu_cx_states[i]; 1420 sbuf_printf(&sb, "C%d/", i + 1); 1421 if (cx->do_mwait) { 1422 sbuf_cat(&sb, "mwait"); 1423 if (cx->mwait_hw_coord) 1424 sbuf_cat(&sb, "/hwc"); 1425 if (cx->mwait_bm_avoidance) 1426 sbuf_cat(&sb, "/bma"); 1427 } else if (cx->type == ACPI_STATE_C1) { 1428 sbuf_cat(&sb, "hlt"); 1429 } else { 1430 sbuf_cat(&sb, "io"); 1431 } 1432 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL) 1433 sbuf_cat(&sb, "/iohlt"); 1434 sbuf_putc(&sb, ' '); 1435 } 1436 sbuf_trim(&sb); 1437 sbuf_finish(&sb); 1438 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1439 sbuf_delete(&sb); 1440 return (0); 1441 } 1442 #endif 1443 1444 static int 1445 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1446 { 1447 int i; 1448 1449 ACPI_SERIAL_ASSERT(cpu); 1450 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1451 1452 /* If not disabling, cache the new lowest non-C3 state. */ 1453 sc->cpu_non_c3 = 0; 1454 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1455 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1456 sc->cpu_non_c3 = i; 1457 break; 1458 } 1459 } 1460 1461 /* Reset the statistics counters. */ 1462 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1463 return (0); 1464 } 1465 1466 static int 1467 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1468 { 1469 struct acpi_cpu_softc *sc; 1470 char state[8]; 1471 int val, error; 1472 1473 sc = (struct acpi_cpu_softc *) arg1; 1474 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1475 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1476 if (error != 0 || req->newptr == NULL) 1477 return (error); 1478 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1479 return (EINVAL); 1480 if (strcasecmp(state, "Cmax") == 0) 1481 val = MAX_CX_STATES; 1482 else { 1483 val = (int) strtol(state + 1, NULL, 10); 1484 if (val < 1 || val > MAX_CX_STATES) 1485 return (EINVAL); 1486 } 1487 1488 ACPI_SERIAL_BEGIN(cpu); 1489 sc->cpu_cx_lowest_lim = val - 1; 1490 acpi_cpu_set_cx_lowest(sc); 1491 ACPI_SERIAL_END(cpu); 1492 1493 return (0); 1494 } 1495 1496 static int 1497 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1498 { 1499 struct acpi_cpu_softc *sc; 1500 char state[8]; 1501 int val, error, i; 1502 1503 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1504 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1505 if (error != 0 || req->newptr == NULL) 1506 return (error); 1507 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1508 return (EINVAL); 1509 if (strcasecmp(state, "Cmax") == 0) 1510 val = MAX_CX_STATES; 1511 else { 1512 val = (int) strtol(state + 1, NULL, 10); 1513 if (val < 1 || val > MAX_CX_STATES) 1514 return (EINVAL); 1515 } 1516 1517 /* Update the new lowest useable Cx state for all CPUs. */ 1518 ACPI_SERIAL_BEGIN(cpu); 1519 cpu_cx_lowest_lim = val - 1; 1520 for (i = 0; i < cpu_ndevices; i++) { 1521 sc = device_get_softc(cpu_devices[i]); 1522 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1523 acpi_cpu_set_cx_lowest(sc); 1524 } 1525 ACPI_SERIAL_END(cpu); 1526 1527 return (0); 1528 } 1529