1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sbuf.h> 42 #include <sys/smp.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <machine/atomic.h> 46 #include <machine/bus.h> 47 #if defined(__amd64__) || defined(__i386__) 48 #include <machine/clock.h> 49 #endif 50 #include <sys/rman.h> 51 52 #include <contrib/dev/acpica/include/acpi.h> 53 #include <contrib/dev/acpica/include/accommon.h> 54 55 #include <dev/acpica/acpivar.h> 56 57 /* 58 * Support for ACPI Processor devices, including C[1-3] sleep states. 59 */ 60 61 /* Hooks for the ACPI CA debugging infrastructure */ 62 #define _COMPONENT ACPI_PROCESSOR 63 ACPI_MODULE_NAME("PROCESSOR") 64 65 struct acpi_cx { 66 struct resource *p_lvlx; /* Register to read to enter state. */ 67 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 68 uint32_t trans_lat; /* Transition latency (usec). */ 69 uint32_t power; /* Power consumed (mW). */ 70 int res_type; /* Resource type for p_lvlx. */ 71 }; 72 #define MAX_CX_STATES 8 73 74 struct acpi_cpu_softc { 75 device_t cpu_dev; 76 ACPI_HANDLE cpu_handle; 77 struct pcpu *cpu_pcpu; 78 uint32_t cpu_acpi_id; /* ACPI processor id */ 79 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 80 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 81 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 82 int cpu_cx_count; /* Number of valid Cx states. */ 83 int cpu_prev_sleep;/* Last idle sleep duration. */ 84 int cpu_features; /* Child driver supported features. */ 85 /* Runtime state. */ 86 int cpu_non_c3; /* Index of lowest non-C3 state. */ 87 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 88 /* Values for sysctl. */ 89 struct sysctl_ctx_list cpu_sysctl_ctx; 90 struct sysctl_oid *cpu_sysctl_tree; 91 int cpu_cx_lowest; 92 int cpu_cx_lowest_lim; 93 char cpu_cx_supported[64]; 94 int cpu_rid; 95 }; 96 97 struct acpi_cpu_device { 98 struct resource_list ad_rl; 99 }; 100 101 #define CPU_GET_REG(reg, width) \ 102 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 103 rman_get_bushandle((reg)), 0)) 104 #define CPU_SET_REG(reg, width, val) \ 105 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 106 rman_get_bushandle((reg)), 0, (val))) 107 108 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 109 110 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 111 112 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 113 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 114 115 #define PCI_VENDOR_INTEL 0x8086 116 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 117 #define PCI_REVISION_A_STEP 0 118 #define PCI_REVISION_B_STEP 1 119 #define PCI_REVISION_4E 2 120 #define PCI_REVISION_4M 3 121 #define PIIX4_DEVACTB_REG 0x58 122 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 123 #define PIIX4_BRLD_EN_IRQ (1<<1) 124 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 125 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 126 #define PIIX4_PCNTRL_BST_EN (1<<10) 127 128 /* Allow users to ignore processor orders in MADT. */ 129 static int cpu_unordered; 130 TUNABLE_INT("debug.acpi.cpu_unordered", &cpu_unordered); 131 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN, 132 &cpu_unordered, 0, 133 "Do not use the MADT to match ACPI Processor objects to CPUs."); 134 135 /* Platform hardware resource information. */ 136 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 137 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 138 static int cpu_quirks; /* Indicate any hardware bugs. */ 139 140 /* Runtime state. */ 141 static int cpu_disable_idle; /* Disable entry to idle function */ 142 143 /* Values for sysctl. */ 144 static struct sysctl_ctx_list cpu_sysctl_ctx; 145 static struct sysctl_oid *cpu_sysctl_tree; 146 static int cpu_cx_generic; 147 static int cpu_cx_lowest_lim; 148 149 static device_t *cpu_devices; 150 static int cpu_ndevices; 151 static struct acpi_cpu_softc **cpu_softc; 152 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 153 154 static int acpi_cpu_probe(device_t dev); 155 static int acpi_cpu_attach(device_t dev); 156 static int acpi_cpu_suspend(device_t dev); 157 static int acpi_cpu_resume(device_t dev); 158 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, 159 uint32_t *cpu_id); 160 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 161 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 162 int unit); 163 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 164 uintptr_t *result); 165 static int acpi_cpu_shutdown(device_t dev); 166 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 167 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 168 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 169 static void acpi_cpu_startup(void *arg); 170 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 171 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 172 static void acpi_cpu_idle(void); 173 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 174 static int acpi_cpu_quirks(void); 175 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 176 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 177 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 178 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 179 180 static device_method_t acpi_cpu_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, acpi_cpu_probe), 183 DEVMETHOD(device_attach, acpi_cpu_attach), 184 DEVMETHOD(device_detach, bus_generic_detach), 185 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 186 DEVMETHOD(device_suspend, acpi_cpu_suspend), 187 DEVMETHOD(device_resume, acpi_cpu_resume), 188 189 /* Bus interface */ 190 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 191 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 192 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 193 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 194 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 195 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 196 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 197 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 198 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 199 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 200 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 201 202 DEVMETHOD_END 203 }; 204 205 static driver_t acpi_cpu_driver = { 206 "cpu", 207 acpi_cpu_methods, 208 sizeof(struct acpi_cpu_softc), 209 }; 210 211 static devclass_t acpi_cpu_devclass; 212 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 213 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 214 215 static int 216 acpi_cpu_probe(device_t dev) 217 { 218 int acpi_id, cpu_id; 219 ACPI_BUFFER buf; 220 ACPI_HANDLE handle; 221 ACPI_OBJECT *obj; 222 ACPI_STATUS status; 223 224 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 225 return (ENXIO); 226 227 handle = acpi_get_handle(dev); 228 if (cpu_softc == NULL) 229 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 230 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 231 232 /* Get our Processor object. */ 233 buf.Pointer = NULL; 234 buf.Length = ACPI_ALLOCATE_BUFFER; 235 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 236 if (ACPI_FAILURE(status)) { 237 device_printf(dev, "probe failed to get Processor obj - %s\n", 238 AcpiFormatException(status)); 239 return (ENXIO); 240 } 241 obj = (ACPI_OBJECT *)buf.Pointer; 242 if (obj->Type != ACPI_TYPE_PROCESSOR) { 243 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 244 AcpiOsFree(obj); 245 return (ENXIO); 246 } 247 248 /* 249 * Find the processor associated with our unit. We could use the 250 * ProcId as a key, however, some boxes do not have the same values 251 * in their Processor object as the ProcId values in the MADT. 252 */ 253 acpi_id = obj->Processor.ProcId; 254 AcpiOsFree(obj); 255 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0) 256 return (ENXIO); 257 258 /* 259 * Check if we already probed this processor. We scan the bus twice 260 * so it's possible we've already seen this one. 261 */ 262 if (cpu_softc[cpu_id] != NULL) 263 return (ENXIO); 264 265 /* Mark this processor as in-use and save our derived id for attach. */ 266 cpu_softc[cpu_id] = (void *)1; 267 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 268 device_set_desc(dev, "ACPI CPU"); 269 270 return (0); 271 } 272 273 static int 274 acpi_cpu_attach(device_t dev) 275 { 276 ACPI_BUFFER buf; 277 ACPI_OBJECT arg[4], *obj; 278 ACPI_OBJECT_LIST arglist; 279 struct pcpu *pcpu_data; 280 struct acpi_cpu_softc *sc; 281 struct acpi_softc *acpi_sc; 282 ACPI_STATUS status; 283 u_int features; 284 int cpu_id, drv_count, i; 285 driver_t **drivers; 286 uint32_t cap_set[3]; 287 288 /* UUID needed by _OSC evaluation */ 289 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 290 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 291 0x58, 0x71, 0x39, 0x53 }; 292 293 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 294 295 sc = device_get_softc(dev); 296 sc->cpu_dev = dev; 297 sc->cpu_handle = acpi_get_handle(dev); 298 cpu_id = (int)(intptr_t)acpi_get_private(dev); 299 cpu_softc[cpu_id] = sc; 300 pcpu_data = pcpu_find(cpu_id); 301 pcpu_data->pc_device = dev; 302 sc->cpu_pcpu = pcpu_data; 303 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 304 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 305 306 buf.Pointer = NULL; 307 buf.Length = ACPI_ALLOCATE_BUFFER; 308 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 309 if (ACPI_FAILURE(status)) { 310 device_printf(dev, "attach failed to get Processor obj - %s\n", 311 AcpiFormatException(status)); 312 return (ENXIO); 313 } 314 obj = (ACPI_OBJECT *)buf.Pointer; 315 sc->cpu_p_blk = obj->Processor.PblkAddress; 316 sc->cpu_p_blk_len = obj->Processor.PblkLength; 317 sc->cpu_acpi_id = obj->Processor.ProcId; 318 AcpiOsFree(obj); 319 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 320 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 321 322 /* 323 * If this is the first cpu we attach, create and initialize the generic 324 * resources that will be used by all acpi cpu devices. 325 */ 326 if (device_get_unit(dev) == 0) { 327 /* Assume we won't be using generic Cx mode by default */ 328 cpu_cx_generic = FALSE; 329 330 /* Install hw.acpi.cpu sysctl tree */ 331 acpi_sc = acpi_device_get_parent_softc(dev); 332 sysctl_ctx_init(&cpu_sysctl_ctx); 333 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 334 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 335 CTLFLAG_RD, 0, "node for CPU children"); 336 337 /* Queue post cpu-probing task handler */ 338 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 339 } 340 341 /* 342 * Before calling any CPU methods, collect child driver feature hints 343 * and notify ACPI of them. We support unified SMP power control 344 * so advertise this ourselves. Note this is not the same as independent 345 * SMP control where each CPU can have different settings. 346 */ 347 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3; 348 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 349 for (i = 0; i < drv_count; i++) { 350 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 351 sc->cpu_features |= features; 352 } 353 free(drivers, M_TEMP); 354 } 355 356 /* 357 * CPU capabilities are specified in 358 * Intel Processor Vendor-Specific ACPI Interface Specification. 359 */ 360 if (sc->cpu_features) { 361 arglist.Pointer = arg; 362 arglist.Count = 4; 363 arg[0].Type = ACPI_TYPE_BUFFER; 364 arg[0].Buffer.Length = sizeof(cpu_oscuuid); 365 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */ 366 arg[1].Type = ACPI_TYPE_INTEGER; 367 arg[1].Integer.Value = 1; /* revision */ 368 arg[2].Type = ACPI_TYPE_INTEGER; 369 arg[2].Integer.Value = 1; /* count */ 370 arg[3].Type = ACPI_TYPE_BUFFER; 371 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */ 372 arg[3].Buffer.Pointer = (uint8_t *)cap_set; 373 cap_set[0] = 0; /* status */ 374 cap_set[1] = sc->cpu_features; 375 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL); 376 if (ACPI_SUCCESS(status)) { 377 if (cap_set[0] != 0) 378 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 379 } 380 else { 381 arglist.Pointer = arg; 382 arglist.Count = 1; 383 arg[0].Type = ACPI_TYPE_BUFFER; 384 arg[0].Buffer.Length = sizeof(cap_set); 385 arg[0].Buffer.Pointer = (uint8_t *)cap_set; 386 cap_set[0] = 1; /* revision */ 387 cap_set[1] = 1; /* number of capabilities integers */ 388 cap_set[2] = sc->cpu_features; 389 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 390 } 391 } 392 393 /* Probe for Cx state support. */ 394 acpi_cpu_cx_probe(sc); 395 396 return (0); 397 } 398 399 static void 400 acpi_cpu_postattach(void *unused __unused) 401 { 402 device_t *devices; 403 int err; 404 int i, n; 405 406 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 407 if (err != 0) { 408 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 409 return; 410 } 411 for (i = 0; i < n; i++) 412 bus_generic_probe(devices[i]); 413 for (i = 0; i < n; i++) 414 bus_generic_attach(devices[i]); 415 free(devices, M_TEMP); 416 } 417 418 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 419 acpi_cpu_postattach, NULL); 420 421 /* 422 * Disable any entry to the idle function during suspend and re-enable it 423 * during resume. 424 */ 425 static int 426 acpi_cpu_suspend(device_t dev) 427 { 428 int error; 429 430 error = bus_generic_suspend(dev); 431 if (error) 432 return (error); 433 cpu_disable_idle = TRUE; 434 return (0); 435 } 436 437 static int 438 acpi_cpu_resume(device_t dev) 439 { 440 441 cpu_disable_idle = FALSE; 442 return (bus_generic_resume(dev)); 443 } 444 445 /* 446 * Find the processor associated with a given ACPI ID. By default, 447 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a 448 * processor. Some systems have inconsistent ASL and MADT however. 449 * For these systems the cpu_unordered tunable can be set in which 450 * case we assume that Processor objects are listed in the same order 451 * in both the MADT and ASL. 452 */ 453 static int 454 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id) 455 { 456 struct pcpu *pc; 457 uint32_t i, idx; 458 459 KASSERT(acpi_id != NULL, ("Null acpi_id")); 460 KASSERT(cpu_id != NULL, ("Null cpu_id")); 461 idx = device_get_unit(dev); 462 463 /* 464 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 465 * UP box) use the ACPI ID from the first processor we find. 466 */ 467 if (idx == 0 && mp_ncpus == 1) { 468 pc = pcpu_find(0); 469 if (pc->pc_acpi_id == 0xffffffff) 470 pc->pc_acpi_id = *acpi_id; 471 *cpu_id = 0; 472 return (0); 473 } 474 475 CPU_FOREACH(i) { 476 pc = pcpu_find(i); 477 KASSERT(pc != NULL, ("no pcpu data for %d", i)); 478 if (cpu_unordered) { 479 if (idx-- == 0) { 480 /* 481 * If pc_acpi_id doesn't match the ACPI ID from the 482 * ASL, prefer the MADT-derived value. 483 */ 484 if (pc->pc_acpi_id != *acpi_id) 485 *acpi_id = pc->pc_acpi_id; 486 *cpu_id = pc->pc_cpuid; 487 return (0); 488 } 489 } else { 490 if (pc->pc_acpi_id == *acpi_id) { 491 if (bootverbose) 492 device_printf(dev, 493 "Processor %s (ACPI ID %u) -> APIC ID %d\n", 494 acpi_name(acpi_get_handle(dev)), *acpi_id, 495 pc->pc_cpuid); 496 *cpu_id = pc->pc_cpuid; 497 return (0); 498 } 499 } 500 } 501 502 if (bootverbose) 503 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 504 acpi_name(acpi_get_handle(dev)), *acpi_id); 505 506 return (ESRCH); 507 } 508 509 static struct resource_list * 510 acpi_cpu_get_rlist(device_t dev, device_t child) 511 { 512 struct acpi_cpu_device *ad; 513 514 ad = device_get_ivars(child); 515 if (ad == NULL) 516 return (NULL); 517 return (&ad->ad_rl); 518 } 519 520 static device_t 521 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 522 { 523 struct acpi_cpu_device *ad; 524 device_t child; 525 526 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 527 return (NULL); 528 529 resource_list_init(&ad->ad_rl); 530 531 child = device_add_child_ordered(dev, order, name, unit); 532 if (child != NULL) 533 device_set_ivars(child, ad); 534 else 535 free(ad, M_TEMP); 536 return (child); 537 } 538 539 static int 540 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 541 { 542 struct acpi_cpu_softc *sc; 543 544 sc = device_get_softc(dev); 545 switch (index) { 546 case ACPI_IVAR_HANDLE: 547 *result = (uintptr_t)sc->cpu_handle; 548 break; 549 case CPU_IVAR_PCPU: 550 *result = (uintptr_t)sc->cpu_pcpu; 551 break; 552 #if defined(__amd64__) || defined(__i386__) 553 case CPU_IVAR_NOMINAL_MHZ: 554 if (tsc_is_invariant) { 555 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 556 break; 557 } 558 /* FALLTHROUGH */ 559 #endif 560 default: 561 return (ENOENT); 562 } 563 return (0); 564 } 565 566 static int 567 acpi_cpu_shutdown(device_t dev) 568 { 569 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 570 571 /* Allow children to shutdown first. */ 572 bus_generic_shutdown(dev); 573 574 /* 575 * Disable any entry to the idle function. There is a small race where 576 * an idle thread have passed this check but not gone to sleep. This 577 * is ok since device_shutdown() does not free the softc, otherwise 578 * we'd have to be sure all threads were evicted before returning. 579 */ 580 cpu_disable_idle = TRUE; 581 582 return_VALUE (0); 583 } 584 585 static void 586 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 587 { 588 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 589 590 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 591 sc->cpu_prev_sleep = 1000000; 592 sc->cpu_cx_lowest = 0; 593 sc->cpu_cx_lowest_lim = 0; 594 595 /* 596 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 597 * any, we'll revert to generic FADT/P_BLK Cx control method which will 598 * be handled by acpi_cpu_startup. We need to defer to after having 599 * probed all the cpus in the system before probing for generic Cx 600 * states as we may already have found cpus with valid _CST packages 601 */ 602 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 603 /* 604 * We were unable to find a _CST package for this cpu or there 605 * was an error parsing it. Switch back to generic mode. 606 */ 607 cpu_cx_generic = TRUE; 608 if (bootverbose) 609 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 610 } 611 612 /* 613 * TODO: _CSD Package should be checked here. 614 */ 615 } 616 617 static void 618 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 619 { 620 ACPI_GENERIC_ADDRESS gas; 621 struct acpi_cx *cx_ptr; 622 623 sc->cpu_cx_count = 0; 624 cx_ptr = sc->cpu_cx_states; 625 626 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 627 sc->cpu_prev_sleep = 1000000; 628 629 /* C1 has been required since just after ACPI 1.0 */ 630 cx_ptr->type = ACPI_STATE_C1; 631 cx_ptr->trans_lat = 0; 632 cx_ptr++; 633 sc->cpu_non_c3 = sc->cpu_cx_count; 634 sc->cpu_cx_count++; 635 636 /* 637 * The spec says P_BLK must be 6 bytes long. However, some systems 638 * use it to indicate a fractional set of features present so we 639 * take 5 as C2. Some may also have a value of 7 to indicate 640 * another C3 but most use _CST for this (as required) and having 641 * "only" C1-C3 is not a hardship. 642 */ 643 if (sc->cpu_p_blk_len < 5) 644 return; 645 646 /* Validate and allocate resources for C2 (P_LVL2). */ 647 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 648 gas.BitWidth = 8; 649 if (AcpiGbl_FADT.C2Latency <= 100) { 650 gas.Address = sc->cpu_p_blk + 4; 651 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, 652 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 653 if (cx_ptr->p_lvlx != NULL) { 654 sc->cpu_rid++; 655 cx_ptr->type = ACPI_STATE_C2; 656 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 657 cx_ptr++; 658 sc->cpu_non_c3 = sc->cpu_cx_count; 659 sc->cpu_cx_count++; 660 } 661 } 662 if (sc->cpu_p_blk_len < 6) 663 return; 664 665 /* Validate and allocate resources for C3 (P_LVL3). */ 666 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 667 gas.Address = sc->cpu_p_blk + 5; 668 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas, 669 &cx_ptr->p_lvlx, RF_SHAREABLE); 670 if (cx_ptr->p_lvlx != NULL) { 671 sc->cpu_rid++; 672 cx_ptr->type = ACPI_STATE_C3; 673 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 674 cx_ptr++; 675 sc->cpu_cx_count++; 676 cpu_can_deep_sleep = 1; 677 } 678 } 679 } 680 681 /* 682 * Parse a _CST package and set up its Cx states. Since the _CST object 683 * can change dynamically, our notify handler may call this function 684 * to clean up and probe the new _CST package. 685 */ 686 static int 687 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 688 { 689 struct acpi_cx *cx_ptr; 690 ACPI_STATUS status; 691 ACPI_BUFFER buf; 692 ACPI_OBJECT *top; 693 ACPI_OBJECT *pkg; 694 uint32_t count; 695 int i; 696 697 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 698 699 buf.Pointer = NULL; 700 buf.Length = ACPI_ALLOCATE_BUFFER; 701 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 702 if (ACPI_FAILURE(status)) 703 return (ENXIO); 704 705 /* _CST is a package with a count and at least one Cx package. */ 706 top = (ACPI_OBJECT *)buf.Pointer; 707 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 708 device_printf(sc->cpu_dev, "invalid _CST package\n"); 709 AcpiOsFree(buf.Pointer); 710 return (ENXIO); 711 } 712 if (count != top->Package.Count - 1) { 713 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 714 count, top->Package.Count - 1); 715 count = top->Package.Count - 1; 716 } 717 if (count > MAX_CX_STATES) { 718 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 719 count = MAX_CX_STATES; 720 } 721 722 sc->cpu_non_c3 = 0; 723 sc->cpu_cx_count = 0; 724 cx_ptr = sc->cpu_cx_states; 725 726 /* 727 * C1 has been required since just after ACPI 1.0. 728 * Reserve the first slot for it. 729 */ 730 cx_ptr->type = ACPI_STATE_C0; 731 cx_ptr++; 732 sc->cpu_cx_count++; 733 734 /* Set up all valid states. */ 735 for (i = 0; i < count; i++) { 736 pkg = &top->Package.Elements[i + 1]; 737 if (!ACPI_PKG_VALID(pkg, 4) || 738 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 739 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 740 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 741 742 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 743 continue; 744 } 745 746 /* Validate the state to see if we should use it. */ 747 switch (cx_ptr->type) { 748 case ACPI_STATE_C1: 749 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 750 /* This is the first C1 state. Use the reserved slot. */ 751 sc->cpu_cx_states[0] = *cx_ptr; 752 } else { 753 sc->cpu_non_c3 = sc->cpu_cx_count; 754 cx_ptr++; 755 sc->cpu_cx_count++; 756 } 757 continue; 758 case ACPI_STATE_C2: 759 sc->cpu_non_c3 = sc->cpu_cx_count; 760 break; 761 case ACPI_STATE_C3: 762 default: 763 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 764 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 765 "acpi_cpu%d: C3[%d] not available.\n", 766 device_get_unit(sc->cpu_dev), i)); 767 continue; 768 } else 769 cpu_can_deep_sleep = 1; 770 break; 771 } 772 773 #ifdef notyet 774 /* Free up any previous register. */ 775 if (cx_ptr->p_lvlx != NULL) { 776 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx); 777 cx_ptr->p_lvlx = NULL; 778 } 779 #endif 780 781 /* Allocate the control register for C2 or C3. */ 782 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &sc->cpu_rid, 783 &cx_ptr->p_lvlx, RF_SHAREABLE); 784 if (cx_ptr->p_lvlx) { 785 sc->cpu_rid++; 786 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 787 "acpi_cpu%d: Got C%d - %d latency\n", 788 device_get_unit(sc->cpu_dev), cx_ptr->type, 789 cx_ptr->trans_lat)); 790 cx_ptr++; 791 sc->cpu_cx_count++; 792 } 793 } 794 AcpiOsFree(buf.Pointer); 795 796 /* If C1 state was not found, we need one now. */ 797 cx_ptr = sc->cpu_cx_states; 798 if (cx_ptr->type == ACPI_STATE_C0) { 799 cx_ptr->type = ACPI_STATE_C1; 800 cx_ptr->trans_lat = 0; 801 } 802 803 return (0); 804 } 805 806 /* 807 * Call this *after* all CPUs have been attached. 808 */ 809 static void 810 acpi_cpu_startup(void *arg) 811 { 812 struct acpi_cpu_softc *sc; 813 int i; 814 815 /* Get set of CPU devices */ 816 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 817 818 /* 819 * Setup any quirks that might necessary now that we have probed 820 * all the CPUs 821 */ 822 acpi_cpu_quirks(); 823 824 if (cpu_cx_generic) { 825 /* 826 * We are using generic Cx mode, probe for available Cx states 827 * for all processors. 828 */ 829 for (i = 0; i < cpu_ndevices; i++) { 830 sc = device_get_softc(cpu_devices[i]); 831 acpi_cpu_generic_cx_probe(sc); 832 } 833 } else { 834 /* 835 * We are using _CST mode, remove C3 state if necessary. 836 * As we now know for sure that we will be using _CST mode 837 * install our notify handler. 838 */ 839 for (i = 0; i < cpu_ndevices; i++) { 840 sc = device_get_softc(cpu_devices[i]); 841 if (cpu_quirks & CPU_QUIRK_NO_C3) { 842 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 843 } 844 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 845 acpi_cpu_notify, sc); 846 } 847 } 848 849 /* Perform Cx final initialization. */ 850 for (i = 0; i < cpu_ndevices; i++) { 851 sc = device_get_softc(cpu_devices[i]); 852 acpi_cpu_startup_cx(sc); 853 } 854 855 /* Add a sysctl handler to handle global Cx lowest setting */ 856 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 857 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 858 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 859 "Global lowest Cx sleep state to use"); 860 861 /* Take over idling from cpu_idle_default(). */ 862 cpu_cx_lowest_lim = 0; 863 cpu_disable_idle = FALSE; 864 cpu_idle_hook = acpi_cpu_idle; 865 } 866 867 static void 868 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 869 { 870 struct sbuf sb; 871 int i; 872 873 /* 874 * Set up the list of Cx states 875 */ 876 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 877 SBUF_FIXEDLEN); 878 for (i = 0; i < sc->cpu_cx_count; i++) 879 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 880 sc->cpu_cx_states[i].trans_lat); 881 sbuf_trim(&sb); 882 sbuf_finish(&sb); 883 } 884 885 static void 886 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 887 { 888 acpi_cpu_cx_list(sc); 889 890 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 891 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 892 OID_AUTO, "cx_supported", CTLFLAG_RD, 893 sc->cpu_cx_supported, 0, 894 "Cx/microsecond values for supported Cx states"); 895 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 896 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 897 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 898 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 899 "lowest Cx sleep state to use"); 900 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 901 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 902 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 903 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 904 "percent usage for each Cx state"); 905 906 /* Signal platform that we can handle _CST notification. */ 907 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 908 ACPI_LOCK(acpi); 909 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 910 ACPI_UNLOCK(acpi); 911 } 912 } 913 914 /* 915 * Idle the CPU in the lowest state possible. This function is called with 916 * interrupts disabled. Note that once it re-enables interrupts, a task 917 * switch can occur so do not access shared data (i.e. the softc) after 918 * interrupts are re-enabled. 919 */ 920 static void 921 acpi_cpu_idle() 922 { 923 struct acpi_cpu_softc *sc; 924 struct acpi_cx *cx_next; 925 uint64_t cputicks; 926 uint32_t start_time, end_time; 927 int bm_active, cx_next_idx, i; 928 929 /* If disabled, return immediately. */ 930 if (cpu_disable_idle) { 931 ACPI_ENABLE_IRQS(); 932 return; 933 } 934 935 /* 936 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 937 * since there is no ACPI processor object for this CPU. This occurs 938 * for logical CPUs in the HTT case. 939 */ 940 sc = cpu_softc[PCPU_GET(cpuid)]; 941 if (sc == NULL) { 942 acpi_cpu_c1(); 943 return; 944 } 945 946 /* Find the lowest state that has small enough latency. */ 947 cx_next_idx = 0; 948 if (cpu_disable_deep_sleep) 949 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 950 else 951 i = sc->cpu_cx_lowest; 952 for (; i >= 0; i--) { 953 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) { 954 cx_next_idx = i; 955 break; 956 } 957 } 958 959 /* 960 * Check for bus master activity. If there was activity, clear 961 * the bit and use the lowest non-C3 state. Note that the USB 962 * driver polling for new devices keeps this bit set all the 963 * time if USB is loaded. 964 */ 965 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 966 cx_next_idx > sc->cpu_non_c3) { 967 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 968 if (bm_active != 0) { 969 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 970 cx_next_idx = sc->cpu_non_c3; 971 } 972 } 973 974 /* Select the next state and update statistics. */ 975 cx_next = &sc->cpu_cx_states[cx_next_idx]; 976 sc->cpu_cx_stats[cx_next_idx]++; 977 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 978 979 /* 980 * Execute HLT (or equivalent) and wait for an interrupt. We can't 981 * precisely calculate the time spent in C1 since the place we wake up 982 * is an ISR. Assume we slept no more then half of quantum, unless 983 * we are called inside critical section, delaying context switch. 984 */ 985 if (cx_next->type == ACPI_STATE_C1) { 986 cputicks = cpu_ticks(); 987 acpi_cpu_c1(); 988 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 989 if (curthread->td_critnest == 0) 990 end_time = min(end_time, 500000 / hz); 991 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 992 return; 993 } 994 995 /* 996 * For C3, disable bus master arbitration and enable bus master wake 997 * if BM control is available, otherwise flush the CPU cache. 998 */ 999 if (cx_next->type == ACPI_STATE_C3) { 1000 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1001 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1002 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1003 } else 1004 ACPI_FLUSH_CPU_CACHE(); 1005 } 1006 1007 /* 1008 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1009 * Use the ACPI timer for measuring sleep time. Since we need to 1010 * get the time very close to the CPU start/stop clock logic, this 1011 * is the only reliable time source. 1012 */ 1013 if (cx_next->type == ACPI_STATE_C3) { 1014 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 1015 cputicks = 0; 1016 } else { 1017 start_time = 0; 1018 cputicks = cpu_ticks(); 1019 } 1020 CPU_GET_REG(cx_next->p_lvlx, 1); 1021 1022 /* 1023 * Read the end time twice. Since it may take an arbitrary time 1024 * to enter the idle state, the first read may be executed before 1025 * the processor has stopped. Doing it again provides enough 1026 * margin that we are certain to have a correct value. 1027 */ 1028 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1029 if (cx_next->type == ACPI_STATE_C3) { 1030 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1031 end_time = acpi_TimerDelta(end_time, start_time); 1032 } else 1033 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1034 1035 /* Enable bus master arbitration and disable bus master wakeup. */ 1036 if (cx_next->type == ACPI_STATE_C3 && 1037 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1038 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1039 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1040 } 1041 ACPI_ENABLE_IRQS(); 1042 1043 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1044 } 1045 1046 /* 1047 * Re-evaluate the _CST object when we are notified that it changed. 1048 * 1049 * XXX Re-evaluation disabled until locking is done. 1050 */ 1051 static void 1052 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1053 { 1054 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1055 1056 if (notify != ACPI_NOTIFY_CX_STATES) 1057 return; 1058 1059 /* Update the list of Cx states. */ 1060 acpi_cpu_cx_cst(sc); 1061 acpi_cpu_cx_list(sc); 1062 1063 ACPI_SERIAL_BEGIN(cpu); 1064 acpi_cpu_set_cx_lowest(sc); 1065 ACPI_SERIAL_END(cpu); 1066 1067 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1068 } 1069 1070 static int 1071 acpi_cpu_quirks(void) 1072 { 1073 device_t acpi_dev; 1074 uint32_t val; 1075 1076 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1077 1078 /* 1079 * Bus mastering arbitration control is needed to keep caches coherent 1080 * while sleeping in C3. If it's not present but a working flush cache 1081 * instruction is present, flush the caches before entering C3 instead. 1082 * Otherwise, just disable C3 completely. 1083 */ 1084 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1085 AcpiGbl_FADT.Pm2ControlLength == 0) { 1086 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1087 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1088 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1089 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1090 "acpi_cpu: no BM control, using flush cache method\n")); 1091 } else { 1092 cpu_quirks |= CPU_QUIRK_NO_C3; 1093 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1094 "acpi_cpu: no BM control, C3 not available\n")); 1095 } 1096 } 1097 1098 /* 1099 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1100 * the expensive flush cache instruction. 1101 */ 1102 if (cpu_cx_generic && mp_ncpus > 1) { 1103 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1104 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1105 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1106 } 1107 1108 /* Look for various quirks of the PIIX4 part. */ 1109 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1110 if (acpi_dev != NULL) { 1111 switch (pci_get_revid(acpi_dev)) { 1112 /* 1113 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1114 * do not report the BMIDE status to the BM status register and 1115 * others have a livelock bug if Type-F DMA is enabled. Linux 1116 * works around the BMIDE bug by reading the BM status directly 1117 * but we take the simpler approach of disabling C3 for these 1118 * parts. 1119 * 1120 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1121 * Livelock") from the January 2002 PIIX4 specification update. 1122 * Applies to all PIIX4 models. 1123 * 1124 * Also, make sure that all interrupts cause a "Stop Break" 1125 * event to exit from C2 state. 1126 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1127 * should be set to zero, otherwise it causes C2 to short-sleep. 1128 * PIIX4 doesn't properly support C3 and bus master activity 1129 * need not break out of C2. 1130 */ 1131 case PCI_REVISION_A_STEP: 1132 case PCI_REVISION_B_STEP: 1133 case PCI_REVISION_4E: 1134 case PCI_REVISION_4M: 1135 cpu_quirks |= CPU_QUIRK_NO_C3; 1136 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1137 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1138 1139 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1140 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1141 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1142 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1143 val |= PIIX4_STOP_BREAK_MASK; 1144 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1145 } 1146 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1147 if (val) { 1148 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1149 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1150 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1151 } 1152 break; 1153 default: 1154 break; 1155 } 1156 } 1157 1158 return (0); 1159 } 1160 1161 static int 1162 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1163 { 1164 struct acpi_cpu_softc *sc; 1165 struct sbuf sb; 1166 char buf[128]; 1167 int i; 1168 uintmax_t fract, sum, whole; 1169 1170 sc = (struct acpi_cpu_softc *) arg1; 1171 sum = 0; 1172 for (i = 0; i < sc->cpu_cx_count; i++) 1173 sum += sc->cpu_cx_stats[i]; 1174 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1175 for (i = 0; i < sc->cpu_cx_count; i++) { 1176 if (sum > 0) { 1177 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1178 fract = (whole % sum) * 100; 1179 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1180 (u_int)(fract / sum)); 1181 } else 1182 sbuf_printf(&sb, "0.00%% "); 1183 } 1184 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1185 sbuf_trim(&sb); 1186 sbuf_finish(&sb); 1187 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1188 sbuf_delete(&sb); 1189 1190 return (0); 1191 } 1192 1193 static int 1194 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1195 { 1196 int i; 1197 1198 ACPI_SERIAL_ASSERT(cpu); 1199 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1200 1201 /* If not disabling, cache the new lowest non-C3 state. */ 1202 sc->cpu_non_c3 = 0; 1203 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1204 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1205 sc->cpu_non_c3 = i; 1206 break; 1207 } 1208 } 1209 1210 /* Reset the statistics counters. */ 1211 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1212 return (0); 1213 } 1214 1215 static int 1216 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1217 { 1218 struct acpi_cpu_softc *sc; 1219 char state[8]; 1220 int val, error; 1221 1222 sc = (struct acpi_cpu_softc *) arg1; 1223 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1224 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1225 if (error != 0 || req->newptr == NULL) 1226 return (error); 1227 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1228 return (EINVAL); 1229 if (strcasecmp(state, "Cmax") == 0) 1230 val = MAX_CX_STATES; 1231 else { 1232 val = (int) strtol(state + 1, NULL, 10); 1233 if (val < 1 || val > MAX_CX_STATES) 1234 return (EINVAL); 1235 } 1236 1237 ACPI_SERIAL_BEGIN(cpu); 1238 sc->cpu_cx_lowest_lim = val - 1; 1239 acpi_cpu_set_cx_lowest(sc); 1240 ACPI_SERIAL_END(cpu); 1241 1242 return (0); 1243 } 1244 1245 static int 1246 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1247 { 1248 struct acpi_cpu_softc *sc; 1249 char state[8]; 1250 int val, error, i; 1251 1252 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1253 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1254 if (error != 0 || req->newptr == NULL) 1255 return (error); 1256 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1257 return (EINVAL); 1258 if (strcasecmp(state, "Cmax") == 0) 1259 val = MAX_CX_STATES; 1260 else { 1261 val = (int) strtol(state + 1, NULL, 10); 1262 if (val < 1 || val > MAX_CX_STATES) 1263 return (EINVAL); 1264 } 1265 1266 /* Update the new lowest useable Cx state for all CPUs. */ 1267 ACPI_SERIAL_BEGIN(cpu); 1268 cpu_cx_lowest_lim = val - 1; 1269 for (i = 0; i < cpu_ndevices; i++) { 1270 sc = device_get_softc(cpu_devices[i]); 1271 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1272 acpi_cpu_set_cx_lowest(sc); 1273 } 1274 ACPI_SERIAL_END(cpu); 1275 1276 return (0); 1277 } 1278