1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/power.h> 40 #include <sys/proc.h> 41 #include <sys/sched.h> 42 #include <sys/sbuf.h> 43 #include <sys/smp.h> 44 45 #include <dev/pci/pcivar.h> 46 #include <machine/atomic.h> 47 #include <machine/bus.h> 48 #if defined(__amd64__) || defined(__i386__) 49 #include <machine/clock.h> 50 #endif 51 #include <sys/rman.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 58 /* 59 * Support for ACPI Processor devices, including C[1-3] sleep states. 60 */ 61 62 /* Hooks for the ACPI CA debugging infrastructure */ 63 #define _COMPONENT ACPI_PROCESSOR 64 ACPI_MODULE_NAME("PROCESSOR") 65 66 struct acpi_cx { 67 struct resource *p_lvlx; /* Register to read to enter state. */ 68 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 69 uint32_t trans_lat; /* Transition latency (usec). */ 70 uint32_t power; /* Power consumed (mW). */ 71 int res_type; /* Resource type for p_lvlx. */ 72 int res_rid; /* Resource ID for p_lvlx. */ 73 }; 74 #define MAX_CX_STATES 8 75 76 struct acpi_cpu_softc { 77 device_t cpu_dev; 78 ACPI_HANDLE cpu_handle; 79 struct pcpu *cpu_pcpu; 80 uint32_t cpu_acpi_id; /* ACPI processor id */ 81 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 82 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 83 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 84 int cpu_cx_count; /* Number of valid Cx states. */ 85 int cpu_prev_sleep;/* Last idle sleep duration. */ 86 int cpu_features; /* Child driver supported features. */ 87 /* Runtime state. */ 88 int cpu_non_c3; /* Index of lowest non-C3 state. */ 89 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 90 /* Values for sysctl. */ 91 struct sysctl_ctx_list cpu_sysctl_ctx; 92 struct sysctl_oid *cpu_sysctl_tree; 93 int cpu_cx_lowest; 94 int cpu_cx_lowest_lim; 95 int cpu_disable_idle; /* Disable entry to idle function */ 96 char cpu_cx_supported[64]; 97 }; 98 99 struct acpi_cpu_device { 100 struct resource_list ad_rl; 101 }; 102 103 #define CPU_GET_REG(reg, width) \ 104 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 105 rman_get_bushandle((reg)), 0)) 106 #define CPU_SET_REG(reg, width, val) \ 107 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 108 rman_get_bushandle((reg)), 0, (val))) 109 110 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 111 112 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 113 114 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 115 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 116 117 #define PCI_VENDOR_INTEL 0x8086 118 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 119 #define PCI_REVISION_A_STEP 0 120 #define PCI_REVISION_B_STEP 1 121 #define PCI_REVISION_4E 2 122 #define PCI_REVISION_4M 3 123 #define PIIX4_DEVACTB_REG 0x58 124 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 125 #define PIIX4_BRLD_EN_IRQ (1<<1) 126 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 127 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 128 #define PIIX4_PCNTRL_BST_EN (1<<10) 129 130 /* Allow users to ignore processor orders in MADT. */ 131 static int cpu_unordered; 132 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN, 133 &cpu_unordered, 0, 134 "Do not use the MADT to match ACPI Processor objects to CPUs."); 135 136 /* Knob to disable acpi_cpu devices */ 137 bool acpi_cpu_disabled = false; 138 139 /* Platform hardware resource information. */ 140 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 141 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 142 static int cpu_quirks; /* Indicate any hardware bugs. */ 143 144 /* Values for sysctl. */ 145 static struct sysctl_ctx_list cpu_sysctl_ctx; 146 static struct sysctl_oid *cpu_sysctl_tree; 147 static int cpu_cx_generic; 148 static int cpu_cx_lowest_lim; 149 150 static device_t *cpu_devices; 151 static int cpu_ndevices; 152 static struct acpi_cpu_softc **cpu_softc; 153 ACPI_SERIAL_DECL(cpu, "ACPI CPU"); 154 155 static int acpi_cpu_probe(device_t dev); 156 static int acpi_cpu_attach(device_t dev); 157 static int acpi_cpu_suspend(device_t dev); 158 static int acpi_cpu_resume(device_t dev); 159 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, 160 uint32_t *cpu_id); 161 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child); 162 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name, 163 int unit); 164 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index, 165 uintptr_t *result); 166 static int acpi_cpu_shutdown(device_t dev); 167 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 168 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 169 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 170 static void acpi_cpu_startup(void *arg); 171 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 172 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 173 static void acpi_cpu_idle(sbintime_t sbt); 174 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context); 175 static int acpi_cpu_quirks(void); 176 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 177 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS); 178 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc); 179 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 180 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 181 182 static device_method_t acpi_cpu_methods[] = { 183 /* Device interface */ 184 DEVMETHOD(device_probe, acpi_cpu_probe), 185 DEVMETHOD(device_attach, acpi_cpu_attach), 186 DEVMETHOD(device_detach, bus_generic_detach), 187 DEVMETHOD(device_shutdown, acpi_cpu_shutdown), 188 DEVMETHOD(device_suspend, acpi_cpu_suspend), 189 DEVMETHOD(device_resume, acpi_cpu_resume), 190 191 /* Bus interface */ 192 DEVMETHOD(bus_add_child, acpi_cpu_add_child), 193 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar), 194 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist), 195 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 196 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 197 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 198 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 199 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 200 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 201 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 202 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 203 204 DEVMETHOD_END 205 }; 206 207 static driver_t acpi_cpu_driver = { 208 "cpu", 209 acpi_cpu_methods, 210 sizeof(struct acpi_cpu_softc), 211 }; 212 213 static devclass_t acpi_cpu_devclass; 214 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0); 215 MODULE_DEPEND(cpu, acpi, 1, 1, 1); 216 217 static int 218 acpi_cpu_probe(device_t dev) 219 { 220 int acpi_id, cpu_id; 221 ACPI_BUFFER buf; 222 ACPI_HANDLE handle; 223 ACPI_OBJECT *obj; 224 ACPI_STATUS status; 225 226 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR || 227 acpi_cpu_disabled) 228 return (ENXIO); 229 230 handle = acpi_get_handle(dev); 231 if (cpu_softc == NULL) 232 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) * 233 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO); 234 235 /* Get our Processor object. */ 236 buf.Pointer = NULL; 237 buf.Length = ACPI_ALLOCATE_BUFFER; 238 status = AcpiEvaluateObject(handle, NULL, NULL, &buf); 239 if (ACPI_FAILURE(status)) { 240 device_printf(dev, "probe failed to get Processor obj - %s\n", 241 AcpiFormatException(status)); 242 return (ENXIO); 243 } 244 obj = (ACPI_OBJECT *)buf.Pointer; 245 if (obj->Type != ACPI_TYPE_PROCESSOR) { 246 device_printf(dev, "Processor object has bad type %d\n", obj->Type); 247 AcpiOsFree(obj); 248 return (ENXIO); 249 } 250 251 /* 252 * Find the processor associated with our unit. We could use the 253 * ProcId as a key, however, some boxes do not have the same values 254 * in their Processor object as the ProcId values in the MADT. 255 */ 256 acpi_id = obj->Processor.ProcId; 257 AcpiOsFree(obj); 258 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0) 259 return (ENXIO); 260 261 /* 262 * Check if we already probed this processor. We scan the bus twice 263 * so it's possible we've already seen this one. 264 */ 265 if (cpu_softc[cpu_id] != NULL) 266 return (ENXIO); 267 268 /* Mark this processor as in-use and save our derived id for attach. */ 269 cpu_softc[cpu_id] = (void *)1; 270 acpi_set_private(dev, (void*)(intptr_t)cpu_id); 271 device_set_desc(dev, "ACPI CPU"); 272 273 return (0); 274 } 275 276 static int 277 acpi_cpu_attach(device_t dev) 278 { 279 ACPI_BUFFER buf; 280 ACPI_OBJECT arg[4], *obj; 281 ACPI_OBJECT_LIST arglist; 282 struct pcpu *pcpu_data; 283 struct acpi_cpu_softc *sc; 284 struct acpi_softc *acpi_sc; 285 ACPI_STATUS status; 286 u_int features; 287 int cpu_id, drv_count, i; 288 driver_t **drivers; 289 uint32_t cap_set[3]; 290 291 /* UUID needed by _OSC evaluation */ 292 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 293 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70, 294 0x58, 0x71, 0x39, 0x53 }; 295 296 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 297 298 sc = device_get_softc(dev); 299 sc->cpu_dev = dev; 300 sc->cpu_handle = acpi_get_handle(dev); 301 cpu_id = (int)(intptr_t)acpi_get_private(dev); 302 cpu_softc[cpu_id] = sc; 303 pcpu_data = pcpu_find(cpu_id); 304 pcpu_data->pc_device = dev; 305 sc->cpu_pcpu = pcpu_data; 306 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 307 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 308 309 buf.Pointer = NULL; 310 buf.Length = ACPI_ALLOCATE_BUFFER; 311 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 312 if (ACPI_FAILURE(status)) { 313 device_printf(dev, "attach failed to get Processor obj - %s\n", 314 AcpiFormatException(status)); 315 return (ENXIO); 316 } 317 obj = (ACPI_OBJECT *)buf.Pointer; 318 sc->cpu_p_blk = obj->Processor.PblkAddress; 319 sc->cpu_p_blk_len = obj->Processor.PblkLength; 320 sc->cpu_acpi_id = obj->Processor.ProcId; 321 AcpiOsFree(obj); 322 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 323 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 324 325 /* 326 * If this is the first cpu we attach, create and initialize the generic 327 * resources that will be used by all acpi cpu devices. 328 */ 329 if (device_get_unit(dev) == 0) { 330 /* Assume we won't be using generic Cx mode by default */ 331 cpu_cx_generic = FALSE; 332 333 /* Install hw.acpi.cpu sysctl tree */ 334 acpi_sc = acpi_device_get_parent_softc(dev); 335 sysctl_ctx_init(&cpu_sysctl_ctx); 336 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx, 337 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu", 338 CTLFLAG_RD, 0, "node for CPU children"); 339 340 /* Queue post cpu-probing task handler */ 341 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 342 } 343 344 /* 345 * Before calling any CPU methods, collect child driver feature hints 346 * and notify ACPI of them. We support unified SMP power control 347 * so advertise this ourselves. Note this is not the same as independent 348 * SMP control where each CPU can have different settings. 349 */ 350 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3; 351 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) { 352 for (i = 0; i < drv_count; i++) { 353 if (ACPI_GET_FEATURES(drivers[i], &features) == 0) 354 sc->cpu_features |= features; 355 } 356 free(drivers, M_TEMP); 357 } 358 359 /* 360 * CPU capabilities are specified in 361 * Intel Processor Vendor-Specific ACPI Interface Specification. 362 */ 363 if (sc->cpu_features) { 364 arglist.Pointer = arg; 365 arglist.Count = 4; 366 arg[0].Type = ACPI_TYPE_BUFFER; 367 arg[0].Buffer.Length = sizeof(cpu_oscuuid); 368 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */ 369 arg[1].Type = ACPI_TYPE_INTEGER; 370 arg[1].Integer.Value = 1; /* revision */ 371 arg[2].Type = ACPI_TYPE_INTEGER; 372 arg[2].Integer.Value = 1; /* count */ 373 arg[3].Type = ACPI_TYPE_BUFFER; 374 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */ 375 arg[3].Buffer.Pointer = (uint8_t *)cap_set; 376 cap_set[0] = 0; /* status */ 377 cap_set[1] = sc->cpu_features; 378 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL); 379 if (ACPI_SUCCESS(status)) { 380 if (cap_set[0] != 0) 381 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]); 382 } 383 else { 384 arglist.Pointer = arg; 385 arglist.Count = 1; 386 arg[0].Type = ACPI_TYPE_BUFFER; 387 arg[0].Buffer.Length = sizeof(cap_set); 388 arg[0].Buffer.Pointer = (uint8_t *)cap_set; 389 cap_set[0] = 1; /* revision */ 390 cap_set[1] = 1; /* number of capabilities integers */ 391 cap_set[2] = sc->cpu_features; 392 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL); 393 } 394 } 395 396 /* Probe for Cx state support. */ 397 acpi_cpu_cx_probe(sc); 398 399 return (0); 400 } 401 402 static void 403 acpi_cpu_postattach(void *unused __unused) 404 { 405 device_t *devices; 406 int err; 407 int i, n; 408 409 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n); 410 if (err != 0) { 411 printf("devclass_get_devices(acpi_cpu_devclass) failed\n"); 412 return; 413 } 414 for (i = 0; i < n; i++) 415 bus_generic_probe(devices[i]); 416 for (i = 0; i < n; i++) 417 bus_generic_attach(devices[i]); 418 free(devices, M_TEMP); 419 } 420 421 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, 422 acpi_cpu_postattach, NULL); 423 424 static void 425 disable_idle(struct acpi_cpu_softc *sc) 426 { 427 cpuset_t cpuset; 428 429 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset); 430 sc->cpu_disable_idle = TRUE; 431 432 /* 433 * Ensure that the CPU is not in idle state or in acpi_cpu_idle(). 434 * Note that this code depends on the fact that the rendezvous IPI 435 * can not penetrate context where interrupts are disabled and acpi_cpu_idle 436 * is called and executed in such a context with interrupts being re-enabled 437 * right before return. 438 */ 439 smp_rendezvous_cpus(cpuset, smp_no_rendevous_barrier, NULL, 440 smp_no_rendevous_barrier, NULL); 441 } 442 443 static void 444 enable_idle(struct acpi_cpu_softc *sc) 445 { 446 447 sc->cpu_disable_idle = FALSE; 448 } 449 450 static int 451 is_idle_disabled(struct acpi_cpu_softc *sc) 452 { 453 454 return (sc->cpu_disable_idle); 455 } 456 457 /* 458 * Disable any entry to the idle function during suspend and re-enable it 459 * during resume. 460 */ 461 static int 462 acpi_cpu_suspend(device_t dev) 463 { 464 int error; 465 466 error = bus_generic_suspend(dev); 467 if (error) 468 return (error); 469 disable_idle(device_get_softc(dev)); 470 return (0); 471 } 472 473 static int 474 acpi_cpu_resume(device_t dev) 475 { 476 477 enable_idle(device_get_softc(dev)); 478 return (bus_generic_resume(dev)); 479 } 480 481 /* 482 * Find the processor associated with a given ACPI ID. By default, 483 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a 484 * processor. Some systems have inconsistent ASL and MADT however. 485 * For these systems the cpu_unordered tunable can be set in which 486 * case we assume that Processor objects are listed in the same order 487 * in both the MADT and ASL. 488 */ 489 static int 490 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id) 491 { 492 struct pcpu *pc; 493 uint32_t i, idx; 494 495 KASSERT(acpi_id != NULL, ("Null acpi_id")); 496 KASSERT(cpu_id != NULL, ("Null cpu_id")); 497 idx = device_get_unit(dev); 498 499 /* 500 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC 501 * UP box) use the ACPI ID from the first processor we find. 502 */ 503 if (idx == 0 && mp_ncpus == 1) { 504 pc = pcpu_find(0); 505 if (pc->pc_acpi_id == 0xffffffff) 506 pc->pc_acpi_id = *acpi_id; 507 *cpu_id = 0; 508 return (0); 509 } 510 511 CPU_FOREACH(i) { 512 pc = pcpu_find(i); 513 KASSERT(pc != NULL, ("no pcpu data for %d", i)); 514 if (cpu_unordered) { 515 if (idx-- == 0) { 516 /* 517 * If pc_acpi_id doesn't match the ACPI ID from the 518 * ASL, prefer the MADT-derived value. 519 */ 520 if (pc->pc_acpi_id != *acpi_id) 521 *acpi_id = pc->pc_acpi_id; 522 *cpu_id = pc->pc_cpuid; 523 return (0); 524 } 525 } else { 526 if (pc->pc_acpi_id == *acpi_id) { 527 if (bootverbose) 528 device_printf(dev, 529 "Processor %s (ACPI ID %u) -> APIC ID %d\n", 530 acpi_name(acpi_get_handle(dev)), *acpi_id, 531 pc->pc_cpuid); 532 *cpu_id = pc->pc_cpuid; 533 return (0); 534 } 535 } 536 } 537 538 if (bootverbose) 539 printf("ACPI: Processor %s (ACPI ID %u) ignored\n", 540 acpi_name(acpi_get_handle(dev)), *acpi_id); 541 542 return (ESRCH); 543 } 544 545 static struct resource_list * 546 acpi_cpu_get_rlist(device_t dev, device_t child) 547 { 548 struct acpi_cpu_device *ad; 549 550 ad = device_get_ivars(child); 551 if (ad == NULL) 552 return (NULL); 553 return (&ad->ad_rl); 554 } 555 556 static device_t 557 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit) 558 { 559 struct acpi_cpu_device *ad; 560 device_t child; 561 562 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 563 return (NULL); 564 565 resource_list_init(&ad->ad_rl); 566 567 child = device_add_child_ordered(dev, order, name, unit); 568 if (child != NULL) 569 device_set_ivars(child, ad); 570 else 571 free(ad, M_TEMP); 572 return (child); 573 } 574 575 static int 576 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 577 { 578 struct acpi_cpu_softc *sc; 579 580 sc = device_get_softc(dev); 581 switch (index) { 582 case ACPI_IVAR_HANDLE: 583 *result = (uintptr_t)sc->cpu_handle; 584 break; 585 case CPU_IVAR_PCPU: 586 *result = (uintptr_t)sc->cpu_pcpu; 587 break; 588 #if defined(__amd64__) || defined(__i386__) 589 case CPU_IVAR_NOMINAL_MHZ: 590 if (tsc_is_invariant) { 591 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000); 592 break; 593 } 594 /* FALLTHROUGH */ 595 #endif 596 default: 597 return (ENOENT); 598 } 599 return (0); 600 } 601 602 static int 603 acpi_cpu_shutdown(device_t dev) 604 { 605 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 606 607 /* Allow children to shutdown first. */ 608 bus_generic_shutdown(dev); 609 610 /* 611 * Disable any entry to the idle function. 612 */ 613 disable_idle(device_get_softc(dev)); 614 615 /* 616 * CPU devices are not truely detached and remain referenced, 617 * so their resources are not freed. 618 */ 619 620 return_VALUE (0); 621 } 622 623 static void 624 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 625 { 626 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 627 628 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 629 sc->cpu_prev_sleep = 1000000; 630 sc->cpu_cx_lowest = 0; 631 sc->cpu_cx_lowest_lim = 0; 632 633 /* 634 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 635 * any, we'll revert to generic FADT/P_BLK Cx control method which will 636 * be handled by acpi_cpu_startup. We need to defer to after having 637 * probed all the cpus in the system before probing for generic Cx 638 * states as we may already have found cpus with valid _CST packages 639 */ 640 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 641 /* 642 * We were unable to find a _CST package for this cpu or there 643 * was an error parsing it. Switch back to generic mode. 644 */ 645 cpu_cx_generic = TRUE; 646 if (bootverbose) 647 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 648 } 649 650 /* 651 * TODO: _CSD Package should be checked here. 652 */ 653 } 654 655 static void 656 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 657 { 658 ACPI_GENERIC_ADDRESS gas; 659 struct acpi_cx *cx_ptr; 660 661 sc->cpu_cx_count = 0; 662 cx_ptr = sc->cpu_cx_states; 663 664 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 665 sc->cpu_prev_sleep = 1000000; 666 667 /* C1 has been required since just after ACPI 1.0 */ 668 cx_ptr->type = ACPI_STATE_C1; 669 cx_ptr->trans_lat = 0; 670 cx_ptr++; 671 sc->cpu_non_c3 = sc->cpu_cx_count; 672 sc->cpu_cx_count++; 673 674 /* 675 * The spec says P_BLK must be 6 bytes long. However, some systems 676 * use it to indicate a fractional set of features present so we 677 * take 5 as C2. Some may also have a value of 7 to indicate 678 * another C3 but most use _CST for this (as required) and having 679 * "only" C1-C3 is not a hardship. 680 */ 681 if (sc->cpu_p_blk_len < 5) 682 return; 683 684 /* Validate and allocate resources for C2 (P_LVL2). */ 685 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 686 gas.BitWidth = 8; 687 if (AcpiGbl_FADT.C2Latency <= 100) { 688 gas.Address = sc->cpu_p_blk + 4; 689 cx_ptr->res_rid = 0; 690 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 691 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 692 if (cx_ptr->p_lvlx != NULL) { 693 cx_ptr->type = ACPI_STATE_C2; 694 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 695 cx_ptr++; 696 sc->cpu_non_c3 = sc->cpu_cx_count; 697 sc->cpu_cx_count++; 698 } 699 } 700 if (sc->cpu_p_blk_len < 6) 701 return; 702 703 /* Validate and allocate resources for C3 (P_LVL3). */ 704 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 705 gas.Address = sc->cpu_p_blk + 5; 706 cx_ptr->res_rid = 1; 707 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid, 708 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE); 709 if (cx_ptr->p_lvlx != NULL) { 710 cx_ptr->type = ACPI_STATE_C3; 711 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 712 cx_ptr++; 713 sc->cpu_cx_count++; 714 cpu_can_deep_sleep = 1; 715 } 716 } 717 } 718 719 /* 720 * Parse a _CST package and set up its Cx states. Since the _CST object 721 * can change dynamically, our notify handler may call this function 722 * to clean up and probe the new _CST package. 723 */ 724 static int 725 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 726 { 727 struct acpi_cx *cx_ptr; 728 ACPI_STATUS status; 729 ACPI_BUFFER buf; 730 ACPI_OBJECT *top; 731 ACPI_OBJECT *pkg; 732 uint32_t count; 733 int i; 734 735 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 736 737 buf.Pointer = NULL; 738 buf.Length = ACPI_ALLOCATE_BUFFER; 739 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 740 if (ACPI_FAILURE(status)) 741 return (ENXIO); 742 743 /* _CST is a package with a count and at least one Cx package. */ 744 top = (ACPI_OBJECT *)buf.Pointer; 745 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 746 device_printf(sc->cpu_dev, "invalid _CST package\n"); 747 AcpiOsFree(buf.Pointer); 748 return (ENXIO); 749 } 750 if (count != top->Package.Count - 1) { 751 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 752 count, top->Package.Count - 1); 753 count = top->Package.Count - 1; 754 } 755 if (count > MAX_CX_STATES) { 756 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 757 count = MAX_CX_STATES; 758 } 759 760 sc->cpu_non_c3 = 0; 761 sc->cpu_cx_count = 0; 762 cx_ptr = sc->cpu_cx_states; 763 764 /* 765 * C1 has been required since just after ACPI 1.0. 766 * Reserve the first slot for it. 767 */ 768 cx_ptr->type = ACPI_STATE_C0; 769 cx_ptr++; 770 sc->cpu_cx_count++; 771 772 /* Set up all valid states. */ 773 for (i = 0; i < count; i++) { 774 pkg = &top->Package.Elements[i + 1]; 775 if (!ACPI_PKG_VALID(pkg, 4) || 776 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 777 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 778 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 779 780 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 781 continue; 782 } 783 784 /* Validate the state to see if we should use it. */ 785 switch (cx_ptr->type) { 786 case ACPI_STATE_C1: 787 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) { 788 /* This is the first C1 state. Use the reserved slot. */ 789 sc->cpu_cx_states[0] = *cx_ptr; 790 } else { 791 sc->cpu_non_c3 = sc->cpu_cx_count; 792 cx_ptr++; 793 sc->cpu_cx_count++; 794 } 795 continue; 796 case ACPI_STATE_C2: 797 sc->cpu_non_c3 = sc->cpu_cx_count; 798 break; 799 case ACPI_STATE_C3: 800 default: 801 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 802 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 803 "acpi_cpu%d: C3[%d] not available.\n", 804 device_get_unit(sc->cpu_dev), i)); 805 continue; 806 } else 807 cpu_can_deep_sleep = 1; 808 break; 809 } 810 811 /* Free up any previous register. */ 812 if (cx_ptr->p_lvlx != NULL) { 813 bus_release_resource(sc->cpu_dev, cx_ptr->res_type, cx_ptr->res_rid, 814 cx_ptr->p_lvlx); 815 cx_ptr->p_lvlx = NULL; 816 } 817 818 /* Allocate the control register for C2 or C3. */ 819 cx_ptr->res_rid = sc->cpu_cx_count; 820 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->res_rid, 821 &cx_ptr->p_lvlx, RF_SHAREABLE); 822 if (cx_ptr->p_lvlx) { 823 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 824 "acpi_cpu%d: Got C%d - %d latency\n", 825 device_get_unit(sc->cpu_dev), cx_ptr->type, 826 cx_ptr->trans_lat)); 827 cx_ptr++; 828 sc->cpu_cx_count++; 829 } 830 } 831 AcpiOsFree(buf.Pointer); 832 833 /* If C1 state was not found, we need one now. */ 834 cx_ptr = sc->cpu_cx_states; 835 if (cx_ptr->type == ACPI_STATE_C0) { 836 cx_ptr->type = ACPI_STATE_C1; 837 cx_ptr->trans_lat = 0; 838 } 839 840 return (0); 841 } 842 843 /* 844 * Call this *after* all CPUs have been attached. 845 */ 846 static void 847 acpi_cpu_startup(void *arg) 848 { 849 struct acpi_cpu_softc *sc; 850 int i; 851 852 /* Get set of CPU devices */ 853 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices); 854 855 /* 856 * Setup any quirks that might necessary now that we have probed 857 * all the CPUs 858 */ 859 acpi_cpu_quirks(); 860 861 if (cpu_cx_generic) { 862 /* 863 * We are using generic Cx mode, probe for available Cx states 864 * for all processors. 865 */ 866 for (i = 0; i < cpu_ndevices; i++) { 867 sc = device_get_softc(cpu_devices[i]); 868 acpi_cpu_generic_cx_probe(sc); 869 } 870 } else { 871 /* 872 * We are using _CST mode, remove C3 state if necessary. 873 * As we now know for sure that we will be using _CST mode 874 * install our notify handler. 875 */ 876 for (i = 0; i < cpu_ndevices; i++) { 877 sc = device_get_softc(cpu_devices[i]); 878 if (cpu_quirks & CPU_QUIRK_NO_C3) { 879 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 880 } 881 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY, 882 acpi_cpu_notify, sc); 883 } 884 } 885 886 /* Perform Cx final initialization. */ 887 for (i = 0; i < cpu_ndevices; i++) { 888 sc = device_get_softc(cpu_devices[i]); 889 acpi_cpu_startup_cx(sc); 890 } 891 892 /* Add a sysctl handler to handle global Cx lowest setting */ 893 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree), 894 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 895 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A", 896 "Global lowest Cx sleep state to use"); 897 898 /* Take over idling from cpu_idle_default(). */ 899 cpu_cx_lowest_lim = 0; 900 for (i = 0; i < cpu_ndevices; i++) { 901 sc = device_get_softc(cpu_devices[i]); 902 enable_idle(sc); 903 } 904 cpu_idle_hook = acpi_cpu_idle; 905 } 906 907 static void 908 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 909 { 910 struct sbuf sb; 911 int i; 912 913 /* 914 * Set up the list of Cx states 915 */ 916 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 917 SBUF_FIXEDLEN); 918 for (i = 0; i < sc->cpu_cx_count; i++) 919 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type, 920 sc->cpu_cx_states[i].trans_lat); 921 sbuf_trim(&sb); 922 sbuf_finish(&sb); 923 } 924 925 static void 926 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 927 { 928 acpi_cpu_cx_list(sc); 929 930 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx, 931 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 932 OID_AUTO, "cx_supported", CTLFLAG_RD, 933 sc->cpu_cx_supported, 0, 934 "Cx/microsecond values for supported Cx states"); 935 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 936 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 937 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 938 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 939 "lowest Cx sleep state to use"); 940 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 941 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 942 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 943 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 944 "percent usage for each Cx state"); 945 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx, 946 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)), 947 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD, 948 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A", 949 "Cx sleep state counters"); 950 951 /* Signal platform that we can handle _CST notification. */ 952 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 953 ACPI_LOCK(acpi); 954 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 955 ACPI_UNLOCK(acpi); 956 } 957 } 958 959 /* 960 * Idle the CPU in the lowest state possible. This function is called with 961 * interrupts disabled. Note that once it re-enables interrupts, a task 962 * switch can occur so do not access shared data (i.e. the softc) after 963 * interrupts are re-enabled. 964 */ 965 static void 966 acpi_cpu_idle(sbintime_t sbt) 967 { 968 struct acpi_cpu_softc *sc; 969 struct acpi_cx *cx_next; 970 uint64_t cputicks; 971 uint32_t start_time, end_time; 972 int bm_active, cx_next_idx, i, us; 973 974 /* 975 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 976 * since there is no ACPI processor object for this CPU. This occurs 977 * for logical CPUs in the HTT case. 978 */ 979 sc = cpu_softc[PCPU_GET(cpuid)]; 980 if (sc == NULL) { 981 acpi_cpu_c1(); 982 return; 983 } 984 985 /* If disabled, take the safe path. */ 986 if (is_idle_disabled(sc)) { 987 acpi_cpu_c1(); 988 return; 989 } 990 991 /* Find the lowest state that has small enough latency. */ 992 us = sc->cpu_prev_sleep; 993 if (sbt >= 0 && us > (sbt >> 12)) 994 us = (sbt >> 12); 995 cx_next_idx = 0; 996 if (cpu_disable_deep_sleep) 997 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3); 998 else 999 i = sc->cpu_cx_lowest; 1000 for (; i >= 0; i--) { 1001 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) { 1002 cx_next_idx = i; 1003 break; 1004 } 1005 } 1006 1007 /* 1008 * Check for bus master activity. If there was activity, clear 1009 * the bit and use the lowest non-C3 state. Note that the USB 1010 * driver polling for new devices keeps this bit set all the 1011 * time if USB is loaded. 1012 */ 1013 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 && 1014 cx_next_idx > sc->cpu_non_c3) { 1015 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 1016 if (bm_active != 0) { 1017 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 1018 cx_next_idx = sc->cpu_non_c3; 1019 } 1020 } 1021 1022 /* Select the next state and update statistics. */ 1023 cx_next = &sc->cpu_cx_states[cx_next_idx]; 1024 sc->cpu_cx_stats[cx_next_idx]++; 1025 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 1026 1027 /* 1028 * Execute HLT (or equivalent) and wait for an interrupt. We can't 1029 * precisely calculate the time spent in C1 since the place we wake up 1030 * is an ISR. Assume we slept no more then half of quantum, unless 1031 * we are called inside critical section, delaying context switch. 1032 */ 1033 if (cx_next->type == ACPI_STATE_C1) { 1034 cputicks = cpu_ticks(); 1035 acpi_cpu_c1(); 1036 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1037 if (curthread->td_critnest == 0) 1038 end_time = min(end_time, 500000 / hz); 1039 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4; 1040 return; 1041 } 1042 1043 /* 1044 * For C3, disable bus master arbitration and enable bus master wake 1045 * if BM control is available, otherwise flush the CPU cache. 1046 */ 1047 if (cx_next->type == ACPI_STATE_C3) { 1048 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1049 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 1050 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 1051 } else 1052 ACPI_FLUSH_CPU_CACHE(); 1053 } 1054 1055 /* 1056 * Read from P_LVLx to enter C2(+), checking time spent asleep. 1057 * Use the ACPI timer for measuring sleep time. Since we need to 1058 * get the time very close to the CPU start/stop clock logic, this 1059 * is the only reliable time source. 1060 */ 1061 if (cx_next->type == ACPI_STATE_C3) { 1062 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 1063 cputicks = 0; 1064 } else { 1065 start_time = 0; 1066 cputicks = cpu_ticks(); 1067 } 1068 CPU_GET_REG(cx_next->p_lvlx, 1); 1069 1070 /* 1071 * Read the end time twice. Since it may take an arbitrary time 1072 * to enter the idle state, the first read may be executed before 1073 * the processor has stopped. Doing it again provides enough 1074 * margin that we are certain to have a correct value. 1075 */ 1076 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1077 if (cx_next->type == ACPI_STATE_C3) { 1078 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 1079 end_time = acpi_TimerDelta(end_time, start_time); 1080 } else 1081 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate(); 1082 1083 /* Enable bus master arbitration and disable bus master wakeup. */ 1084 if (cx_next->type == ACPI_STATE_C3 && 1085 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 1086 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 1087 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1088 } 1089 ACPI_ENABLE_IRQS(); 1090 1091 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 1092 } 1093 1094 /* 1095 * Re-evaluate the _CST object when we are notified that it changed. 1096 */ 1097 static void 1098 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context) 1099 { 1100 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context; 1101 1102 if (notify != ACPI_NOTIFY_CX_STATES) 1103 return; 1104 1105 /* 1106 * C-state data for target CPU is going to be in flux while we execute 1107 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle. 1108 * Also, it may happen that multiple ACPI taskqueues may concurrently 1109 * execute notifications for the same CPU. ACPI_SERIAL is used to 1110 * protect against that. 1111 */ 1112 ACPI_SERIAL_BEGIN(cpu); 1113 disable_idle(sc); 1114 1115 /* Update the list of Cx states. */ 1116 acpi_cpu_cx_cst(sc); 1117 acpi_cpu_cx_list(sc); 1118 acpi_cpu_set_cx_lowest(sc); 1119 1120 enable_idle(sc); 1121 ACPI_SERIAL_END(cpu); 1122 1123 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify); 1124 } 1125 1126 static int 1127 acpi_cpu_quirks(void) 1128 { 1129 device_t acpi_dev; 1130 uint32_t val; 1131 1132 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 1133 1134 /* 1135 * Bus mastering arbitration control is needed to keep caches coherent 1136 * while sleeping in C3. If it's not present but a working flush cache 1137 * instruction is present, flush the caches before entering C3 instead. 1138 * Otherwise, just disable C3 completely. 1139 */ 1140 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 1141 AcpiGbl_FADT.Pm2ControlLength == 0) { 1142 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 1143 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 1144 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1145 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1146 "acpi_cpu: no BM control, using flush cache method\n")); 1147 } else { 1148 cpu_quirks |= CPU_QUIRK_NO_C3; 1149 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1150 "acpi_cpu: no BM control, C3 not available\n")); 1151 } 1152 } 1153 1154 /* 1155 * If we are using generic Cx mode, C3 on multiple CPUs requires using 1156 * the expensive flush cache instruction. 1157 */ 1158 if (cpu_cx_generic && mp_ncpus > 1) { 1159 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 1160 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1161 "acpi_cpu: SMP, using flush cache mode for C3\n")); 1162 } 1163 1164 /* Look for various quirks of the PIIX4 part. */ 1165 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 1166 if (acpi_dev != NULL) { 1167 switch (pci_get_revid(acpi_dev)) { 1168 /* 1169 * Disable C3 support for all PIIX4 chipsets. Some of these parts 1170 * do not report the BMIDE status to the BM status register and 1171 * others have a livelock bug if Type-F DMA is enabled. Linux 1172 * works around the BMIDE bug by reading the BM status directly 1173 * but we take the simpler approach of disabling C3 for these 1174 * parts. 1175 * 1176 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 1177 * Livelock") from the January 2002 PIIX4 specification update. 1178 * Applies to all PIIX4 models. 1179 * 1180 * Also, make sure that all interrupts cause a "Stop Break" 1181 * event to exit from C2 state. 1182 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 1183 * should be set to zero, otherwise it causes C2 to short-sleep. 1184 * PIIX4 doesn't properly support C3 and bus master activity 1185 * need not break out of C2. 1186 */ 1187 case PCI_REVISION_A_STEP: 1188 case PCI_REVISION_B_STEP: 1189 case PCI_REVISION_4E: 1190 case PCI_REVISION_4M: 1191 cpu_quirks |= CPU_QUIRK_NO_C3; 1192 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1193 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 1194 1195 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 1196 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 1197 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1198 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 1199 val |= PIIX4_STOP_BREAK_MASK; 1200 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 1201 } 1202 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 1203 if (val) { 1204 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 1205 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 1206 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 1207 } 1208 break; 1209 default: 1210 break; 1211 } 1212 } 1213 1214 return (0); 1215 } 1216 1217 static int 1218 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 1219 { 1220 struct acpi_cpu_softc *sc; 1221 struct sbuf sb; 1222 char buf[128]; 1223 int i; 1224 uintmax_t fract, sum, whole; 1225 1226 sc = (struct acpi_cpu_softc *) arg1; 1227 sum = 0; 1228 for (i = 0; i < sc->cpu_cx_count; i++) 1229 sum += sc->cpu_cx_stats[i]; 1230 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1231 for (i = 0; i < sc->cpu_cx_count; i++) { 1232 if (sum > 0) { 1233 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1234 fract = (whole % sum) * 100; 1235 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1236 (u_int)(fract / sum)); 1237 } else 1238 sbuf_printf(&sb, "0.00%% "); 1239 } 1240 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1241 sbuf_trim(&sb); 1242 sbuf_finish(&sb); 1243 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1244 sbuf_delete(&sb); 1245 1246 return (0); 1247 } 1248 1249 /* 1250 * XXX TODO: actually add support to count each entry/exit 1251 * from the Cx states. 1252 */ 1253 static int 1254 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS) 1255 { 1256 struct acpi_cpu_softc *sc; 1257 struct sbuf sb; 1258 char buf[128]; 1259 int i; 1260 1261 sc = (struct acpi_cpu_softc *) arg1; 1262 1263 /* Print out the raw counters */ 1264 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1265 1266 for (i = 0; i < sc->cpu_cx_count; i++) { 1267 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]); 1268 } 1269 1270 sbuf_trim(&sb); 1271 sbuf_finish(&sb); 1272 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1273 sbuf_delete(&sb); 1274 1275 return (0); 1276 } 1277 1278 static int 1279 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc) 1280 { 1281 int i; 1282 1283 ACPI_SERIAL_ASSERT(cpu); 1284 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1); 1285 1286 /* If not disabling, cache the new lowest non-C3 state. */ 1287 sc->cpu_non_c3 = 0; 1288 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1289 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1290 sc->cpu_non_c3 = i; 1291 break; 1292 } 1293 } 1294 1295 /* Reset the statistics counters. */ 1296 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1297 return (0); 1298 } 1299 1300 static int 1301 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1302 { 1303 struct acpi_cpu_softc *sc; 1304 char state[8]; 1305 int val, error; 1306 1307 sc = (struct acpi_cpu_softc *) arg1; 1308 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1); 1309 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1310 if (error != 0 || req->newptr == NULL) 1311 return (error); 1312 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1313 return (EINVAL); 1314 if (strcasecmp(state, "Cmax") == 0) 1315 val = MAX_CX_STATES; 1316 else { 1317 val = (int) strtol(state + 1, NULL, 10); 1318 if (val < 1 || val > MAX_CX_STATES) 1319 return (EINVAL); 1320 } 1321 1322 ACPI_SERIAL_BEGIN(cpu); 1323 sc->cpu_cx_lowest_lim = val - 1; 1324 acpi_cpu_set_cx_lowest(sc); 1325 ACPI_SERIAL_END(cpu); 1326 1327 return (0); 1328 } 1329 1330 static int 1331 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1332 { 1333 struct acpi_cpu_softc *sc; 1334 char state[8]; 1335 int val, error, i; 1336 1337 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1); 1338 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1339 if (error != 0 || req->newptr == NULL) 1340 return (error); 1341 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1342 return (EINVAL); 1343 if (strcasecmp(state, "Cmax") == 0) 1344 val = MAX_CX_STATES; 1345 else { 1346 val = (int) strtol(state + 1, NULL, 10); 1347 if (val < 1 || val > MAX_CX_STATES) 1348 return (EINVAL); 1349 } 1350 1351 /* Update the new lowest useable Cx state for all CPUs. */ 1352 ACPI_SERIAL_BEGIN(cpu); 1353 cpu_cx_lowest_lim = val - 1; 1354 for (i = 0; i < cpu_ndevices; i++) { 1355 sc = device_get_softc(cpu_devices[i]); 1356 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim; 1357 acpi_cpu_set_cx_lowest(sc); 1358 } 1359 ACPI_SERIAL_END(cpu); 1360 1361 return (0); 1362 } 1363