1*fd86ae68SMitchell Horne /*- 2*fd86ae68SMitchell Horne * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3*fd86ae68SMitchell Horne * 4*fd86ae68SMitchell Horne * Copyright (c) 2020 Netflix, Inc 5*fd86ae68SMitchell Horne * 6*fd86ae68SMitchell Horne * Redistribution and use in source and binary forms, with or without 7*fd86ae68SMitchell Horne * modification, are permitted provided that the following conditions 8*fd86ae68SMitchell Horne * are met: 9*fd86ae68SMitchell Horne * 1. Redistributions of source code must retain the above copyright 10*fd86ae68SMitchell Horne * notice, this list of conditions and the following disclaimer, 11*fd86ae68SMitchell Horne * without modification. 12*fd86ae68SMitchell Horne * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13*fd86ae68SMitchell Horne * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14*fd86ae68SMitchell Horne * redistribution must be conditioned upon including a substantially 15*fd86ae68SMitchell Horne * similar Disclaimer requirement for further binary redistribution. 16*fd86ae68SMitchell Horne * 17*fd86ae68SMitchell Horne * NO WARRANTY 18*fd86ae68SMitchell Horne * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19*fd86ae68SMitchell Horne * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20*fd86ae68SMitchell Horne * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21*fd86ae68SMitchell Horne * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22*fd86ae68SMitchell Horne * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23*fd86ae68SMitchell Horne * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*fd86ae68SMitchell Horne * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*fd86ae68SMitchell Horne * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26*fd86ae68SMitchell Horne * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*fd86ae68SMitchell Horne * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28*fd86ae68SMitchell Horne * THE POSSIBILITY OF SUCH DAMAGES. 29*fd86ae68SMitchell Horne * 30*fd86ae68SMitchell Horne * $FreeBSD$ 31*fd86ae68SMitchell Horne */ 32*fd86ae68SMitchell Horne 33*fd86ae68SMitchell Horne #include <sys/types.h> 34*fd86ae68SMitchell Horne #include <sys/systm.h> 35*fd86ae68SMitchell Horne 36*fd86ae68SMitchell Horne #include <machine/cpufunc.h> 37*fd86ae68SMitchell Horne #include <machine/md_var.h> 38*fd86ae68SMitchell Horne #include <x86/cputypes.h> 39*fd86ae68SMitchell Horne #include <x86/specialreg.h> 40*fd86ae68SMitchell Horne 41*fd86ae68SMitchell Horne #include <crypto/openssl/ossl.h> 42*fd86ae68SMitchell Horne 43*fd86ae68SMitchell Horne /* 44*fd86ae68SMitchell Horne * See OPENSSL_ia32cap(3). 45*fd86ae68SMitchell Horne * 46*fd86ae68SMitchell Horne * [0] = cpu_feature but with a few custom bits 47*fd86ae68SMitchell Horne * [1] = cpu_feature2 but with AMD XOP in bit 11 48*fd86ae68SMitchell Horne * [2] = cpu_stdext_feature 49*fd86ae68SMitchell Horne * [3] = 0 50*fd86ae68SMitchell Horne */ 51*fd86ae68SMitchell Horne unsigned int OPENSSL_ia32cap_P[4]; 52*fd86ae68SMitchell Horne 53*fd86ae68SMitchell Horne void 54*fd86ae68SMitchell Horne ossl_cpuid(void) 55*fd86ae68SMitchell Horne { 56*fd86ae68SMitchell Horne uint64_t xcr0; 57*fd86ae68SMitchell Horne u_int regs[4]; 58*fd86ae68SMitchell Horne u_int max_cores; 59*fd86ae68SMitchell Horne 60*fd86ae68SMitchell Horne /* Derived from OpenSSL_ia32_cpuid. */ 61*fd86ae68SMitchell Horne 62*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] = cpu_feature & ~(CPUID_B20 | CPUID_IA64); 63*fd86ae68SMitchell Horne if (cpu_vendor_id == CPU_VENDOR_INTEL) { 64*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] |= CPUID_IA64; 65*fd86ae68SMitchell Horne if ((cpu_id & 0xf00) != 0xf00) 66*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] |= CPUID_B20; 67*fd86ae68SMitchell Horne } 68*fd86ae68SMitchell Horne 69*fd86ae68SMitchell Horne /* Only leave CPUID_HTT on if HTT is present. */ 70*fd86ae68SMitchell Horne if (cpu_vendor_id == CPU_VENDOR_AMD && cpu_exthigh >= 0x80000008) { 71*fd86ae68SMitchell Horne max_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 72*fd86ae68SMitchell Horne if (cpu_feature & CPUID_HTT) { 73*fd86ae68SMitchell Horne if ((cpu_procinfo & CPUID_HTT_CORES) >> 16 <= max_cores) 74*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] &= ~CPUID_HTT; 75*fd86ae68SMitchell Horne } 76*fd86ae68SMitchell Horne } else { 77*fd86ae68SMitchell Horne if (cpu_high >= 4) { 78*fd86ae68SMitchell Horne cpuid_count(4, 0, regs); 79*fd86ae68SMitchell Horne max_cores = (regs[0] >> 26) & 0xfff; 80*fd86ae68SMitchell Horne } else 81*fd86ae68SMitchell Horne max_cores = -1; 82*fd86ae68SMitchell Horne } 83*fd86ae68SMitchell Horne if (max_cores == 0) 84*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] &= ~CPUID_HTT; 85*fd86ae68SMitchell Horne else if ((cpu_procinfo & CPUID_HTT_CORES) >> 16 == 0) 86*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[0] &= ~CPUID_HTT; 87*fd86ae68SMitchell Horne 88*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[1] = cpu_feature2 & ~AMDID2_XOP; 89*fd86ae68SMitchell Horne if (cpu_vendor_id == CPU_VENDOR_AMD) 90*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[1] |= amd_feature2 & AMDID2_XOP; 91*fd86ae68SMitchell Horne 92*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[2] = cpu_stdext_feature; 93*fd86ae68SMitchell Horne if ((OPENSSL_ia32cap_P[1] & CPUID2_XSAVE) == 0) 94*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512F | 95*fd86ae68SMitchell Horne CPUID_STDEXT_AVX512DQ); 96*fd86ae68SMitchell Horne 97*fd86ae68SMitchell Horne /* Disable AVX512F on Skylake-X. */ 98*fd86ae68SMitchell Horne if ((cpu_id & 0x0fff0ff0) == 0x00050650) 99*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512F); 100*fd86ae68SMitchell Horne 101*fd86ae68SMitchell Horne if (cpu_feature2 & CPUID2_OSXSAVE) 102*fd86ae68SMitchell Horne xcr0 = rxcr(0); 103*fd86ae68SMitchell Horne else 104*fd86ae68SMitchell Horne xcr0 = 0; 105*fd86ae68SMitchell Horne 106*fd86ae68SMitchell Horne if ((xcr0 & (XFEATURE_AVX512 | XFEATURE_AVX)) != 107*fd86ae68SMitchell Horne (XFEATURE_AVX512 | XFEATURE_AVX)) 108*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512VL | 109*fd86ae68SMitchell Horne CPUID_STDEXT_AVX512BW | CPUID_STDEXT_AVX512IFMA | 110*fd86ae68SMitchell Horne CPUID_STDEXT_AVX512F); 111*fd86ae68SMitchell Horne if ((xcr0 & XFEATURE_AVX) != XFEATURE_AVX) { 112*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[1] &= ~(CPUID2_AVX | AMDID2_XOP | CPUID2_FMA); 113*fd86ae68SMitchell Horne OPENSSL_ia32cap_P[2] &= ~CPUID_STDEXT_AVX2; 114*fd86ae68SMitchell Horne } 115*fd86ae68SMitchell Horne } 116