1 /*- 2 * Copyright (c) 2005-2008 Pawel Jakub Dawidek <pjd@FreeBSD.org> 3 * Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Portions of this software were developed by John-Mark Gurney 9 * under sponsorship of the FreeBSD Foundation and 10 * Rubicon Communications, LLC (Netgate). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/kobj.h> 41 #include <sys/libkern.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/rwlock.h> 46 #include <sys/bus.h> 47 #include <sys/uio.h> 48 #include <sys/mbuf.h> 49 #include <sys/smp.h> 50 51 #include <crypto/aesni/aesni.h> 52 #include <crypto/aesni/sha_sse.h> 53 #include <crypto/sha1.h> 54 #include <crypto/sha2/sha256.h> 55 56 #include <opencrypto/cryptodev.h> 57 #include <opencrypto/gmac.h> 58 #include <cryptodev_if.h> 59 60 #include <machine/md_var.h> 61 #include <machine/specialreg.h> 62 #if defined(__i386__) 63 #include <machine/npx.h> 64 #elif defined(__amd64__) 65 #include <machine/fpu.h> 66 #endif 67 68 static struct mtx_padalign *ctx_mtx; 69 static struct fpu_kern_ctx **ctx_fpu; 70 71 struct aesni_softc { 72 int dieing; 73 int32_t cid; 74 uint32_t sid; 75 bool has_aes; 76 bool has_sha; 77 TAILQ_HEAD(aesni_sessions_head, aesni_session) sessions; 78 struct rwlock lock; 79 }; 80 81 #define ACQUIRE_CTX(i, ctx) \ 82 do { \ 83 (i) = PCPU_GET(cpuid); \ 84 mtx_lock(&ctx_mtx[(i)]); \ 85 (ctx) = ctx_fpu[(i)]; \ 86 } while (0) 87 #define RELEASE_CTX(i, ctx) \ 88 do { \ 89 mtx_unlock(&ctx_mtx[(i)]); \ 90 (i) = -1; \ 91 (ctx) = NULL; \ 92 } while (0) 93 94 static int aesni_newsession(device_t, uint32_t *sidp, struct cryptoini *cri); 95 static int aesni_freesession(device_t, uint64_t tid); 96 static void aesni_freesession_locked(struct aesni_softc *sc, 97 struct aesni_session *ses); 98 static int aesni_cipher_setup(struct aesni_session *ses, 99 struct cryptoini *encini, struct cryptoini *authini); 100 static int aesni_cipher_process(struct aesni_session *ses, 101 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp); 102 static int aesni_cipher_crypt(struct aesni_session *ses, 103 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp); 104 static int aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd, 105 struct cryptop *crp); 106 107 MALLOC_DEFINE(M_AESNI, "aesni_data", "AESNI Data"); 108 109 static void 110 aesni_identify(driver_t *drv, device_t parent) 111 { 112 113 /* NB: order 10 is so we get attached after h/w devices */ 114 if (device_find_child(parent, "aesni", -1) == NULL && 115 BUS_ADD_CHILD(parent, 10, "aesni", -1) == 0) 116 panic("aesni: could not attach"); 117 } 118 119 static void 120 detect_cpu_features(bool *has_aes, bool *has_sha) 121 { 122 123 *has_aes = ((cpu_feature2 & CPUID2_AESNI) != 0 && 124 (cpu_feature2 & CPUID2_SSE41) != 0); 125 *has_sha = ((cpu_stdext_feature & CPUID_STDEXT_SHA) != 0 && 126 (cpu_feature2 & CPUID2_SSSE3) != 0); 127 } 128 129 static int 130 aesni_probe(device_t dev) 131 { 132 bool has_aes, has_sha; 133 134 detect_cpu_features(&has_aes, &has_sha); 135 if (!has_aes && !has_sha) { 136 device_printf(dev, "No AES or SHA support.\n"); 137 return (EINVAL); 138 } else if (has_aes && has_sha) 139 device_set_desc(dev, 140 "AES-CBC,AES-XTS,AES-GCM,AES-ICM,SHA1,SHA256"); 141 else if (has_aes) 142 device_set_desc(dev, "AES-CBC,AES-XTS,AES-GCM,AES-ICM"); 143 else 144 device_set_desc(dev, "SHA1,SHA256"); 145 146 return (0); 147 } 148 149 static void 150 aesni_cleanctx(void) 151 { 152 int i; 153 154 /* XXX - no way to return driverid */ 155 CPU_FOREACH(i) { 156 if (ctx_fpu[i] != NULL) { 157 mtx_destroy(&ctx_mtx[i]); 158 fpu_kern_free_ctx(ctx_fpu[i]); 159 } 160 ctx_fpu[i] = NULL; 161 } 162 free(ctx_mtx, M_AESNI); 163 ctx_mtx = NULL; 164 free(ctx_fpu, M_AESNI); 165 ctx_fpu = NULL; 166 } 167 168 static int 169 aesni_attach(device_t dev) 170 { 171 struct aesni_softc *sc; 172 int i; 173 174 sc = device_get_softc(dev); 175 sc->dieing = 0; 176 TAILQ_INIT(&sc->sessions); 177 sc->sid = 1; 178 179 sc->cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE | 180 CRYPTOCAP_F_SYNC); 181 if (sc->cid < 0) { 182 device_printf(dev, "Could not get crypto driver id.\n"); 183 return (ENOMEM); 184 } 185 186 ctx_mtx = malloc(sizeof *ctx_mtx * (mp_maxid + 1), M_AESNI, 187 M_WAITOK|M_ZERO); 188 ctx_fpu = malloc(sizeof *ctx_fpu * (mp_maxid + 1), M_AESNI, 189 M_WAITOK|M_ZERO); 190 191 CPU_FOREACH(i) { 192 ctx_fpu[i] = fpu_kern_alloc_ctx(0); 193 mtx_init(&ctx_mtx[i], "anifpumtx", NULL, MTX_DEF|MTX_NEW); 194 } 195 196 rw_init(&sc->lock, "aesni_lock"); 197 198 detect_cpu_features(&sc->has_aes, &sc->has_sha); 199 if (sc->has_aes) { 200 crypto_register(sc->cid, CRYPTO_AES_CBC, 0, 0); 201 crypto_register(sc->cid, CRYPTO_AES_ICM, 0, 0); 202 crypto_register(sc->cid, CRYPTO_AES_NIST_GCM_16, 0, 0); 203 crypto_register(sc->cid, CRYPTO_AES_128_NIST_GMAC, 0, 0); 204 crypto_register(sc->cid, CRYPTO_AES_192_NIST_GMAC, 0, 0); 205 crypto_register(sc->cid, CRYPTO_AES_256_NIST_GMAC, 0, 0); 206 crypto_register(sc->cid, CRYPTO_AES_XTS, 0, 0); 207 } 208 if (sc->has_sha) { 209 crypto_register(sc->cid, CRYPTO_SHA1, 0, 0); 210 crypto_register(sc->cid, CRYPTO_SHA1_HMAC, 0, 0); 211 crypto_register(sc->cid, CRYPTO_SHA2_256_HMAC, 0, 0); 212 } 213 return (0); 214 } 215 216 static int 217 aesni_detach(device_t dev) 218 { 219 struct aesni_softc *sc; 220 struct aesni_session *ses; 221 222 sc = device_get_softc(dev); 223 224 rw_wlock(&sc->lock); 225 TAILQ_FOREACH(ses, &sc->sessions, next) { 226 if (ses->used) { 227 rw_wunlock(&sc->lock); 228 device_printf(dev, 229 "Cannot detach, sessions still active.\n"); 230 return (EBUSY); 231 } 232 } 233 sc->dieing = 1; 234 while ((ses = TAILQ_FIRST(&sc->sessions)) != NULL) { 235 TAILQ_REMOVE(&sc->sessions, ses, next); 236 free(ses, M_AESNI); 237 } 238 rw_wunlock(&sc->lock); 239 crypto_unregister_all(sc->cid); 240 241 rw_destroy(&sc->lock); 242 243 aesni_cleanctx(); 244 245 return (0); 246 } 247 248 static int 249 aesni_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 250 { 251 struct aesni_softc *sc; 252 struct aesni_session *ses; 253 struct cryptoini *encini, *authini; 254 bool gcm_hash, gcm; 255 int error; 256 257 if (sidp == NULL || cri == NULL) { 258 CRYPTDEB("no sidp or cri"); 259 return (EINVAL); 260 } 261 262 sc = device_get_softc(dev); 263 if (sc->dieing) 264 return (EINVAL); 265 266 ses = NULL; 267 authini = NULL; 268 encini = NULL; 269 gcm = false; 270 gcm_hash = false; 271 for (; cri != NULL; cri = cri->cri_next) { 272 switch (cri->cri_alg) { 273 case CRYPTO_AES_NIST_GCM_16: 274 gcm = true; 275 /* FALLTHROUGH */ 276 case CRYPTO_AES_CBC: 277 case CRYPTO_AES_ICM: 278 case CRYPTO_AES_XTS: 279 if (!sc->has_aes) 280 goto unhandled; 281 if (encini != NULL) { 282 CRYPTDEB("encini already set"); 283 return (EINVAL); 284 } 285 encini = cri; 286 break; 287 case CRYPTO_AES_128_NIST_GMAC: 288 case CRYPTO_AES_192_NIST_GMAC: 289 case CRYPTO_AES_256_NIST_GMAC: 290 /* 291 * nothing to do here, maybe in the future cache some 292 * values for GHASH 293 */ 294 gcm_hash = true; 295 break; 296 case CRYPTO_SHA1: 297 case CRYPTO_SHA1_HMAC: 298 case CRYPTO_SHA2_256_HMAC: 299 if (!sc->has_sha) 300 goto unhandled; 301 if (authini != NULL) { 302 CRYPTDEB("authini already set"); 303 return (EINVAL); 304 } 305 authini = cri; 306 break; 307 default: 308 unhandled: 309 CRYPTDEB("unhandled algorithm"); 310 return (EINVAL); 311 } 312 } 313 if (encini == NULL && authini == NULL) { 314 CRYPTDEB("no cipher"); 315 return (EINVAL); 316 } 317 /* 318 * GMAC algorithms are only supported with simultaneous GCM. Likewise 319 * GCM is not supported without GMAC. 320 */ 321 if (gcm_hash != gcm) 322 return (EINVAL); 323 324 rw_wlock(&sc->lock); 325 if (sc->dieing) { 326 rw_wunlock(&sc->lock); 327 return (EINVAL); 328 } 329 /* 330 * Free sessions are inserted at the head of the list. So if the first 331 * session is used, none are free and we must allocate a new one. 332 */ 333 ses = TAILQ_FIRST(&sc->sessions); 334 if (ses == NULL || ses->used) { 335 ses = malloc(sizeof(*ses), M_AESNI, M_NOWAIT | M_ZERO); 336 if (ses == NULL) { 337 rw_wunlock(&sc->lock); 338 return (ENOMEM); 339 } 340 ses->id = sc->sid++; 341 } else { 342 TAILQ_REMOVE(&sc->sessions, ses, next); 343 } 344 ses->used = 1; 345 TAILQ_INSERT_TAIL(&sc->sessions, ses, next); 346 rw_wunlock(&sc->lock); 347 348 if (encini != NULL) 349 ses->algo = encini->cri_alg; 350 if (authini != NULL) 351 ses->auth_algo = authini->cri_alg; 352 353 error = aesni_cipher_setup(ses, encini, authini); 354 if (error != 0) { 355 CRYPTDEB("setup failed"); 356 rw_wlock(&sc->lock); 357 aesni_freesession_locked(sc, ses); 358 rw_wunlock(&sc->lock); 359 return (error); 360 } 361 362 *sidp = ses->id; 363 return (0); 364 } 365 366 static void 367 aesni_freesession_locked(struct aesni_softc *sc, struct aesni_session *ses) 368 { 369 uint32_t sid; 370 371 rw_assert(&sc->lock, RA_WLOCKED); 372 373 sid = ses->id; 374 TAILQ_REMOVE(&sc->sessions, ses, next); 375 explicit_bzero(ses, sizeof(*ses)); 376 ses->id = sid; 377 TAILQ_INSERT_HEAD(&sc->sessions, ses, next); 378 } 379 380 static int 381 aesni_freesession(device_t dev, uint64_t tid) 382 { 383 struct aesni_softc *sc; 384 struct aesni_session *ses; 385 uint32_t sid; 386 387 sc = device_get_softc(dev); 388 sid = ((uint32_t)tid) & 0xffffffff; 389 rw_wlock(&sc->lock); 390 TAILQ_FOREACH_REVERSE(ses, &sc->sessions, aesni_sessions_head, next) { 391 if (ses->id == sid) 392 break; 393 } 394 if (ses == NULL) { 395 rw_wunlock(&sc->lock); 396 return (EINVAL); 397 } 398 aesni_freesession_locked(sc, ses); 399 rw_wunlock(&sc->lock); 400 return (0); 401 } 402 403 static int 404 aesni_process(device_t dev, struct cryptop *crp, int hint __unused) 405 { 406 struct aesni_softc *sc; 407 struct aesni_session *ses; 408 struct cryptodesc *crd, *enccrd, *authcrd; 409 int error, needauth; 410 411 sc = device_get_softc(dev); 412 ses = NULL; 413 error = 0; 414 enccrd = NULL; 415 authcrd = NULL; 416 needauth = 0; 417 418 /* Sanity check. */ 419 if (crp == NULL) 420 return (EINVAL); 421 422 if (crp->crp_callback == NULL || crp->crp_desc == NULL) { 423 error = EINVAL; 424 goto out; 425 } 426 427 for (crd = crp->crp_desc; crd != NULL; crd = crd->crd_next) { 428 switch (crd->crd_alg) { 429 case CRYPTO_AES_NIST_GCM_16: 430 needauth = 1; 431 /* FALLTHROUGH */ 432 case CRYPTO_AES_CBC: 433 case CRYPTO_AES_ICM: 434 case CRYPTO_AES_XTS: 435 if (enccrd != NULL) { 436 error = EINVAL; 437 goto out; 438 } 439 enccrd = crd; 440 break; 441 442 case CRYPTO_AES_128_NIST_GMAC: 443 case CRYPTO_AES_192_NIST_GMAC: 444 case CRYPTO_AES_256_NIST_GMAC: 445 case CRYPTO_SHA1: 446 case CRYPTO_SHA1_HMAC: 447 case CRYPTO_SHA2_256_HMAC: 448 if (authcrd != NULL) { 449 error = EINVAL; 450 goto out; 451 } 452 authcrd = crd; 453 break; 454 455 default: 456 error = EINVAL; 457 goto out; 458 } 459 } 460 461 if ((enccrd == NULL && authcrd == NULL) || 462 (needauth && authcrd == NULL)) { 463 error = EINVAL; 464 goto out; 465 } 466 467 /* CBC & XTS can only handle full blocks for now */ 468 if (enccrd != NULL && (enccrd->crd_alg == CRYPTO_AES_CBC || 469 enccrd->crd_alg == CRYPTO_AES_XTS) && 470 (enccrd->crd_len % AES_BLOCK_LEN) != 0) { 471 error = EINVAL; 472 goto out; 473 } 474 475 rw_rlock(&sc->lock); 476 TAILQ_FOREACH_REVERSE(ses, &sc->sessions, aesni_sessions_head, next) { 477 if (ses->id == (crp->crp_sid & 0xffffffff)) 478 break; 479 } 480 rw_runlock(&sc->lock); 481 if (ses == NULL) { 482 error = EINVAL; 483 goto out; 484 } 485 486 error = aesni_cipher_process(ses, enccrd, authcrd, crp); 487 if (error != 0) 488 goto out; 489 490 out: 491 crp->crp_etype = error; 492 crypto_done(crp); 493 return (error); 494 } 495 496 static uint8_t * 497 aesni_cipher_alloc(struct cryptodesc *enccrd, struct cryptop *crp, 498 bool *allocated) 499 { 500 struct mbuf *m; 501 struct uio *uio; 502 struct iovec *iov; 503 uint8_t *addr; 504 505 if (crp->crp_flags & CRYPTO_F_IMBUF) { 506 m = (struct mbuf *)crp->crp_buf; 507 if (m->m_next != NULL) 508 goto alloc; 509 addr = mtod(m, uint8_t *); 510 } else if (crp->crp_flags & CRYPTO_F_IOV) { 511 uio = (struct uio *)crp->crp_buf; 512 if (uio->uio_iovcnt != 1) 513 goto alloc; 514 iov = uio->uio_iov; 515 addr = (uint8_t *)iov->iov_base; 516 } else 517 addr = (uint8_t *)crp->crp_buf; 518 *allocated = false; 519 addr += enccrd->crd_skip; 520 return (addr); 521 522 alloc: 523 addr = malloc(enccrd->crd_len, M_AESNI, M_NOWAIT); 524 if (addr != NULL) { 525 *allocated = true; 526 crypto_copydata(crp->crp_flags, crp->crp_buf, enccrd->crd_skip, 527 enccrd->crd_len, addr); 528 } else 529 *allocated = false; 530 return (addr); 531 } 532 533 static device_method_t aesni_methods[] = { 534 DEVMETHOD(device_identify, aesni_identify), 535 DEVMETHOD(device_probe, aesni_probe), 536 DEVMETHOD(device_attach, aesni_attach), 537 DEVMETHOD(device_detach, aesni_detach), 538 539 DEVMETHOD(cryptodev_newsession, aesni_newsession), 540 DEVMETHOD(cryptodev_freesession, aesni_freesession), 541 DEVMETHOD(cryptodev_process, aesni_process), 542 543 DEVMETHOD_END 544 }; 545 546 static driver_t aesni_driver = { 547 "aesni", 548 aesni_methods, 549 sizeof(struct aesni_softc), 550 }; 551 static devclass_t aesni_devclass; 552 553 DRIVER_MODULE(aesni, nexus, aesni_driver, aesni_devclass, 0, 0); 554 MODULE_VERSION(aesni, 1); 555 MODULE_DEPEND(aesni, crypto, 1, 1, 1); 556 557 static int 558 aesni_cipher_setup(struct aesni_session *ses, struct cryptoini *encini, 559 struct cryptoini *authini) 560 { 561 struct fpu_kern_ctx *ctx; 562 int kt, ctxidx, keylen, error; 563 564 switch (ses->auth_algo) { 565 case CRYPTO_SHA1: 566 case CRYPTO_SHA1_HMAC: 567 case CRYPTO_SHA2_256_HMAC: 568 if (authini->cri_klen % 8 != 0) 569 return (EINVAL); 570 keylen = authini->cri_klen / 8; 571 if (keylen > sizeof(ses->hmac_key)) 572 return (EINVAL); 573 if (ses->auth_algo == CRYPTO_SHA1 && keylen > 0) 574 return (EINVAL); 575 memcpy(ses->hmac_key, authini->cri_key, keylen); 576 ses->mlen = authini->cri_mlen; 577 } 578 579 kt = is_fpu_kern_thread(0) || (encini == NULL); 580 if (!kt) { 581 ACQUIRE_CTX(ctxidx, ctx); 582 fpu_kern_enter(curthread, ctx, 583 FPU_KERN_NORMAL | FPU_KERN_KTHR); 584 } 585 586 error = 0; 587 if (encini != NULL) 588 error = aesni_cipher_setup_common(ses, encini->cri_key, 589 encini->cri_klen); 590 591 if (!kt) { 592 fpu_kern_leave(curthread, ctx); 593 RELEASE_CTX(ctxidx, ctx); 594 } 595 return (error); 596 } 597 598 static int 599 intel_sha1_update(void *vctx, const void *vdata, u_int datalen) 600 { 601 struct sha1_ctxt *ctx = vctx; 602 const char *data = vdata; 603 size_t gaplen; 604 size_t gapstart; 605 size_t off; 606 size_t copysiz; 607 u_int blocks; 608 609 off = 0; 610 /* Do any aligned blocks without redundant copying. */ 611 if (datalen >= 64 && ctx->count % 64 == 0) { 612 blocks = datalen / 64; 613 ctx->c.b64[0] += blocks * 64 * 8; 614 intel_sha1_step(ctx->h.b32, data + off, blocks); 615 off += blocks * 64; 616 } 617 618 while (off < datalen) { 619 gapstart = ctx->count % 64; 620 gaplen = 64 - gapstart; 621 622 copysiz = (gaplen < datalen - off) ? gaplen : datalen - off; 623 bcopy(&data[off], &ctx->m.b8[gapstart], copysiz); 624 ctx->count += copysiz; 625 ctx->count %= 64; 626 ctx->c.b64[0] += copysiz * 8; 627 if (ctx->count % 64 == 0) 628 intel_sha1_step(ctx->h.b32, (void *)ctx->m.b8, 1); 629 off += copysiz; 630 } 631 return (0); 632 } 633 634 static void 635 SHA1_Finalize_fn(void *digest, void *ctx) 636 { 637 sha1_result(ctx, digest); 638 } 639 640 static int 641 intel_sha256_update(void *vctx, const void *vdata, u_int len) 642 { 643 SHA256_CTX *ctx = vctx; 644 uint64_t bitlen; 645 uint32_t r; 646 u_int blocks; 647 const unsigned char *src = vdata; 648 649 /* Number of bytes left in the buffer from previous updates */ 650 r = (ctx->count >> 3) & 0x3f; 651 652 /* Convert the length into a number of bits */ 653 bitlen = len << 3; 654 655 /* Update number of bits */ 656 ctx->count += bitlen; 657 658 /* Handle the case where we don't need to perform any transforms */ 659 if (len < 64 - r) { 660 memcpy(&ctx->buf[r], src, len); 661 return (0); 662 } 663 664 /* Finish the current block */ 665 memcpy(&ctx->buf[r], src, 64 - r); 666 intel_sha256_step(ctx->state, ctx->buf, 1); 667 src += 64 - r; 668 len -= 64 - r; 669 670 /* Perform complete blocks */ 671 if (len >= 64) { 672 blocks = len / 64; 673 intel_sha256_step(ctx->state, src, blocks); 674 src += blocks * 64; 675 len -= blocks * 64; 676 } 677 678 /* Copy left over data into buffer */ 679 memcpy(ctx->buf, src, len); 680 return (0); 681 } 682 683 static void 684 SHA256_Finalize_fn(void *digest, void *ctx) 685 { 686 SHA256_Final(digest, ctx); 687 } 688 689 /* 690 * Compute the HASH( (key ^ xorbyte) || buf ) 691 */ 692 static void 693 hmac_internal(void *ctx, uint32_t *res, 694 int (*update)(void *, const void *, u_int), 695 void (*finalize)(void *, void *), uint8_t *key, uint8_t xorbyte, 696 const void *buf, size_t off, size_t buflen, int crpflags) 697 { 698 size_t i; 699 700 for (i = 0; i < 64; i++) 701 key[i] ^= xorbyte; 702 update(ctx, key, 64); 703 for (i = 0; i < 64; i++) 704 key[i] ^= xorbyte; 705 706 crypto_apply(crpflags, __DECONST(void *, buf), off, buflen, 707 __DECONST(int (*)(void *, void *, u_int), update), ctx); 708 finalize(res, ctx); 709 } 710 711 static int 712 aesni_cipher_process(struct aesni_session *ses, struct cryptodesc *enccrd, 713 struct cryptodesc *authcrd, struct cryptop *crp) 714 { 715 struct fpu_kern_ctx *ctx; 716 int error, ctxidx; 717 bool kt; 718 719 if (enccrd != NULL) { 720 if ((enccrd->crd_alg == CRYPTO_AES_ICM || 721 enccrd->crd_alg == CRYPTO_AES_NIST_GCM_16) && 722 (enccrd->crd_flags & CRD_F_IV_EXPLICIT) == 0) 723 return (EINVAL); 724 } 725 726 ctx = NULL; 727 ctxidx = 0; 728 error = 0; 729 kt = is_fpu_kern_thread(0); 730 if (!kt) { 731 ACQUIRE_CTX(ctxidx, ctx); 732 fpu_kern_enter(curthread, ctx, 733 FPU_KERN_NORMAL | FPU_KERN_KTHR); 734 } 735 736 /* Do work */ 737 if (enccrd != NULL && authcrd != NULL) { 738 /* Perform the first operation */ 739 if (crp->crp_desc == enccrd) 740 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 741 else 742 error = aesni_cipher_mac(ses, authcrd, crp); 743 if (error != 0) 744 goto out; 745 /* Perform the second operation */ 746 if (crp->crp_desc == enccrd) 747 error = aesni_cipher_mac(ses, authcrd, crp); 748 else 749 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 750 } else if (enccrd != NULL) 751 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 752 else 753 error = aesni_cipher_mac(ses, authcrd, crp); 754 755 if (error != 0) 756 goto out; 757 758 out: 759 if (!kt) { 760 fpu_kern_leave(curthread, ctx); 761 RELEASE_CTX(ctxidx, ctx); 762 } 763 return (error); 764 } 765 766 static int 767 aesni_cipher_crypt(struct aesni_session *ses, struct cryptodesc *enccrd, 768 struct cryptodesc *authcrd, struct cryptop *crp) 769 { 770 uint8_t iv[AES_BLOCK_LEN], tag[GMAC_DIGEST_LEN], *buf, *authbuf; 771 int error, ivlen; 772 bool encflag, allocated, authallocated; 773 774 KASSERT(ses->algo != CRYPTO_AES_NIST_GCM_16 || authcrd != NULL, 775 ("AES_NIST_GCM_16 must include MAC descriptor")); 776 777 ivlen = 0; 778 authbuf = NULL; 779 780 buf = aesni_cipher_alloc(enccrd, crp, &allocated); 781 if (buf == NULL) 782 return (ENOMEM); 783 784 authallocated = false; 785 if (ses->algo == CRYPTO_AES_NIST_GCM_16) { 786 authbuf = aesni_cipher_alloc(authcrd, crp, &authallocated); 787 if (authbuf == NULL) { 788 error = ENOMEM; 789 goto out; 790 } 791 } 792 793 error = 0; 794 encflag = (enccrd->crd_flags & CRD_F_ENCRYPT) == CRD_F_ENCRYPT; 795 if ((enccrd->crd_flags & CRD_F_KEY_EXPLICIT) != 0) { 796 error = aesni_cipher_setup_common(ses, enccrd->crd_key, 797 enccrd->crd_klen); 798 if (error != 0) 799 goto out; 800 } 801 802 switch (enccrd->crd_alg) { 803 case CRYPTO_AES_CBC: 804 case CRYPTO_AES_ICM: 805 ivlen = AES_BLOCK_LEN; 806 break; 807 case CRYPTO_AES_XTS: 808 ivlen = 8; 809 break; 810 case CRYPTO_AES_NIST_GCM_16: 811 ivlen = 12; /* should support arbitarily larger */ 812 break; 813 } 814 815 /* Setup iv */ 816 if (encflag) { 817 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0) 818 bcopy(enccrd->crd_iv, iv, ivlen); 819 else 820 arc4rand(iv, ivlen, 0); 821 822 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) 823 crypto_copyback(crp->crp_flags, crp->crp_buf, 824 enccrd->crd_inject, ivlen, iv); 825 } else { 826 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0) 827 bcopy(enccrd->crd_iv, iv, ivlen); 828 else 829 crypto_copydata(crp->crp_flags, crp->crp_buf, 830 enccrd->crd_inject, ivlen, iv); 831 } 832 833 switch (ses->algo) { 834 case CRYPTO_AES_CBC: 835 if (encflag) 836 aesni_encrypt_cbc(ses->rounds, ses->enc_schedule, 837 enccrd->crd_len, buf, buf, iv); 838 else 839 aesni_decrypt_cbc(ses->rounds, ses->dec_schedule, 840 enccrd->crd_len, buf, iv); 841 break; 842 case CRYPTO_AES_ICM: 843 /* encryption & decryption are the same */ 844 aesni_encrypt_icm(ses->rounds, ses->enc_schedule, 845 enccrd->crd_len, buf, buf, iv); 846 break; 847 case CRYPTO_AES_XTS: 848 if (encflag) 849 aesni_encrypt_xts(ses->rounds, ses->enc_schedule, 850 ses->xts_schedule, enccrd->crd_len, buf, buf, 851 iv); 852 else 853 aesni_decrypt_xts(ses->rounds, ses->dec_schedule, 854 ses->xts_schedule, enccrd->crd_len, buf, buf, 855 iv); 856 break; 857 case CRYPTO_AES_NIST_GCM_16: 858 if (!encflag) 859 crypto_copydata(crp->crp_flags, crp->crp_buf, 860 authcrd->crd_inject, GMAC_DIGEST_LEN, tag); 861 else 862 bzero(tag, sizeof tag); 863 864 if (encflag) { 865 AES_GCM_encrypt(buf, buf, authbuf, iv, tag, 866 enccrd->crd_len, authcrd->crd_len, ivlen, 867 ses->enc_schedule, ses->rounds); 868 869 if (authcrd != NULL) 870 crypto_copyback(crp->crp_flags, crp->crp_buf, 871 authcrd->crd_inject, GMAC_DIGEST_LEN, tag); 872 } else { 873 if (!AES_GCM_decrypt(buf, buf, authbuf, iv, tag, 874 enccrd->crd_len, authcrd->crd_len, ivlen, 875 ses->enc_schedule, ses->rounds)) 876 error = EBADMSG; 877 } 878 break; 879 } 880 881 out: 882 if (allocated) { 883 explicit_bzero(buf, enccrd->crd_len); 884 free(buf, M_AESNI); 885 } 886 if (authallocated) { 887 explicit_bzero(authbuf, authcrd->crd_len); 888 free(authbuf, M_AESNI); 889 } 890 return (error); 891 } 892 893 static int 894 aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd, 895 struct cryptop *crp) 896 { 897 union { 898 struct SHA256Context sha2 __aligned(16); 899 struct sha1_ctxt sha1 __aligned(16); 900 } sctx; 901 uint32_t res[SHA2_256_HASH_LEN / sizeof(uint32_t)]; 902 int hashlen; 903 904 if (crd->crd_flags != 0) 905 return (EINVAL); 906 907 switch (ses->auth_algo) { 908 case CRYPTO_SHA1_HMAC: 909 hashlen = SHA1_HASH_LEN; 910 /* Inner hash: (K ^ IPAD) || data */ 911 sha1_init(&sctx.sha1); 912 hmac_internal(&sctx.sha1, res, intel_sha1_update, 913 SHA1_Finalize_fn, ses->hmac_key, 0x36, crp->crp_buf, 914 crd->crd_skip, crd->crd_len, crp->crp_flags); 915 /* Outer hash: (K ^ OPAD) || inner hash */ 916 sha1_init(&sctx.sha1); 917 hmac_internal(&sctx.sha1, res, intel_sha1_update, 918 SHA1_Finalize_fn, ses->hmac_key, 0x5C, res, 0, hashlen, 0); 919 break; 920 case CRYPTO_SHA1: 921 hashlen = SHA1_HASH_LEN; 922 sha1_init(&sctx.sha1); 923 crypto_apply(crp->crp_flags, crp->crp_buf, crd->crd_skip, 924 crd->crd_len, __DECONST(int (*)(void *, void *, u_int), 925 intel_sha1_update), &sctx.sha1); 926 sha1_result(&sctx.sha1, (void *)res); 927 break; 928 case CRYPTO_SHA2_256_HMAC: 929 hashlen = SHA2_256_HASH_LEN; 930 /* Inner hash: (K ^ IPAD) || data */ 931 SHA256_Init(&sctx.sha2); 932 hmac_internal(&sctx.sha2, res, intel_sha256_update, 933 SHA256_Finalize_fn, ses->hmac_key, 0x36, crp->crp_buf, 934 crd->crd_skip, crd->crd_len, crp->crp_flags); 935 /* Outer hash: (K ^ OPAD) || inner hash */ 936 SHA256_Init(&sctx.sha2); 937 hmac_internal(&sctx.sha2, res, intel_sha256_update, 938 SHA256_Finalize_fn, ses->hmac_key, 0x5C, res, 0, hashlen, 939 0); 940 break; 941 default: 942 /* 943 * AES-GMAC authentication is verified while processing the 944 * enccrd 945 */ 946 return (0); 947 } 948 949 if (ses->mlen != 0 && ses->mlen < hashlen) 950 hashlen = ses->mlen; 951 952 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, hashlen, 953 (void *)res); 954 return (0); 955 } 956