1 /*- 2 * Copyright (c) 2005-2008 Pawel Jakub Dawidek <pjd@FreeBSD.org> 3 * Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Portions of this software were developed by John-Mark Gurney 9 * under sponsorship of the FreeBSD Foundation and 10 * Rubicon Communications, LLC (Netgate). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/kobj.h> 41 #include <sys/libkern.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/mbuf.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/smp.h> 48 #include <sys/systm.h> 49 #include <sys/uio.h> 50 51 #include <crypto/aesni/aesni.h> 52 #include <crypto/aesni/sha_sse.h> 53 #include <crypto/sha1.h> 54 #include <crypto/sha2/sha224.h> 55 #include <crypto/sha2/sha256.h> 56 57 #include <opencrypto/cryptodev.h> 58 #include <opencrypto/gmac.h> 59 #include <cryptodev_if.h> 60 61 #include <machine/md_var.h> 62 #include <machine/specialreg.h> 63 #if defined(__i386__) 64 #include <machine/npx.h> 65 #elif defined(__amd64__) 66 #include <machine/fpu.h> 67 #endif 68 69 static struct mtx_padalign *ctx_mtx; 70 static struct fpu_kern_ctx **ctx_fpu; 71 72 struct aesni_softc { 73 int32_t cid; 74 bool has_aes; 75 bool has_sha; 76 }; 77 78 #define ACQUIRE_CTX(i, ctx) \ 79 do { \ 80 (i) = PCPU_GET(cpuid); \ 81 mtx_lock(&ctx_mtx[(i)]); \ 82 (ctx) = ctx_fpu[(i)]; \ 83 } while (0) 84 #define RELEASE_CTX(i, ctx) \ 85 do { \ 86 mtx_unlock(&ctx_mtx[(i)]); \ 87 (i) = -1; \ 88 (ctx) = NULL; \ 89 } while (0) 90 91 static int aesni_newsession(device_t, crypto_session_t cses, 92 struct cryptoini *cri); 93 static int aesni_cipher_setup(struct aesni_session *ses, 94 struct cryptoini *encini, struct cryptoini *authini); 95 static int aesni_cipher_process(struct aesni_session *ses, 96 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp); 97 static int aesni_cipher_crypt(struct aesni_session *ses, 98 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp); 99 static int aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd, 100 struct cryptop *crp); 101 102 MALLOC_DEFINE(M_AESNI, "aesni_data", "AESNI Data"); 103 104 static void 105 aesni_identify(driver_t *drv, device_t parent) 106 { 107 108 /* NB: order 10 is so we get attached after h/w devices */ 109 if (device_find_child(parent, "aesni", -1) == NULL && 110 BUS_ADD_CHILD(parent, 10, "aesni", -1) == 0) 111 panic("aesni: could not attach"); 112 } 113 114 static void 115 detect_cpu_features(bool *has_aes, bool *has_sha) 116 { 117 118 *has_aes = ((cpu_feature2 & CPUID2_AESNI) != 0 && 119 (cpu_feature2 & CPUID2_SSE41) != 0); 120 *has_sha = ((cpu_stdext_feature & CPUID_STDEXT_SHA) != 0 && 121 (cpu_feature2 & CPUID2_SSSE3) != 0); 122 } 123 124 static int 125 aesni_probe(device_t dev) 126 { 127 bool has_aes, has_sha; 128 129 detect_cpu_features(&has_aes, &has_sha); 130 if (!has_aes && !has_sha) { 131 device_printf(dev, "No AES or SHA support.\n"); 132 return (EINVAL); 133 } else if (has_aes && has_sha) 134 device_set_desc(dev, 135 "AES-CBC,AES-CCM,AES-GCM,AES-ICM,AES-XTS,SHA1,SHA256"); 136 else if (has_aes) 137 device_set_desc(dev, 138 "AES-CBC,AES-CCM,AES-GCM,AES-ICM,AES-XTS"); 139 else 140 device_set_desc(dev, "SHA1,SHA256"); 141 142 return (0); 143 } 144 145 static void 146 aesni_cleanctx(void) 147 { 148 int i; 149 150 /* XXX - no way to return driverid */ 151 CPU_FOREACH(i) { 152 if (ctx_fpu[i] != NULL) { 153 mtx_destroy(&ctx_mtx[i]); 154 fpu_kern_free_ctx(ctx_fpu[i]); 155 } 156 ctx_fpu[i] = NULL; 157 } 158 free(ctx_mtx, M_AESNI); 159 ctx_mtx = NULL; 160 free(ctx_fpu, M_AESNI); 161 ctx_fpu = NULL; 162 } 163 164 static int 165 aesni_attach(device_t dev) 166 { 167 struct aesni_softc *sc; 168 int i; 169 170 sc = device_get_softc(dev); 171 172 sc->cid = crypto_get_driverid(dev, sizeof(struct aesni_session), 173 CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); 174 if (sc->cid < 0) { 175 device_printf(dev, "Could not get crypto driver id.\n"); 176 return (ENOMEM); 177 } 178 179 ctx_mtx = malloc(sizeof *ctx_mtx * (mp_maxid + 1), M_AESNI, 180 M_WAITOK|M_ZERO); 181 ctx_fpu = malloc(sizeof *ctx_fpu * (mp_maxid + 1), M_AESNI, 182 M_WAITOK|M_ZERO); 183 184 CPU_FOREACH(i) { 185 ctx_fpu[i] = fpu_kern_alloc_ctx(0); 186 mtx_init(&ctx_mtx[i], "anifpumtx", NULL, MTX_DEF|MTX_NEW); 187 } 188 189 detect_cpu_features(&sc->has_aes, &sc->has_sha); 190 if (sc->has_aes) { 191 crypto_register(sc->cid, CRYPTO_AES_CBC, 0, 0); 192 crypto_register(sc->cid, CRYPTO_AES_ICM, 0, 0); 193 crypto_register(sc->cid, CRYPTO_AES_NIST_GCM_16, 0, 0); 194 crypto_register(sc->cid, CRYPTO_AES_128_NIST_GMAC, 0, 0); 195 crypto_register(sc->cid, CRYPTO_AES_192_NIST_GMAC, 0, 0); 196 crypto_register(sc->cid, CRYPTO_AES_256_NIST_GMAC, 0, 0); 197 crypto_register(sc->cid, CRYPTO_AES_XTS, 0, 0); 198 crypto_register(sc->cid, CRYPTO_AES_CCM_16, 0, 0); 199 crypto_register(sc->cid, CRYPTO_AES_CCM_CBC_MAC, 0, 0); 200 } 201 if (sc->has_sha) { 202 crypto_register(sc->cid, CRYPTO_SHA1, 0, 0); 203 crypto_register(sc->cid, CRYPTO_SHA1_HMAC, 0, 0); 204 crypto_register(sc->cid, CRYPTO_SHA2_224, 0, 0); 205 crypto_register(sc->cid, CRYPTO_SHA2_224_HMAC, 0, 0); 206 crypto_register(sc->cid, CRYPTO_SHA2_256, 0, 0); 207 crypto_register(sc->cid, CRYPTO_SHA2_256_HMAC, 0, 0); 208 } 209 return (0); 210 } 211 212 static int 213 aesni_detach(device_t dev) 214 { 215 struct aesni_softc *sc; 216 217 sc = device_get_softc(dev); 218 219 crypto_unregister_all(sc->cid); 220 221 aesni_cleanctx(); 222 223 return (0); 224 } 225 226 static int 227 aesni_newsession(device_t dev, crypto_session_t cses, struct cryptoini *cri) 228 { 229 struct aesni_softc *sc; 230 struct aesni_session *ses; 231 struct cryptoini *encini, *authini; 232 bool gcm_hash, gcm; 233 bool cbc_hash, ccm; 234 int error; 235 236 KASSERT(cses != NULL, ("EDOOFUS")); 237 if (cri == NULL) { 238 CRYPTDEB("no cri"); 239 return (EINVAL); 240 } 241 242 sc = device_get_softc(dev); 243 244 ses = crypto_get_driver_session(cses); 245 246 authini = NULL; 247 encini = NULL; 248 gcm = false; 249 gcm_hash = false; 250 ccm = cbc_hash = false; 251 252 for (; cri != NULL; cri = cri->cri_next) { 253 switch (cri->cri_alg) { 254 case CRYPTO_AES_NIST_GCM_16: 255 case CRYPTO_AES_CCM_16: 256 if (cri->cri_alg == CRYPTO_AES_NIST_GCM_16) { 257 gcm = true; 258 } else if (cri->cri_alg == CRYPTO_AES_CCM_16) { 259 ccm = true; 260 } 261 /* FALLTHROUGH */ 262 case CRYPTO_AES_CBC: 263 case CRYPTO_AES_ICM: 264 case CRYPTO_AES_XTS: 265 if (!sc->has_aes) 266 goto unhandled; 267 if (encini != NULL) { 268 CRYPTDEB("encini already set"); 269 return (EINVAL); 270 } 271 encini = cri; 272 break; 273 case CRYPTO_AES_CCM_CBC_MAC: 274 cbc_hash = true; 275 authini = cri; 276 break; 277 case CRYPTO_AES_128_NIST_GMAC: 278 case CRYPTO_AES_192_NIST_GMAC: 279 case CRYPTO_AES_256_NIST_GMAC: 280 /* 281 * nothing to do here, maybe in the future cache some 282 * values for GHASH 283 */ 284 if (authini != NULL) { 285 CRYPTDEB("authini already set"); 286 return (EINVAL); 287 } 288 gcm_hash = true; 289 authini = cri; 290 break; 291 case CRYPTO_SHA1: 292 case CRYPTO_SHA1_HMAC: 293 case CRYPTO_SHA2_224: 294 case CRYPTO_SHA2_224_HMAC: 295 case CRYPTO_SHA2_256: 296 case CRYPTO_SHA2_256_HMAC: 297 if (!sc->has_sha) 298 goto unhandled; 299 if (authini != NULL) { 300 CRYPTDEB("authini already set"); 301 return (EINVAL); 302 } 303 authini = cri; 304 break; 305 default: 306 unhandled: 307 CRYPTDEB("unhandled algorithm"); 308 return (EINVAL); 309 } 310 } 311 if (encini == NULL && authini == NULL) { 312 CRYPTDEB("no cipher"); 313 return (EINVAL); 314 } 315 /* 316 * GMAC algorithms are only supported with simultaneous GCM. Likewise 317 * GCM is not supported without GMAC. 318 */ 319 if (gcm_hash != gcm) { 320 CRYPTDEB("gcm_hash != gcm"); 321 return (EINVAL); 322 } 323 324 if (cbc_hash != ccm) { 325 CRYPTDEB("cbc_hash != ccm"); 326 return (EINVAL); 327 } 328 329 if (encini != NULL) 330 ses->algo = encini->cri_alg; 331 if (authini != NULL) 332 ses->auth_algo = authini->cri_alg; 333 334 error = aesni_cipher_setup(ses, encini, authini); 335 if (error != 0) { 336 CRYPTDEB("setup failed"); 337 return (error); 338 } 339 340 return (0); 341 } 342 343 static int 344 aesni_process(device_t dev, struct cryptop *crp, int hint __unused) 345 { 346 struct aesni_session *ses; 347 struct cryptodesc *crd, *enccrd, *authcrd; 348 int error, needauth; 349 350 ses = NULL; 351 error = 0; 352 enccrd = NULL; 353 authcrd = NULL; 354 needauth = 0; 355 356 /* Sanity check. */ 357 if (crp == NULL) 358 return (EINVAL); 359 360 if (crp->crp_callback == NULL || crp->crp_desc == NULL || 361 crp->crp_session == NULL) { 362 error = EINVAL; 363 goto out; 364 } 365 366 for (crd = crp->crp_desc; crd != NULL; crd = crd->crd_next) { 367 switch (crd->crd_alg) { 368 case CRYPTO_AES_NIST_GCM_16: 369 case CRYPTO_AES_CCM_16: 370 needauth = 1; 371 /* FALLTHROUGH */ 372 case CRYPTO_AES_CBC: 373 case CRYPTO_AES_ICM: 374 case CRYPTO_AES_XTS: 375 if (enccrd != NULL) { 376 error = EINVAL; 377 goto out; 378 } 379 enccrd = crd; 380 break; 381 382 case CRYPTO_AES_128_NIST_GMAC: 383 case CRYPTO_AES_192_NIST_GMAC: 384 case CRYPTO_AES_256_NIST_GMAC: 385 case CRYPTO_AES_CCM_CBC_MAC: 386 case CRYPTO_SHA1: 387 case CRYPTO_SHA1_HMAC: 388 case CRYPTO_SHA2_224: 389 case CRYPTO_SHA2_224_HMAC: 390 case CRYPTO_SHA2_256: 391 case CRYPTO_SHA2_256_HMAC: 392 if (authcrd != NULL) { 393 error = EINVAL; 394 goto out; 395 } 396 authcrd = crd; 397 break; 398 399 default: 400 error = EINVAL; 401 goto out; 402 } 403 } 404 405 if ((enccrd == NULL && authcrd == NULL) || 406 (needauth && authcrd == NULL)) { 407 error = EINVAL; 408 goto out; 409 } 410 411 /* CBC & XTS can only handle full blocks for now */ 412 if (enccrd != NULL && (enccrd->crd_alg == CRYPTO_AES_CBC || 413 enccrd->crd_alg == CRYPTO_AES_XTS) && 414 (enccrd->crd_len % AES_BLOCK_LEN) != 0) { 415 error = EINVAL; 416 goto out; 417 } 418 419 ses = crypto_get_driver_session(crp->crp_session); 420 KASSERT(ses != NULL, ("EDOOFUS")); 421 422 error = aesni_cipher_process(ses, enccrd, authcrd, crp); 423 if (error != 0) 424 goto out; 425 426 out: 427 crp->crp_etype = error; 428 crypto_done(crp); 429 return (error); 430 } 431 432 static uint8_t * 433 aesni_cipher_alloc(struct cryptodesc *enccrd, struct cryptop *crp, 434 bool *allocated) 435 { 436 uint8_t *addr; 437 438 addr = crypto_contiguous_subsegment(crp->crp_flags, 439 crp->crp_buf, enccrd->crd_skip, enccrd->crd_len); 440 if (addr != NULL) { 441 *allocated = false; 442 return (addr); 443 } 444 addr = malloc(enccrd->crd_len, M_AESNI, M_NOWAIT); 445 if (addr != NULL) { 446 *allocated = true; 447 crypto_copydata(crp->crp_flags, crp->crp_buf, enccrd->crd_skip, 448 enccrd->crd_len, addr); 449 } else 450 *allocated = false; 451 return (addr); 452 } 453 454 static device_method_t aesni_methods[] = { 455 DEVMETHOD(device_identify, aesni_identify), 456 DEVMETHOD(device_probe, aesni_probe), 457 DEVMETHOD(device_attach, aesni_attach), 458 DEVMETHOD(device_detach, aesni_detach), 459 460 DEVMETHOD(cryptodev_newsession, aesni_newsession), 461 DEVMETHOD(cryptodev_process, aesni_process), 462 463 DEVMETHOD_END 464 }; 465 466 static driver_t aesni_driver = { 467 "aesni", 468 aesni_methods, 469 sizeof(struct aesni_softc), 470 }; 471 static devclass_t aesni_devclass; 472 473 DRIVER_MODULE(aesni, nexus, aesni_driver, aesni_devclass, 0, 0); 474 MODULE_VERSION(aesni, 1); 475 MODULE_DEPEND(aesni, crypto, 1, 1, 1); 476 477 static int 478 aesni_authprepare(struct aesni_session *ses, int klen, const void *cri_key) 479 { 480 int keylen; 481 482 if (klen % 8 != 0) 483 return (EINVAL); 484 keylen = klen / 8; 485 if (keylen > sizeof(ses->hmac_key)) 486 return (EINVAL); 487 if (ses->auth_algo == CRYPTO_SHA1 && keylen > 0) 488 return (EINVAL); 489 memcpy(ses->hmac_key, cri_key, keylen); 490 return (0); 491 } 492 493 static int 494 aesni_cipher_setup(struct aesni_session *ses, struct cryptoini *encini, 495 struct cryptoini *authini) 496 { 497 struct fpu_kern_ctx *ctx; 498 int kt, ctxidx, error; 499 500 switch (ses->auth_algo) { 501 case CRYPTO_SHA1: 502 case CRYPTO_SHA1_HMAC: 503 case CRYPTO_SHA2_224: 504 case CRYPTO_SHA2_224_HMAC: 505 case CRYPTO_SHA2_256: 506 case CRYPTO_SHA2_256_HMAC: 507 error = aesni_authprepare(ses, authini->cri_klen, 508 authini->cri_key); 509 if (error != 0) 510 return (error); 511 ses->mlen = authini->cri_mlen; 512 } 513 514 kt = is_fpu_kern_thread(0) || (encini == NULL); 515 if (!kt) { 516 ACQUIRE_CTX(ctxidx, ctx); 517 fpu_kern_enter(curthread, ctx, 518 FPU_KERN_NORMAL | FPU_KERN_KTHR); 519 } 520 521 error = 0; 522 if (encini != NULL) 523 error = aesni_cipher_setup_common(ses, encini->cri_key, 524 encini->cri_klen); 525 526 if (!kt) { 527 fpu_kern_leave(curthread, ctx); 528 RELEASE_CTX(ctxidx, ctx); 529 } 530 return (error); 531 } 532 533 static int 534 intel_sha1_update(void *vctx, const void *vdata, u_int datalen) 535 { 536 struct sha1_ctxt *ctx = vctx; 537 const char *data = vdata; 538 size_t gaplen; 539 size_t gapstart; 540 size_t off; 541 size_t copysiz; 542 u_int blocks; 543 544 off = 0; 545 /* Do any aligned blocks without redundant copying. */ 546 if (datalen >= 64 && ctx->count % 64 == 0) { 547 blocks = datalen / 64; 548 ctx->c.b64[0] += blocks * 64 * 8; 549 intel_sha1_step(ctx->h.b32, data + off, blocks); 550 off += blocks * 64; 551 } 552 553 while (off < datalen) { 554 gapstart = ctx->count % 64; 555 gaplen = 64 - gapstart; 556 557 copysiz = (gaplen < datalen - off) ? gaplen : datalen - off; 558 bcopy(&data[off], &ctx->m.b8[gapstart], copysiz); 559 ctx->count += copysiz; 560 ctx->count %= 64; 561 ctx->c.b64[0] += copysiz * 8; 562 if (ctx->count % 64 == 0) 563 intel_sha1_step(ctx->h.b32, (void *)ctx->m.b8, 1); 564 off += copysiz; 565 } 566 return (0); 567 } 568 569 static void 570 SHA1_Init_fn(void *ctx) 571 { 572 sha1_init(ctx); 573 } 574 575 static void 576 SHA1_Finalize_fn(void *digest, void *ctx) 577 { 578 sha1_result(ctx, digest); 579 } 580 581 static int 582 intel_sha256_update(void *vctx, const void *vdata, u_int len) 583 { 584 SHA256_CTX *ctx = vctx; 585 uint64_t bitlen; 586 uint32_t r; 587 u_int blocks; 588 const unsigned char *src = vdata; 589 590 /* Number of bytes left in the buffer from previous updates */ 591 r = (ctx->count >> 3) & 0x3f; 592 593 /* Convert the length into a number of bits */ 594 bitlen = len << 3; 595 596 /* Update number of bits */ 597 ctx->count += bitlen; 598 599 /* Handle the case where we don't need to perform any transforms */ 600 if (len < 64 - r) { 601 memcpy(&ctx->buf[r], src, len); 602 return (0); 603 } 604 605 /* Finish the current block */ 606 memcpy(&ctx->buf[r], src, 64 - r); 607 intel_sha256_step(ctx->state, ctx->buf, 1); 608 src += 64 - r; 609 len -= 64 - r; 610 611 /* Perform complete blocks */ 612 if (len >= 64) { 613 blocks = len / 64; 614 intel_sha256_step(ctx->state, src, blocks); 615 src += blocks * 64; 616 len -= blocks * 64; 617 } 618 619 /* Copy left over data into buffer */ 620 memcpy(ctx->buf, src, len); 621 return (0); 622 } 623 624 static void 625 SHA224_Init_fn(void *ctx) 626 { 627 SHA224_Init(ctx); 628 } 629 630 static void 631 SHA224_Finalize_fn(void *digest, void *ctx) 632 { 633 SHA224_Final(digest, ctx); 634 } 635 636 static void 637 SHA256_Init_fn(void *ctx) 638 { 639 SHA256_Init(ctx); 640 } 641 642 static void 643 SHA256_Finalize_fn(void *digest, void *ctx) 644 { 645 SHA256_Final(digest, ctx); 646 } 647 648 /* 649 * Compute the HASH( (key ^ xorbyte) || buf ) 650 */ 651 static void 652 hmac_internal(void *ctx, uint32_t *res, 653 int (*update)(void *, const void *, u_int), 654 void (*finalize)(void *, void *), uint8_t *key, uint8_t xorbyte, 655 const void *buf, size_t off, size_t buflen, int crpflags) 656 { 657 size_t i; 658 659 for (i = 0; i < 64; i++) 660 key[i] ^= xorbyte; 661 update(ctx, key, 64); 662 for (i = 0; i < 64; i++) 663 key[i] ^= xorbyte; 664 665 crypto_apply(crpflags, __DECONST(void *, buf), off, buflen, 666 __DECONST(int (*)(void *, void *, u_int), update), ctx); 667 finalize(res, ctx); 668 } 669 670 static int 671 aesni_cipher_process(struct aesni_session *ses, struct cryptodesc *enccrd, 672 struct cryptodesc *authcrd, struct cryptop *crp) 673 { 674 struct fpu_kern_ctx *ctx; 675 int error, ctxidx; 676 bool kt; 677 678 if (enccrd != NULL) { 679 if ((enccrd->crd_alg == CRYPTO_AES_ICM || 680 enccrd->crd_alg == CRYPTO_AES_CCM_16 || 681 enccrd->crd_alg == CRYPTO_AES_NIST_GCM_16) && 682 (enccrd->crd_flags & CRD_F_IV_EXPLICIT) == 0) 683 return (EINVAL); 684 } 685 686 ctx = NULL; 687 ctxidx = 0; 688 error = 0; 689 kt = is_fpu_kern_thread(0); 690 if (!kt) { 691 ACQUIRE_CTX(ctxidx, ctx); 692 fpu_kern_enter(curthread, ctx, 693 FPU_KERN_NORMAL | FPU_KERN_KTHR); 694 } 695 696 /* Do work */ 697 if (enccrd != NULL && authcrd != NULL) { 698 /* Perform the first operation */ 699 if (crp->crp_desc == enccrd) 700 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 701 else 702 error = aesni_cipher_mac(ses, authcrd, crp); 703 if (error != 0) 704 goto out; 705 /* Perform the second operation */ 706 if (crp->crp_desc == enccrd) 707 error = aesni_cipher_mac(ses, authcrd, crp); 708 else 709 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 710 } else if (enccrd != NULL) 711 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp); 712 else 713 error = aesni_cipher_mac(ses, authcrd, crp); 714 715 if (error != 0) 716 goto out; 717 718 out: 719 if (!kt) { 720 fpu_kern_leave(curthread, ctx); 721 RELEASE_CTX(ctxidx, ctx); 722 } 723 return (error); 724 } 725 726 static int 727 aesni_cipher_crypt(struct aesni_session *ses, struct cryptodesc *enccrd, 728 struct cryptodesc *authcrd, struct cryptop *crp) 729 { 730 uint8_t iv[AES_BLOCK_LEN], tag[GMAC_DIGEST_LEN], *buf, *authbuf; 731 int error, ivlen; 732 bool encflag, allocated, authallocated; 733 734 KASSERT((ses->algo != CRYPTO_AES_NIST_GCM_16 && 735 ses->algo != CRYPTO_AES_CCM_16) || authcrd != NULL, 736 ("AES_NIST_GCM_16/AES_CCM_16 must include MAC descriptor")); 737 738 ivlen = 0; 739 authbuf = NULL; 740 741 buf = aesni_cipher_alloc(enccrd, crp, &allocated); 742 if (buf == NULL) 743 return (ENOMEM); 744 745 authallocated = false; 746 if (ses->algo == CRYPTO_AES_NIST_GCM_16 || 747 ses->algo == CRYPTO_AES_CCM_16) { 748 authbuf = aesni_cipher_alloc(authcrd, crp, &authallocated); 749 if (authbuf == NULL) { 750 error = ENOMEM; 751 goto out; 752 } 753 } 754 755 error = 0; 756 encflag = (enccrd->crd_flags & CRD_F_ENCRYPT) == CRD_F_ENCRYPT; 757 if ((enccrd->crd_flags & CRD_F_KEY_EXPLICIT) != 0) { 758 error = aesni_cipher_setup_common(ses, enccrd->crd_key, 759 enccrd->crd_klen); 760 if (error != 0) 761 goto out; 762 } 763 764 switch (enccrd->crd_alg) { 765 case CRYPTO_AES_CBC: 766 case CRYPTO_AES_ICM: 767 ivlen = AES_BLOCK_LEN; 768 break; 769 case CRYPTO_AES_XTS: 770 ivlen = 8; 771 break; 772 case CRYPTO_AES_NIST_GCM_16: 773 case CRYPTO_AES_CCM_16: 774 ivlen = 12; /* should support arbitarily larger */ 775 break; 776 } 777 778 /* Setup iv */ 779 if (encflag) { 780 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0) 781 bcopy(enccrd->crd_iv, iv, ivlen); 782 else 783 arc4rand(iv, ivlen, 0); 784 785 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) 786 crypto_copyback(crp->crp_flags, crp->crp_buf, 787 enccrd->crd_inject, ivlen, iv); 788 } else { 789 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0) 790 bcopy(enccrd->crd_iv, iv, ivlen); 791 else 792 crypto_copydata(crp->crp_flags, crp->crp_buf, 793 enccrd->crd_inject, ivlen, iv); 794 } 795 796 switch (ses->algo) { 797 case CRYPTO_AES_CBC: 798 if (encflag) 799 aesni_encrypt_cbc(ses->rounds, ses->enc_schedule, 800 enccrd->crd_len, buf, buf, iv); 801 else 802 aesni_decrypt_cbc(ses->rounds, ses->dec_schedule, 803 enccrd->crd_len, buf, iv); 804 break; 805 case CRYPTO_AES_ICM: 806 /* encryption & decryption are the same */ 807 aesni_encrypt_icm(ses->rounds, ses->enc_schedule, 808 enccrd->crd_len, buf, buf, iv); 809 break; 810 case CRYPTO_AES_XTS: 811 if (encflag) 812 aesni_encrypt_xts(ses->rounds, ses->enc_schedule, 813 ses->xts_schedule, enccrd->crd_len, buf, buf, 814 iv); 815 else 816 aesni_decrypt_xts(ses->rounds, ses->dec_schedule, 817 ses->xts_schedule, enccrd->crd_len, buf, buf, 818 iv); 819 break; 820 case CRYPTO_AES_NIST_GCM_16: 821 if (!encflag) 822 crypto_copydata(crp->crp_flags, crp->crp_buf, 823 authcrd->crd_inject, sizeof(tag), tag); 824 else 825 bzero(tag, sizeof tag); 826 827 if (encflag) { 828 AES_GCM_encrypt(buf, buf, authbuf, iv, tag, 829 enccrd->crd_len, authcrd->crd_len, ivlen, 830 ses->enc_schedule, ses->rounds); 831 832 if (authcrd != NULL) 833 crypto_copyback(crp->crp_flags, crp->crp_buf, 834 authcrd->crd_inject, sizeof(tag), tag); 835 } else { 836 if (!AES_GCM_decrypt(buf, buf, authbuf, iv, tag, 837 enccrd->crd_len, authcrd->crd_len, ivlen, 838 ses->enc_schedule, ses->rounds)) 839 error = EBADMSG; 840 } 841 break; 842 case CRYPTO_AES_CCM_16: 843 if (!encflag) 844 crypto_copydata(crp->crp_flags, crp->crp_buf, 845 authcrd->crd_inject, sizeof(tag), tag); 846 else 847 bzero(tag, sizeof tag); 848 if (encflag) { 849 AES_CCM_encrypt(buf, buf, authbuf, iv, tag, 850 enccrd->crd_len, authcrd->crd_len, ivlen, 851 ses->enc_schedule, ses->rounds); 852 if (authcrd != NULL) 853 crypto_copyback(crp->crp_flags, crp->crp_buf, 854 authcrd->crd_inject, sizeof(tag), tag); 855 } else { 856 if (!AES_CCM_decrypt(buf, buf, authbuf, iv, tag, 857 enccrd->crd_len, authcrd->crd_len, ivlen, 858 ses->enc_schedule, ses->rounds)) 859 error = EBADMSG; 860 } 861 break; 862 } 863 if (allocated && error == 0) 864 crypto_copyback(crp->crp_flags, crp->crp_buf, enccrd->crd_skip, 865 enccrd->crd_len, buf); 866 867 out: 868 if (allocated) { 869 explicit_bzero(buf, enccrd->crd_len); 870 free(buf, M_AESNI); 871 } 872 if (authallocated) { 873 explicit_bzero(authbuf, authcrd->crd_len); 874 free(authbuf, M_AESNI); 875 } 876 return (error); 877 } 878 879 static int 880 aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd, 881 struct cryptop *crp) 882 { 883 union { 884 struct SHA256Context sha2 __aligned(16); 885 struct sha1_ctxt sha1 __aligned(16); 886 } sctx; 887 uint32_t res[SHA2_256_HASH_LEN / sizeof(uint32_t)]; 888 int hashlen, error; 889 void *ctx; 890 void (*InitFn)(void *); 891 int (*UpdateFn)(void *, const void *, unsigned); 892 void (*FinalizeFn)(void *, void *); 893 894 bool hmac; 895 896 if ((crd->crd_flags & ~CRD_F_KEY_EXPLICIT) != 0) { 897 CRYPTDEB("%s: Unsupported MAC flags: 0x%x", __func__, 898 (crd->crd_flags & ~CRD_F_KEY_EXPLICIT)); 899 return (EINVAL); 900 } 901 if ((crd->crd_flags & CRD_F_KEY_EXPLICIT) != 0) { 902 error = aesni_authprepare(ses, crd->crd_klen, crd->crd_key); 903 if (error != 0) 904 return (error); 905 } 906 907 hmac = false; 908 switch (ses->auth_algo) { 909 case CRYPTO_SHA1_HMAC: 910 hmac = true; 911 /* FALLTHROUGH */ 912 case CRYPTO_SHA1: 913 hashlen = SHA1_HASH_LEN; 914 InitFn = SHA1_Init_fn; 915 UpdateFn = intel_sha1_update; 916 FinalizeFn = SHA1_Finalize_fn; 917 ctx = &sctx.sha1; 918 break; 919 920 case CRYPTO_SHA2_256_HMAC: 921 hmac = true; 922 /* FALLTHROUGH */ 923 case CRYPTO_SHA2_256: 924 hashlen = SHA2_256_HASH_LEN; 925 InitFn = SHA256_Init_fn; 926 UpdateFn = intel_sha256_update; 927 FinalizeFn = SHA256_Finalize_fn; 928 ctx = &sctx.sha2; 929 break; 930 931 case CRYPTO_SHA2_224_HMAC: 932 hmac = true; 933 /* FALLTHROUGH */ 934 case CRYPTO_SHA2_224: 935 hashlen = SHA2_224_HASH_LEN; 936 InitFn = SHA224_Init_fn; 937 UpdateFn = intel_sha256_update; 938 FinalizeFn = SHA224_Finalize_fn; 939 ctx = &sctx.sha2; 940 break; 941 default: 942 /* 943 * AES-GMAC authentication is verified while processing the 944 * enccrd 945 */ 946 return (0); 947 } 948 949 if (hmac) { 950 /* Inner hash: (K ^ IPAD) || data */ 951 InitFn(ctx); 952 hmac_internal(ctx, res, UpdateFn, FinalizeFn, ses->hmac_key, 953 0x36, crp->crp_buf, crd->crd_skip, crd->crd_len, 954 crp->crp_flags); 955 /* Outer hash: (K ^ OPAD) || inner hash */ 956 InitFn(ctx); 957 hmac_internal(ctx, res, UpdateFn, FinalizeFn, ses->hmac_key, 958 0x5C, res, 0, hashlen, 0); 959 } else { 960 InitFn(ctx); 961 crypto_apply(crp->crp_flags, crp->crp_buf, crd->crd_skip, 962 crd->crd_len, __DECONST(int (*)(void *, void *, u_int), 963 UpdateFn), ctx); 964 FinalizeFn(res, ctx); 965 } 966 967 if (ses->mlen != 0 && ses->mlen < hashlen) 968 hashlen = ses->mlen; 969 970 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, hashlen, 971 (void *)res); 972 return (0); 973 } 974