1*3a9fd824SRoger Pau Monné /* 2*3a9fd824SRoger Pau Monné * Copyright (c) 2016, Citrix Systems Inc 3*3a9fd824SRoger Pau Monné * 4*3a9fd824SRoger Pau Monné * Permission is hereby granted, free of charge, to any person obtaining a copy 5*3a9fd824SRoger Pau Monné * of this software and associated documentation files (the "Software"), to 6*3a9fd824SRoger Pau Monné * deal in the Software without restriction, including without limitation the 7*3a9fd824SRoger Pau Monné * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8*3a9fd824SRoger Pau Monné * sell copies of the Software, and to permit persons to whom the Software is 9*3a9fd824SRoger Pau Monné * furnished to do so, subject to the following conditions: 10*3a9fd824SRoger Pau Monné * 11*3a9fd824SRoger Pau Monné * The above copyright notice and this permission notice shall be included in 12*3a9fd824SRoger Pau Monné * all copies or substantial portions of the Software. 13*3a9fd824SRoger Pau Monné * 14*3a9fd824SRoger Pau Monné * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*3a9fd824SRoger Pau Monné * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*3a9fd824SRoger Pau Monné * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17*3a9fd824SRoger Pau Monné * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18*3a9fd824SRoger Pau Monné * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19*3a9fd824SRoger Pau Monné * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20*3a9fd824SRoger Pau Monné * DEALINGS IN THE SOFTWARE. 21*3a9fd824SRoger Pau Monné * 22*3a9fd824SRoger Pau Monné */ 23*3a9fd824SRoger Pau Monné 24*3a9fd824SRoger Pau Monné #ifndef __XEN_PUBLIC_HVM_DM_OP_H__ 25*3a9fd824SRoger Pau Monné #define __XEN_PUBLIC_HVM_DM_OP_H__ 26*3a9fd824SRoger Pau Monné 27*3a9fd824SRoger Pau Monné #include "../xen.h" 28*3a9fd824SRoger Pau Monné #include "../event_channel.h" 29*3a9fd824SRoger Pau Monné 30*3a9fd824SRoger Pau Monné #ifndef uint64_aligned_t 31*3a9fd824SRoger Pau Monné #define uint64_aligned_t uint64_t 32*3a9fd824SRoger Pau Monné #endif 33*3a9fd824SRoger Pau Monné 34*3a9fd824SRoger Pau Monné /* 35*3a9fd824SRoger Pau Monné * IOREQ Servers 36*3a9fd824SRoger Pau Monné * 37*3a9fd824SRoger Pau Monné * The interface between an I/O emulator an Xen is called an IOREQ Server. 38*3a9fd824SRoger Pau Monné * A domain supports a single 'legacy' IOREQ Server which is instantiated if 39*3a9fd824SRoger Pau Monné * parameter... 40*3a9fd824SRoger Pau Monné * 41*3a9fd824SRoger Pau Monné * HVM_PARAM_IOREQ_PFN is read (to get the gfn containing the synchronous 42*3a9fd824SRoger Pau Monné * ioreq structures), or... 43*3a9fd824SRoger Pau Monné * HVM_PARAM_BUFIOREQ_PFN is read (to get the gfn containing the buffered 44*3a9fd824SRoger Pau Monné * ioreq ring), or... 45*3a9fd824SRoger Pau Monné * HVM_PARAM_BUFIOREQ_EVTCHN is read (to get the event channel that Xen uses 46*3a9fd824SRoger Pau Monné * to request buffered I/O emulation). 47*3a9fd824SRoger Pau Monné * 48*3a9fd824SRoger Pau Monné * The following hypercalls facilitate the creation of IOREQ Servers for 49*3a9fd824SRoger Pau Monné * 'secondary' emulators which are invoked to implement port I/O, memory, or 50*3a9fd824SRoger Pau Monné * PCI config space ranges which they explicitly register. 51*3a9fd824SRoger Pau Monné */ 52*3a9fd824SRoger Pau Monné 53*3a9fd824SRoger Pau Monné typedef uint16_t ioservid_t; 54*3a9fd824SRoger Pau Monné 55*3a9fd824SRoger Pau Monné /* 56*3a9fd824SRoger Pau Monné * XEN_DMOP_create_ioreq_server: Instantiate a new IOREQ Server for a 57*3a9fd824SRoger Pau Monné * secondary emulator. 58*3a9fd824SRoger Pau Monné * 59*3a9fd824SRoger Pau Monné * The <id> handed back is unique for target domain. The valur of 60*3a9fd824SRoger Pau Monné * <handle_bufioreq> should be one of HVM_IOREQSRV_BUFIOREQ_* defined in 61*3a9fd824SRoger Pau Monné * hvm_op.h. If the value is HVM_IOREQSRV_BUFIOREQ_OFF then the buffered 62*3a9fd824SRoger Pau Monné * ioreq ring will not be allocated and hence all emulation requests to 63*3a9fd824SRoger Pau Monné * this server will be synchronous. 64*3a9fd824SRoger Pau Monné */ 65*3a9fd824SRoger Pau Monné #define XEN_DMOP_create_ioreq_server 1 66*3a9fd824SRoger Pau Monné 67*3a9fd824SRoger Pau Monné struct xen_dm_op_create_ioreq_server { 68*3a9fd824SRoger Pau Monné /* IN - should server handle buffered ioreqs */ 69*3a9fd824SRoger Pau Monné uint8_t handle_bufioreq; 70*3a9fd824SRoger Pau Monné uint8_t pad[3]; 71*3a9fd824SRoger Pau Monné /* OUT - server id */ 72*3a9fd824SRoger Pau Monné ioservid_t id; 73*3a9fd824SRoger Pau Monné }; 74*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_create_ioreq_server xen_dm_op_create_ioreq_server_t; 75*3a9fd824SRoger Pau Monné 76*3a9fd824SRoger Pau Monné /* 77*3a9fd824SRoger Pau Monné * XEN_DMOP_get_ioreq_server_info: Get all the information necessary to 78*3a9fd824SRoger Pau Monné * access IOREQ Server <id>. 79*3a9fd824SRoger Pau Monné * 80*3a9fd824SRoger Pau Monné * If the IOREQ Server is handling buffered emulation requests, the 81*3a9fd824SRoger Pau Monné * emulator needs to bind to event channel <bufioreq_port> to listen for 82*3a9fd824SRoger Pau Monné * them. (The event channels used for synchronous emulation requests are 83*3a9fd824SRoger Pau Monné * specified in the per-CPU ioreq structures). 84*3a9fd824SRoger Pau Monné * In addition, if the XENMEM_acquire_resource memory op cannot be used, 85*3a9fd824SRoger Pau Monné * the emulator will need to map the synchronous ioreq structures and 86*3a9fd824SRoger Pau Monné * buffered ioreq ring (if it exists) from guest memory. If <flags> does 87*3a9fd824SRoger Pau Monné * not contain XEN_DMOP_no_gfns then these pages will be made available and 88*3a9fd824SRoger Pau Monné * the frame numbers passed back in gfns <ioreq_gfn> and <bufioreq_gfn> 89*3a9fd824SRoger Pau Monné * respectively. (If the IOREQ Server is not handling buffered emulation 90*3a9fd824SRoger Pau Monné * only <ioreq_gfn> will be valid). 91*3a9fd824SRoger Pau Monné * 92*3a9fd824SRoger Pau Monné * NOTE: To access the synchronous ioreq structures and buffered ioreq 93*3a9fd824SRoger Pau Monné * ring, it is preferable to use the XENMEM_acquire_resource memory 94*3a9fd824SRoger Pau Monné * op specifying resource type XENMEM_resource_ioreq_server. 95*3a9fd824SRoger Pau Monné */ 96*3a9fd824SRoger Pau Monné #define XEN_DMOP_get_ioreq_server_info 2 97*3a9fd824SRoger Pau Monné 98*3a9fd824SRoger Pau Monné struct xen_dm_op_get_ioreq_server_info { 99*3a9fd824SRoger Pau Monné /* IN - server id */ 100*3a9fd824SRoger Pau Monné ioservid_t id; 101*3a9fd824SRoger Pau Monné /* IN - flags */ 102*3a9fd824SRoger Pau Monné uint16_t flags; 103*3a9fd824SRoger Pau Monné 104*3a9fd824SRoger Pau Monné #define _XEN_DMOP_no_gfns 0 105*3a9fd824SRoger Pau Monné #define XEN_DMOP_no_gfns (1u << _XEN_DMOP_no_gfns) 106*3a9fd824SRoger Pau Monné 107*3a9fd824SRoger Pau Monné /* OUT - buffered ioreq port */ 108*3a9fd824SRoger Pau Monné evtchn_port_t bufioreq_port; 109*3a9fd824SRoger Pau Monné /* OUT - sync ioreq gfn (see block comment above) */ 110*3a9fd824SRoger Pau Monné uint64_aligned_t ioreq_gfn; 111*3a9fd824SRoger Pau Monné /* OUT - buffered ioreq gfn (see block comment above)*/ 112*3a9fd824SRoger Pau Monné uint64_aligned_t bufioreq_gfn; 113*3a9fd824SRoger Pau Monné }; 114*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_get_ioreq_server_info xen_dm_op_get_ioreq_server_info_t; 115*3a9fd824SRoger Pau Monné 116*3a9fd824SRoger Pau Monné /* 117*3a9fd824SRoger Pau Monné * XEN_DMOP_map_io_range_to_ioreq_server: Register an I/O range for 118*3a9fd824SRoger Pau Monné * emulation by the client of 119*3a9fd824SRoger Pau Monné * IOREQ Server <id>. 120*3a9fd824SRoger Pau Monné * XEN_DMOP_unmap_io_range_from_ioreq_server: Deregister an I/O range 121*3a9fd824SRoger Pau Monné * previously registered for 122*3a9fd824SRoger Pau Monné * emulation by the client of 123*3a9fd824SRoger Pau Monné * IOREQ Server <id>. 124*3a9fd824SRoger Pau Monné * 125*3a9fd824SRoger Pau Monné * There are three types of I/O that can be emulated: port I/O, memory 126*3a9fd824SRoger Pau Monné * accesses and PCI config space accesses. The <type> field denotes which 127*3a9fd824SRoger Pau Monné * type of range* the <start> and <end> (inclusive) fields are specifying. 128*3a9fd824SRoger Pau Monné * PCI config space ranges are specified by segment/bus/device/function 129*3a9fd824SRoger Pau Monné * values which should be encoded using the DMOP_PCI_SBDF helper macro 130*3a9fd824SRoger Pau Monné * below. 131*3a9fd824SRoger Pau Monné * 132*3a9fd824SRoger Pau Monné * NOTE: unless an emulation request falls entirely within a range mapped 133*3a9fd824SRoger Pau Monné * by a secondary emulator, it will not be passed to that emulator. 134*3a9fd824SRoger Pau Monné */ 135*3a9fd824SRoger Pau Monné #define XEN_DMOP_map_io_range_to_ioreq_server 3 136*3a9fd824SRoger Pau Monné #define XEN_DMOP_unmap_io_range_from_ioreq_server 4 137*3a9fd824SRoger Pau Monné 138*3a9fd824SRoger Pau Monné struct xen_dm_op_ioreq_server_range { 139*3a9fd824SRoger Pau Monné /* IN - server id */ 140*3a9fd824SRoger Pau Monné ioservid_t id; 141*3a9fd824SRoger Pau Monné uint16_t pad; 142*3a9fd824SRoger Pau Monné /* IN - type of range */ 143*3a9fd824SRoger Pau Monné uint32_t type; 144*3a9fd824SRoger Pau Monné # define XEN_DMOP_IO_RANGE_PORT 0 /* I/O port range */ 145*3a9fd824SRoger Pau Monné # define XEN_DMOP_IO_RANGE_MEMORY 1 /* MMIO range */ 146*3a9fd824SRoger Pau Monné # define XEN_DMOP_IO_RANGE_PCI 2 /* PCI segment/bus/dev/func range */ 147*3a9fd824SRoger Pau Monné /* IN - inclusive start and end of range */ 148*3a9fd824SRoger Pau Monné uint64_aligned_t start, end; 149*3a9fd824SRoger Pau Monné }; 150*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_ioreq_server_range xen_dm_op_ioreq_server_range_t; 151*3a9fd824SRoger Pau Monné 152*3a9fd824SRoger Pau Monné #define XEN_DMOP_PCI_SBDF(s,b,d,f) \ 153*3a9fd824SRoger Pau Monné ((((s) & 0xffff) << 16) | \ 154*3a9fd824SRoger Pau Monné (((b) & 0xff) << 8) | \ 155*3a9fd824SRoger Pau Monné (((d) & 0x1f) << 3) | \ 156*3a9fd824SRoger Pau Monné ((f) & 0x07)) 157*3a9fd824SRoger Pau Monné 158*3a9fd824SRoger Pau Monné /* 159*3a9fd824SRoger Pau Monné * XEN_DMOP_set_ioreq_server_state: Enable or disable the IOREQ Server <id> 160*3a9fd824SRoger Pau Monné * 161*3a9fd824SRoger Pau Monné * The IOREQ Server will not be passed any emulation requests until it is 162*3a9fd824SRoger Pau Monné * in the enabled state. 163*3a9fd824SRoger Pau Monné * Note that the contents of the ioreq_gfn and bufioreq_gfn (see 164*3a9fd824SRoger Pau Monné * XEN_DMOP_get_ioreq_server_info) are not meaningful until the IOREQ Server 165*3a9fd824SRoger Pau Monné * is in the enabled state. 166*3a9fd824SRoger Pau Monné */ 167*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_ioreq_server_state 5 168*3a9fd824SRoger Pau Monné 169*3a9fd824SRoger Pau Monné struct xen_dm_op_set_ioreq_server_state { 170*3a9fd824SRoger Pau Monné /* IN - server id */ 171*3a9fd824SRoger Pau Monné ioservid_t id; 172*3a9fd824SRoger Pau Monné /* IN - enabled? */ 173*3a9fd824SRoger Pau Monné uint8_t enabled; 174*3a9fd824SRoger Pau Monné uint8_t pad; 175*3a9fd824SRoger Pau Monné }; 176*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_ioreq_server_state xen_dm_op_set_ioreq_server_state_t; 177*3a9fd824SRoger Pau Monné 178*3a9fd824SRoger Pau Monné /* 179*3a9fd824SRoger Pau Monné * XEN_DMOP_destroy_ioreq_server: Destroy the IOREQ Server <id>. 180*3a9fd824SRoger Pau Monné * 181*3a9fd824SRoger Pau Monné * Any registered I/O ranges will be automatically deregistered. 182*3a9fd824SRoger Pau Monné */ 183*3a9fd824SRoger Pau Monné #define XEN_DMOP_destroy_ioreq_server 6 184*3a9fd824SRoger Pau Monné 185*3a9fd824SRoger Pau Monné struct xen_dm_op_destroy_ioreq_server { 186*3a9fd824SRoger Pau Monné /* IN - server id */ 187*3a9fd824SRoger Pau Monné ioservid_t id; 188*3a9fd824SRoger Pau Monné uint16_t pad; 189*3a9fd824SRoger Pau Monné }; 190*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_destroy_ioreq_server xen_dm_op_destroy_ioreq_server_t; 191*3a9fd824SRoger Pau Monné 192*3a9fd824SRoger Pau Monné /* 193*3a9fd824SRoger Pau Monné * XEN_DMOP_track_dirty_vram: Track modifications to the specified pfn 194*3a9fd824SRoger Pau Monné * range. 195*3a9fd824SRoger Pau Monné * 196*3a9fd824SRoger Pau Monné * NOTE: The bitmap passed back to the caller is passed in a 197*3a9fd824SRoger Pau Monné * secondary buffer. 198*3a9fd824SRoger Pau Monné */ 199*3a9fd824SRoger Pau Monné #define XEN_DMOP_track_dirty_vram 7 200*3a9fd824SRoger Pau Monné 201*3a9fd824SRoger Pau Monné struct xen_dm_op_track_dirty_vram { 202*3a9fd824SRoger Pau Monné /* IN - number of pages to be tracked */ 203*3a9fd824SRoger Pau Monné uint32_t nr; 204*3a9fd824SRoger Pau Monné uint32_t pad; 205*3a9fd824SRoger Pau Monné /* IN - first pfn to track */ 206*3a9fd824SRoger Pau Monné uint64_aligned_t first_pfn; 207*3a9fd824SRoger Pau Monné }; 208*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_track_dirty_vram xen_dm_op_track_dirty_vram_t; 209*3a9fd824SRoger Pau Monné 210*3a9fd824SRoger Pau Monné /* 211*3a9fd824SRoger Pau Monné * XEN_DMOP_set_pci_intx_level: Set the logical level of one of a domain's 212*3a9fd824SRoger Pau Monné * PCI INTx pins. 213*3a9fd824SRoger Pau Monné */ 214*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_pci_intx_level 8 215*3a9fd824SRoger Pau Monné 216*3a9fd824SRoger Pau Monné struct xen_dm_op_set_pci_intx_level { 217*3a9fd824SRoger Pau Monné /* IN - PCI INTx identification (domain:bus:device:intx) */ 218*3a9fd824SRoger Pau Monné uint16_t domain; 219*3a9fd824SRoger Pau Monné uint8_t bus, device, intx; 220*3a9fd824SRoger Pau Monné /* IN - Level: 0 -> deasserted, 1 -> asserted */ 221*3a9fd824SRoger Pau Monné uint8_t level; 222*3a9fd824SRoger Pau Monné }; 223*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_pci_intx_level xen_dm_op_set_pci_intx_level_t; 224*3a9fd824SRoger Pau Monné 225*3a9fd824SRoger Pau Monné /* 226*3a9fd824SRoger Pau Monné * XEN_DMOP_set_isa_irq_level: Set the logical level of a one of a domain's 227*3a9fd824SRoger Pau Monné * ISA IRQ lines. 228*3a9fd824SRoger Pau Monné */ 229*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_isa_irq_level 9 230*3a9fd824SRoger Pau Monné 231*3a9fd824SRoger Pau Monné struct xen_dm_op_set_isa_irq_level { 232*3a9fd824SRoger Pau Monné /* IN - ISA IRQ (0-15) */ 233*3a9fd824SRoger Pau Monné uint8_t isa_irq; 234*3a9fd824SRoger Pau Monné /* IN - Level: 0 -> deasserted, 1 -> asserted */ 235*3a9fd824SRoger Pau Monné uint8_t level; 236*3a9fd824SRoger Pau Monné }; 237*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_isa_irq_level xen_dm_op_set_isa_irq_level_t; 238*3a9fd824SRoger Pau Monné 239*3a9fd824SRoger Pau Monné /* 240*3a9fd824SRoger Pau Monné * XEN_DMOP_set_pci_link_route: Map a PCI INTx line to an IRQ line. 241*3a9fd824SRoger Pau Monné */ 242*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_pci_link_route 10 243*3a9fd824SRoger Pau Monné 244*3a9fd824SRoger Pau Monné struct xen_dm_op_set_pci_link_route { 245*3a9fd824SRoger Pau Monné /* PCI INTx line (0-3) */ 246*3a9fd824SRoger Pau Monné uint8_t link; 247*3a9fd824SRoger Pau Monné /* ISA IRQ (1-15) or 0 -> disable link */ 248*3a9fd824SRoger Pau Monné uint8_t isa_irq; 249*3a9fd824SRoger Pau Monné }; 250*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_pci_link_route xen_dm_op_set_pci_link_route_t; 251*3a9fd824SRoger Pau Monné 252*3a9fd824SRoger Pau Monné /* 253*3a9fd824SRoger Pau Monné * XEN_DMOP_modified_memory: Notify that a set of pages were modified by 254*3a9fd824SRoger Pau Monné * an emulator. 255*3a9fd824SRoger Pau Monné * 256*3a9fd824SRoger Pau Monné * DMOP buf 1 contains an array of xen_dm_op_modified_memory_extent with 257*3a9fd824SRoger Pau Monné * @nr_extents entries. 258*3a9fd824SRoger Pau Monné * 259*3a9fd824SRoger Pau Monné * On error, @nr_extents will contain the index+1 of the extent that 260*3a9fd824SRoger Pau Monné * had the error. It is not defined if or which pages may have been 261*3a9fd824SRoger Pau Monné * marked as dirty, in this event. 262*3a9fd824SRoger Pau Monné */ 263*3a9fd824SRoger Pau Monné #define XEN_DMOP_modified_memory 11 264*3a9fd824SRoger Pau Monné 265*3a9fd824SRoger Pau Monné struct xen_dm_op_modified_memory { 266*3a9fd824SRoger Pau Monné /* 267*3a9fd824SRoger Pau Monné * IN - Number of extents to be processed 268*3a9fd824SRoger Pau Monné * OUT -returns n+1 for failing extent 269*3a9fd824SRoger Pau Monné */ 270*3a9fd824SRoger Pau Monné uint32_t nr_extents; 271*3a9fd824SRoger Pau Monné /* IN/OUT - Must be set to 0 */ 272*3a9fd824SRoger Pau Monné uint32_t opaque; 273*3a9fd824SRoger Pau Monné }; 274*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_modified_memory xen_dm_op_modified_memory_t; 275*3a9fd824SRoger Pau Monné 276*3a9fd824SRoger Pau Monné struct xen_dm_op_modified_memory_extent { 277*3a9fd824SRoger Pau Monné /* IN - number of contiguous pages modified */ 278*3a9fd824SRoger Pau Monné uint32_t nr; 279*3a9fd824SRoger Pau Monné uint32_t pad; 280*3a9fd824SRoger Pau Monné /* IN - first pfn modified */ 281*3a9fd824SRoger Pau Monné uint64_aligned_t first_pfn; 282*3a9fd824SRoger Pau Monné }; 283*3a9fd824SRoger Pau Monné 284*3a9fd824SRoger Pau Monné /* 285*3a9fd824SRoger Pau Monné * XEN_DMOP_set_mem_type: Notify that a region of memory is to be treated 286*3a9fd824SRoger Pau Monné * in a specific way. (See definition of 287*3a9fd824SRoger Pau Monné * hvmmem_type_t). 288*3a9fd824SRoger Pau Monné * 289*3a9fd824SRoger Pau Monné * NOTE: In the event of a continuation (return code -ERESTART), the 290*3a9fd824SRoger Pau Monné * @first_pfn is set to the value of the pfn of the remaining 291*3a9fd824SRoger Pau Monné * region and @nr reduced to the size of the remaining region. 292*3a9fd824SRoger Pau Monné */ 293*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_mem_type 12 294*3a9fd824SRoger Pau Monné 295*3a9fd824SRoger Pau Monné struct xen_dm_op_set_mem_type { 296*3a9fd824SRoger Pau Monné /* IN - number of contiguous pages */ 297*3a9fd824SRoger Pau Monné uint32_t nr; 298*3a9fd824SRoger Pau Monné /* IN - new hvmmem_type_t of region */ 299*3a9fd824SRoger Pau Monné uint16_t mem_type; 300*3a9fd824SRoger Pau Monné uint16_t pad; 301*3a9fd824SRoger Pau Monné /* IN - first pfn in region */ 302*3a9fd824SRoger Pau Monné uint64_aligned_t first_pfn; 303*3a9fd824SRoger Pau Monné }; 304*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_mem_type xen_dm_op_set_mem_type_t; 305*3a9fd824SRoger Pau Monné 306*3a9fd824SRoger Pau Monné /* 307*3a9fd824SRoger Pau Monné * XEN_DMOP_inject_event: Inject an event into a VCPU, which will 308*3a9fd824SRoger Pau Monné * get taken up when it is next scheduled. 309*3a9fd824SRoger Pau Monné * 310*3a9fd824SRoger Pau Monné * Note that the caller should know enough of the state of the CPU before 311*3a9fd824SRoger Pau Monné * injecting, to know what the effect of injecting the event will be. 312*3a9fd824SRoger Pau Monné */ 313*3a9fd824SRoger Pau Monné #define XEN_DMOP_inject_event 13 314*3a9fd824SRoger Pau Monné 315*3a9fd824SRoger Pau Monné struct xen_dm_op_inject_event { 316*3a9fd824SRoger Pau Monné /* IN - index of vCPU */ 317*3a9fd824SRoger Pau Monné uint32_t vcpuid; 318*3a9fd824SRoger Pau Monné /* IN - interrupt vector */ 319*3a9fd824SRoger Pau Monné uint8_t vector; 320*3a9fd824SRoger Pau Monné /* IN - event type (DMOP_EVENT_* ) */ 321*3a9fd824SRoger Pau Monné uint8_t type; 322*3a9fd824SRoger Pau Monné /* NB. This enumeration precisely matches hvm.h:X86_EVENTTYPE_* */ 323*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_ext_int 0 /* external interrupt */ 324*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_nmi 2 /* nmi */ 325*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_hw_exc 3 /* hardware exception */ 326*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_sw_int 4 /* software interrupt (CD nn) */ 327*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_pri_sw_exc 5 /* ICEBP (F1) */ 328*3a9fd824SRoger Pau Monné # define XEN_DMOP_EVENT_sw_exc 6 /* INT3 (CC), INTO (CE) */ 329*3a9fd824SRoger Pau Monné /* IN - instruction length */ 330*3a9fd824SRoger Pau Monné uint8_t insn_len; 331*3a9fd824SRoger Pau Monné uint8_t pad0; 332*3a9fd824SRoger Pau Monné /* IN - error code (or ~0 to skip) */ 333*3a9fd824SRoger Pau Monné uint32_t error_code; 334*3a9fd824SRoger Pau Monné uint32_t pad1; 335*3a9fd824SRoger Pau Monné /* IN - type-specific extra data (%cr2 for #PF, pending_dbg for #DB) */ 336*3a9fd824SRoger Pau Monné uint64_aligned_t cr2; 337*3a9fd824SRoger Pau Monné }; 338*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_inject_event xen_dm_op_inject_event_t; 339*3a9fd824SRoger Pau Monné 340*3a9fd824SRoger Pau Monné /* 341*3a9fd824SRoger Pau Monné * XEN_DMOP_inject_msi: Inject an MSI for an emulated device. 342*3a9fd824SRoger Pau Monné */ 343*3a9fd824SRoger Pau Monné #define XEN_DMOP_inject_msi 14 344*3a9fd824SRoger Pau Monné 345*3a9fd824SRoger Pau Monné struct xen_dm_op_inject_msi { 346*3a9fd824SRoger Pau Monné /* IN - MSI data (lower 32 bits) */ 347*3a9fd824SRoger Pau Monné uint32_t data; 348*3a9fd824SRoger Pau Monné uint32_t pad; 349*3a9fd824SRoger Pau Monné /* IN - MSI address (0xfeexxxxx) */ 350*3a9fd824SRoger Pau Monné uint64_aligned_t addr; 351*3a9fd824SRoger Pau Monné }; 352*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_inject_msi xen_dm_op_inject_msi_t; 353*3a9fd824SRoger Pau Monné 354*3a9fd824SRoger Pau Monné /* 355*3a9fd824SRoger Pau Monné * XEN_DMOP_map_mem_type_to_ioreq_server : map or unmap the IOREQ Server <id> 356*3a9fd824SRoger Pau Monné * to specific memory type <type> 357*3a9fd824SRoger Pau Monné * for specific accesses <flags> 358*3a9fd824SRoger Pau Monné * 359*3a9fd824SRoger Pau Monné * For now, flags only accept the value of XEN_DMOP_IOREQ_MEM_ACCESS_WRITE, 360*3a9fd824SRoger Pau Monné * which means only write operations are to be forwarded to an ioreq server. 361*3a9fd824SRoger Pau Monné * Support for the emulation of read operations can be added when an ioreq 362*3a9fd824SRoger Pau Monné * server has such requirement in future. 363*3a9fd824SRoger Pau Monné */ 364*3a9fd824SRoger Pau Monné #define XEN_DMOP_map_mem_type_to_ioreq_server 15 365*3a9fd824SRoger Pau Monné 366*3a9fd824SRoger Pau Monné struct xen_dm_op_map_mem_type_to_ioreq_server { 367*3a9fd824SRoger Pau Monné ioservid_t id; /* IN - ioreq server id */ 368*3a9fd824SRoger Pau Monné uint16_t type; /* IN - memory type */ 369*3a9fd824SRoger Pau Monné uint32_t flags; /* IN - types of accesses to be forwarded to the 370*3a9fd824SRoger Pau Monné ioreq server. flags with 0 means to unmap the 371*3a9fd824SRoger Pau Monné ioreq server */ 372*3a9fd824SRoger Pau Monné 373*3a9fd824SRoger Pau Monné #define XEN_DMOP_IOREQ_MEM_ACCESS_READ (1u << 0) 374*3a9fd824SRoger Pau Monné #define XEN_DMOP_IOREQ_MEM_ACCESS_WRITE (1u << 1) 375*3a9fd824SRoger Pau Monné 376*3a9fd824SRoger Pau Monné uint64_t opaque; /* IN/OUT - only used for hypercall continuation, 377*3a9fd824SRoger Pau Monné has to be set to zero by the caller */ 378*3a9fd824SRoger Pau Monné }; 379*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_map_mem_type_to_ioreq_server xen_dm_op_map_mem_type_to_ioreq_server_t; 380*3a9fd824SRoger Pau Monné 381*3a9fd824SRoger Pau Monné /* 382*3a9fd824SRoger Pau Monné * XEN_DMOP_remote_shutdown : Declare a shutdown for another domain 383*3a9fd824SRoger Pau Monné * Identical to SCHEDOP_remote_shutdown 384*3a9fd824SRoger Pau Monné */ 385*3a9fd824SRoger Pau Monné #define XEN_DMOP_remote_shutdown 16 386*3a9fd824SRoger Pau Monné 387*3a9fd824SRoger Pau Monné struct xen_dm_op_remote_shutdown { 388*3a9fd824SRoger Pau Monné uint32_t reason; /* SHUTDOWN_* => enum sched_shutdown_reason */ 389*3a9fd824SRoger Pau Monné /* (Other reason values are not blocked) */ 390*3a9fd824SRoger Pau Monné }; 391*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_remote_shutdown xen_dm_op_remote_shutdown_t; 392*3a9fd824SRoger Pau Monné 393*3a9fd824SRoger Pau Monné /* 394*3a9fd824SRoger Pau Monné * XEN_DMOP_relocate_memory : Relocate GFNs for the specified guest. 395*3a9fd824SRoger Pau Monné * Identical to XENMEM_add_to_physmap with 396*3a9fd824SRoger Pau Monné * space == XENMAPSPACE_gmfn_range. 397*3a9fd824SRoger Pau Monné */ 398*3a9fd824SRoger Pau Monné #define XEN_DMOP_relocate_memory 17 399*3a9fd824SRoger Pau Monné 400*3a9fd824SRoger Pau Monné struct xen_dm_op_relocate_memory { 401*3a9fd824SRoger Pau Monné /* All fields are IN/OUT, with their OUT state undefined. */ 402*3a9fd824SRoger Pau Monné /* Number of GFNs to process. */ 403*3a9fd824SRoger Pau Monné uint32_t size; 404*3a9fd824SRoger Pau Monné uint32_t pad; 405*3a9fd824SRoger Pau Monné /* Starting GFN to relocate. */ 406*3a9fd824SRoger Pau Monné uint64_aligned_t src_gfn; 407*3a9fd824SRoger Pau Monné /* Starting GFN where GFNs should be relocated. */ 408*3a9fd824SRoger Pau Monné uint64_aligned_t dst_gfn; 409*3a9fd824SRoger Pau Monné }; 410*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_relocate_memory xen_dm_op_relocate_memory_t; 411*3a9fd824SRoger Pau Monné 412*3a9fd824SRoger Pau Monné /* 413*3a9fd824SRoger Pau Monné * XEN_DMOP_pin_memory_cacheattr : Pin caching type of RAM space. 414*3a9fd824SRoger Pau Monné * Identical to XEN_DOMCTL_pin_mem_cacheattr. 415*3a9fd824SRoger Pau Monné */ 416*3a9fd824SRoger Pau Monné #define XEN_DMOP_pin_memory_cacheattr 18 417*3a9fd824SRoger Pau Monné 418*3a9fd824SRoger Pau Monné struct xen_dm_op_pin_memory_cacheattr { 419*3a9fd824SRoger Pau Monné uint64_aligned_t start; /* Start gfn. */ 420*3a9fd824SRoger Pau Monné uint64_aligned_t end; /* End gfn. */ 421*3a9fd824SRoger Pau Monné /* Caching types: these happen to be the same as x86 MTRR/PAT type codes. */ 422*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_UC 0 423*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_WC 1 424*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_WT 4 425*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_WP 5 426*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_WB 6 427*3a9fd824SRoger Pau Monné #define XEN_DMOP_MEM_CACHEATTR_UCM 7 428*3a9fd824SRoger Pau Monné #define XEN_DMOP_DELETE_MEM_CACHEATTR (~(uint32_t)0) 429*3a9fd824SRoger Pau Monné uint32_t type; /* XEN_DMOP_MEM_CACHEATTR_* */ 430*3a9fd824SRoger Pau Monné uint32_t pad; 431*3a9fd824SRoger Pau Monné }; 432*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_pin_memory_cacheattr xen_dm_op_pin_memory_cacheattr_t; 433*3a9fd824SRoger Pau Monné 434*3a9fd824SRoger Pau Monné /* 435*3a9fd824SRoger Pau Monné * XEN_DMOP_set_irq_level: Set the logical level of a one of a domain's 436*3a9fd824SRoger Pau Monné * IRQ lines (currently Arm only). 437*3a9fd824SRoger Pau Monné * Only SPIs are supported. 438*3a9fd824SRoger Pau Monné */ 439*3a9fd824SRoger Pau Monné #define XEN_DMOP_set_irq_level 19 440*3a9fd824SRoger Pau Monné 441*3a9fd824SRoger Pau Monné struct xen_dm_op_set_irq_level { 442*3a9fd824SRoger Pau Monné uint32_t irq; 443*3a9fd824SRoger Pau Monné /* IN - Level: 0 -> deasserted, 1 -> asserted */ 444*3a9fd824SRoger Pau Monné uint8_t level; 445*3a9fd824SRoger Pau Monné uint8_t pad[3]; 446*3a9fd824SRoger Pau Monné }; 447*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_set_irq_level xen_dm_op_set_irq_level_t; 448*3a9fd824SRoger Pau Monné 449*3a9fd824SRoger Pau Monné /* 450*3a9fd824SRoger Pau Monné * XEN_DMOP_nr_vcpus: Query the number of vCPUs a domain has. 451*3a9fd824SRoger Pau Monné * 452*3a9fd824SRoger Pau Monné * This is the number of vcpu objects allocated in Xen for the domain, and is 453*3a9fd824SRoger Pau Monné * fixed from creation time. This bound is applicable to e.g. the vcpuid 454*3a9fd824SRoger Pau Monné * parameter of XEN_DMOP_inject_event, or number of struct ioreq objects 455*3a9fd824SRoger Pau Monné * mapped via XENMEM_acquire_resource. 456*3a9fd824SRoger Pau Monné */ 457*3a9fd824SRoger Pau Monné #define XEN_DMOP_nr_vcpus 20 458*3a9fd824SRoger Pau Monné 459*3a9fd824SRoger Pau Monné struct xen_dm_op_nr_vcpus { 460*3a9fd824SRoger Pau Monné uint32_t vcpus; /* OUT */ 461*3a9fd824SRoger Pau Monné }; 462*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_nr_vcpus xen_dm_op_nr_vcpus_t; 463*3a9fd824SRoger Pau Monné 464*3a9fd824SRoger Pau Monné struct xen_dm_op { 465*3a9fd824SRoger Pau Monné uint32_t op; 466*3a9fd824SRoger Pau Monné uint32_t pad; 467*3a9fd824SRoger Pau Monné union { 468*3a9fd824SRoger Pau Monné xen_dm_op_create_ioreq_server_t create_ioreq_server; 469*3a9fd824SRoger Pau Monné xen_dm_op_get_ioreq_server_info_t get_ioreq_server_info; 470*3a9fd824SRoger Pau Monné xen_dm_op_ioreq_server_range_t map_io_range_to_ioreq_server; 471*3a9fd824SRoger Pau Monné xen_dm_op_ioreq_server_range_t unmap_io_range_from_ioreq_server; 472*3a9fd824SRoger Pau Monné xen_dm_op_set_ioreq_server_state_t set_ioreq_server_state; 473*3a9fd824SRoger Pau Monné xen_dm_op_destroy_ioreq_server_t destroy_ioreq_server; 474*3a9fd824SRoger Pau Monné xen_dm_op_track_dirty_vram_t track_dirty_vram; 475*3a9fd824SRoger Pau Monné xen_dm_op_set_pci_intx_level_t set_pci_intx_level; 476*3a9fd824SRoger Pau Monné xen_dm_op_set_isa_irq_level_t set_isa_irq_level; 477*3a9fd824SRoger Pau Monné xen_dm_op_set_irq_level_t set_irq_level; 478*3a9fd824SRoger Pau Monné xen_dm_op_set_pci_link_route_t set_pci_link_route; 479*3a9fd824SRoger Pau Monné xen_dm_op_modified_memory_t modified_memory; 480*3a9fd824SRoger Pau Monné xen_dm_op_set_mem_type_t set_mem_type; 481*3a9fd824SRoger Pau Monné xen_dm_op_inject_event_t inject_event; 482*3a9fd824SRoger Pau Monné xen_dm_op_inject_msi_t inject_msi; 483*3a9fd824SRoger Pau Monné xen_dm_op_map_mem_type_to_ioreq_server_t map_mem_type_to_ioreq_server; 484*3a9fd824SRoger Pau Monné xen_dm_op_remote_shutdown_t remote_shutdown; 485*3a9fd824SRoger Pau Monné xen_dm_op_relocate_memory_t relocate_memory; 486*3a9fd824SRoger Pau Monné xen_dm_op_pin_memory_cacheattr_t pin_memory_cacheattr; 487*3a9fd824SRoger Pau Monné xen_dm_op_nr_vcpus_t nr_vcpus; 488*3a9fd824SRoger Pau Monné } u; 489*3a9fd824SRoger Pau Monné }; 490*3a9fd824SRoger Pau Monné 491*3a9fd824SRoger Pau Monné struct xen_dm_op_buf { 492*3a9fd824SRoger Pau Monné XEN_GUEST_HANDLE(void) h; 493*3a9fd824SRoger Pau Monné xen_ulong_t size; 494*3a9fd824SRoger Pau Monné }; 495*3a9fd824SRoger Pau Monné typedef struct xen_dm_op_buf xen_dm_op_buf_t; 496*3a9fd824SRoger Pau Monné DEFINE_XEN_GUEST_HANDLE(xen_dm_op_buf_t); 497*3a9fd824SRoger Pau Monné 498*3a9fd824SRoger Pau Monné /* ` enum neg_errnoval 499*3a9fd824SRoger Pau Monné * ` HYPERVISOR_dm_op(domid_t domid, 500*3a9fd824SRoger Pau Monné * ` unsigned int nr_bufs, 501*3a9fd824SRoger Pau Monné * ` xen_dm_op_buf_t bufs[]) 502*3a9fd824SRoger Pau Monné * ` 503*3a9fd824SRoger Pau Monné * 504*3a9fd824SRoger Pau Monné * @domid is the domain the hypercall operates on. 505*3a9fd824SRoger Pau Monné * @nr_bufs is the number of buffers in the @bufs array. 506*3a9fd824SRoger Pau Monné * @bufs points to an array of buffers where @bufs[0] contains a struct 507*3a9fd824SRoger Pau Monné * xen_dm_op, describing the specific device model operation and its 508*3a9fd824SRoger Pau Monné * parameters. 509*3a9fd824SRoger Pau Monné * @bufs[1..] may be referenced in the parameters for the purposes of 510*3a9fd824SRoger Pau Monné * passing extra information to or from the domain. 511*3a9fd824SRoger Pau Monné */ 512*3a9fd824SRoger Pau Monné 513*3a9fd824SRoger Pau Monné #endif /* __XEN_PUBLIC_HVM_DM_OP_H__ */ 514*3a9fd824SRoger Pau Monné 515*3a9fd824SRoger Pau Monné /* 516*3a9fd824SRoger Pau Monné * Local variables: 517*3a9fd824SRoger Pau Monné * mode: C 518*3a9fd824SRoger Pau Monné * c-file-style: "BSD" 519*3a9fd824SRoger Pau Monné * c-basic-offset: 4 520*3a9fd824SRoger Pau Monné * tab-width: 4 521*3a9fd824SRoger Pau Monné * indent-tabs-mode: nil 522*3a9fd824SRoger Pau Monné * End: 523*3a9fd824SRoger Pau Monné */ 524