1 #ifndef __XEN_DEVICE_TREE_DEFS_H__ 2 #define __XEN_DEVICE_TREE_DEFS_H__ 3 4 #if defined(__XEN__) || defined(__XEN_TOOLS__) 5 /* 6 * The device tree compiler (DTC) is allocating the phandle from 1 to 7 * onwards. Reserve a high value for the GIC phandle. 8 */ 9 #define GUEST_PHANDLE_GIC (65000) 10 11 #define GUEST_ROOT_ADDRESS_CELLS 2 12 #define GUEST_ROOT_SIZE_CELLS 2 13 14 /** 15 * IRQ line type. 16 * 17 * DT_IRQ_TYPE_NONE - default, unspecified type 18 * DT_IRQ_TYPE_EDGE_RISING - rising edge triggered 19 * DT_IRQ_TYPE_EDGE_FALLING - falling edge triggered 20 * DT_IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 21 * DT_IRQ_TYPE_LEVEL_HIGH - high level triggered 22 * DT_IRQ_TYPE_LEVEL_LOW - low level triggered 23 * DT_IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 24 * DT_IRQ_TYPE_SENSE_MASK - Mask for all the above bits 25 * DT_IRQ_TYPE_INVALID - Use to initialize the type 26 */ 27 #define DT_IRQ_TYPE_NONE 0x00000000 28 #define DT_IRQ_TYPE_EDGE_RISING 0x00000001 29 #define DT_IRQ_TYPE_EDGE_FALLING 0x00000002 30 #define DT_IRQ_TYPE_EDGE_BOTH \ 31 (DT_IRQ_TYPE_EDGE_FALLING | DT_IRQ_TYPE_EDGE_RISING) 32 #define DT_IRQ_TYPE_LEVEL_HIGH 0x00000004 33 #define DT_IRQ_TYPE_LEVEL_LOW 0x00000008 34 #define DT_IRQ_TYPE_LEVEL_MASK \ 35 (DT_IRQ_TYPE_LEVEL_LOW | DT_IRQ_TYPE_LEVEL_HIGH) 36 #define DT_IRQ_TYPE_SENSE_MASK 0x0000000f 37 38 #define DT_IRQ_TYPE_INVALID 0x00000010 39 40 #endif 41 42 #endif 43