1 /* 2 * Implement fast Fletcher4 using superscalar pipelines. 3 * 4 * Use regular C code to compute 5 * Fletcher4 in two incremental 64-bit parallel accumulator streams, 6 * and then combine the streams to form the final four checksum words. 7 * This implementation is a derivative of the AVX SIMD implementation by 8 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c). 9 * 10 * Copyright (C) 2016 Romain Dolbeau. 11 * 12 * Authors: 13 * Romain Dolbeau <romain.dolbeau@atos.net> 14 * 15 * This software is available to you under a choice of one of two 16 * licenses. You may choose to be licensed under the terms of the GNU 17 * General Public License (GPL) Version 2, available from the file 18 * COPYING in the main directory of this source tree, or the 19 * OpenIB.org BSD license below: 20 * 21 * Redistribution and use in source and binary forms, with or 22 * without modification, are permitted provided that the following 23 * conditions are met: 24 * 25 * - Redistributions of source code must retain the above 26 * copyright notice, this list of conditions and the following 27 * disclaimer. 28 * 29 * - Redistributions in binary form must reproduce the above 30 * copyright notice, this list of conditions and the following 31 * disclaimer in the documentation and/or other materials 32 * provided with the distribution. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 41 * SOFTWARE. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/byteorder.h> 46 #include <sys/spa_checksum.h> 47 #include <sys/string.h> 48 #include <zfs_fletcher.h> 49 50 static void 51 fletcher_4_superscalar_init(fletcher_4_ctx_t *ctx) 52 { 53 memset(ctx->superscalar, 0, 4 * sizeof (zfs_fletcher_superscalar_t)); 54 } 55 56 static void 57 fletcher_4_superscalar_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp) 58 { 59 uint64_t A, B, C, D; 60 A = ctx->superscalar[0].v[0] + ctx->superscalar[0].v[1]; 61 B = 2 * ctx->superscalar[1].v[0] + 2 * ctx->superscalar[1].v[1] - 62 ctx->superscalar[0].v[1]; 63 C = 4 * ctx->superscalar[2].v[0] - ctx->superscalar[1].v[0] + 64 4 * ctx->superscalar[2].v[1] - 3 * ctx->superscalar[1].v[1]; 65 D = 8 * ctx->superscalar[3].v[0] - 4 * ctx->superscalar[2].v[0] + 66 8 * ctx->superscalar[3].v[1] - 8 * ctx->superscalar[2].v[1] + 67 ctx->superscalar[1].v[1]; 68 ZIO_SET_CHECKSUM(zcp, A, B, C, D); 69 } 70 71 static void 72 fletcher_4_superscalar_native(fletcher_4_ctx_t *ctx, 73 const void *buf, uint64_t size) 74 { 75 const uint32_t *ip = buf; 76 const uint32_t *ipend = ip + (size / sizeof (uint32_t)); 77 uint64_t a, b, c, d; 78 uint64_t a2, b2, c2, d2; 79 80 a = ctx->superscalar[0].v[0]; 81 b = ctx->superscalar[1].v[0]; 82 c = ctx->superscalar[2].v[0]; 83 d = ctx->superscalar[3].v[0]; 84 a2 = ctx->superscalar[0].v[1]; 85 b2 = ctx->superscalar[1].v[1]; 86 c2 = ctx->superscalar[2].v[1]; 87 d2 = ctx->superscalar[3].v[1]; 88 89 do { 90 a += ip[0]; 91 a2 += ip[1]; 92 b += a; 93 b2 += a2; 94 c += b; 95 c2 += b2; 96 d += c; 97 d2 += c2; 98 } while ((ip += 2) < ipend); 99 100 ctx->superscalar[0].v[0] = a; 101 ctx->superscalar[1].v[0] = b; 102 ctx->superscalar[2].v[0] = c; 103 ctx->superscalar[3].v[0] = d; 104 ctx->superscalar[0].v[1] = a2; 105 ctx->superscalar[1].v[1] = b2; 106 ctx->superscalar[2].v[1] = c2; 107 ctx->superscalar[3].v[1] = d2; 108 } 109 110 static void 111 fletcher_4_superscalar_byteswap(fletcher_4_ctx_t *ctx, 112 const void *buf, uint64_t size) 113 { 114 const uint32_t *ip = buf; 115 const uint32_t *ipend = ip + (size / sizeof (uint32_t)); 116 uint64_t a, b, c, d; 117 uint64_t a2, b2, c2, d2; 118 119 a = ctx->superscalar[0].v[0]; 120 b = ctx->superscalar[1].v[0]; 121 c = ctx->superscalar[2].v[0]; 122 d = ctx->superscalar[3].v[0]; 123 a2 = ctx->superscalar[0].v[1]; 124 b2 = ctx->superscalar[1].v[1]; 125 c2 = ctx->superscalar[2].v[1]; 126 d2 = ctx->superscalar[3].v[1]; 127 128 do { 129 a += BSWAP_32(ip[0]); 130 a2 += BSWAP_32(ip[1]); 131 b += a; 132 b2 += a2; 133 c += b; 134 c2 += b2; 135 d += c; 136 d2 += c2; 137 } while ((ip += 2) < ipend); 138 139 ctx->superscalar[0].v[0] = a; 140 ctx->superscalar[1].v[0] = b; 141 ctx->superscalar[2].v[0] = c; 142 ctx->superscalar[3].v[0] = d; 143 ctx->superscalar[0].v[1] = a2; 144 ctx->superscalar[1].v[1] = b2; 145 ctx->superscalar[2].v[1] = c2; 146 ctx->superscalar[3].v[1] = d2; 147 } 148 149 static boolean_t fletcher_4_superscalar_valid(void) 150 { 151 return (B_TRUE); 152 } 153 154 const fletcher_4_ops_t fletcher_4_superscalar_ops = { 155 .init_native = fletcher_4_superscalar_init, 156 .compute_native = fletcher_4_superscalar_native, 157 .fini_native = fletcher_4_superscalar_fini, 158 .init_byteswap = fletcher_4_superscalar_init, 159 .compute_byteswap = fletcher_4_superscalar_byteswap, 160 .fini_byteswap = fletcher_4_superscalar_fini, 161 .valid = fletcher_4_superscalar_valid, 162 .uses_fpu = B_FALSE, 163 .name = "superscalar" 164 }; 165