xref: /freebsd/sys/contrib/openzfs/module/zcommon/zfs_fletcher_aarch64_neon.c (revision 643ac419fafba89f5adda0e0ea75b538727453fb)
1 /*
2  * Implement fast Fletcher4 with NEON instructions. (aarch64)
3  *
4  * Use the 128-bit NEON SIMD instructions and registers to compute
5  * Fletcher4 in two incremental 64-bit parallel accumulator streams,
6  * and then combine the streams to form the final four checksum words.
7  * This implementation is a derivative of the AVX SIMD implementation by
8  * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
9  *
10  * Copyright (C) 2016 Romain Dolbeau.
11  *
12  * Authors:
13  *	Romain Dolbeau <romain.dolbeau@atos.net>
14  *
15  * This software is available to you under a choice of one of two
16  * licenses.  You may choose to be licensed under the terms of the GNU
17  * General Public License (GPL) Version 2, available from the file
18  * COPYING in the main directory of this source tree, or the
19  * OpenIB.org BSD license below:
20  *
21  *     Redistribution and use in source and binary forms, with or
22  *     without modification, are permitted provided that the following
23  *     conditions are met:
24  *
25  *	- Redistributions of source code must retain the above
26  *	  copyright notice, this list of conditions and the following
27  *	  disclaimer.
28  *
29  *	- Redistributions in binary form must reproduce the above
30  *	  copyright notice, this list of conditions and the following
31  *	  disclaimer in the documentation and/or other materials
32  *	  provided with the distribution.
33  *
34  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
38  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
39  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
40  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
41  * SOFTWARE.
42  */
43 
44 #if defined(__aarch64__)
45 
46 #include <sys/simd.h>
47 #include <sys/spa_checksum.h>
48 #include <sys/string.h>
49 #include <zfs_fletcher.h>
50 
51 ZFS_NO_SANITIZE_UNDEFINED
52 static void
53 fletcher_4_aarch64_neon_init(fletcher_4_ctx_t *ctx)
54 {
55 	memset(ctx->aarch64_neon, 0, 4 * sizeof (zfs_fletcher_aarch64_neon_t));
56 }
57 
58 ZFS_NO_SANITIZE_UNDEFINED
59 static void
60 fletcher_4_aarch64_neon_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
61 {
62 	uint64_t A, B, C, D;
63 	A = ctx->aarch64_neon[0].v[0] + ctx->aarch64_neon[0].v[1];
64 	B = 2 * ctx->aarch64_neon[1].v[0] + 2 * ctx->aarch64_neon[1].v[1] -
65 	    ctx->aarch64_neon[0].v[1];
66 	C = 4 * ctx->aarch64_neon[2].v[0] - ctx->aarch64_neon[1].v[0] +
67 	    4 * ctx->aarch64_neon[2].v[1] - 3 * ctx->aarch64_neon[1].v[1];
68 	D = 8 * ctx->aarch64_neon[3].v[0] - 4 * ctx->aarch64_neon[2].v[0] +
69 	    8 * ctx->aarch64_neon[3].v[1] - 8 * ctx->aarch64_neon[2].v[1] +
70 	    ctx->aarch64_neon[1].v[1];
71 	ZIO_SET_CHECKSUM(zcp, A, B, C, D);
72 }
73 
74 #define	NEON_INIT_LOOP()			\
75 	asm("eor %[ZERO].16b,%[ZERO].16b,%[ZERO].16b\n"	\
76 	"ld1 { %[ACC0].4s }, %[CTX0]\n"		\
77 	"ld1 { %[ACC1].4s }, %[CTX1]\n"		\
78 	"ld1 { %[ACC2].4s }, %[CTX2]\n"		\
79 	"ld1 { %[ACC3].4s }, %[CTX3]\n"		\
80 	: [ZERO] "=w" (ZERO),			\
81 	[ACC0] "=w" (ACC0), [ACC1] "=w" (ACC1),	\
82 	[ACC2] "=w" (ACC2), [ACC3] "=w" (ACC3)	\
83 	: [CTX0] "Q" (ctx->aarch64_neon[0]),	\
84 	[CTX1] "Q" (ctx->aarch64_neon[1]),	\
85 	[CTX2] "Q" (ctx->aarch64_neon[2]),	\
86 	[CTX3] "Q" (ctx->aarch64_neon[3]))
87 
88 #define	NEON_DO_REVERSE "rev32 %[SRC].16b, %[SRC].16b\n"
89 
90 #define	NEON_DONT_REVERSE ""
91 
92 #define	NEON_MAIN_LOOP(REVERSE)				\
93 	asm("ld1 { %[SRC].4s }, %[IP]\n"		\
94 	REVERSE						\
95 	"zip1 %[TMP1].4s, %[SRC].4s, %[ZERO].4s\n"	\
96 	"zip2 %[TMP2].4s, %[SRC].4s, %[ZERO].4s\n"	\
97 	"add %[ACC0].2d, %[ACC0].2d, %[TMP1].2d\n"	\
98 	"add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n"	\
99 	"add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n"	\
100 	"add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n"	\
101 	"add %[ACC0].2d, %[ACC0].2d, %[TMP2].2d\n"	\
102 	"add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n"	\
103 	"add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n"	\
104 	"add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n"	\
105 	: [SRC] "=&w" (SRC),				\
106 	[TMP1] "=&w" (TMP1), [TMP2] "=&w" (TMP2),	\
107 	[ACC0] "+w" (ACC0), [ACC1] "+w" (ACC1),		\
108 	[ACC2] "+w" (ACC2), [ACC3] "+w" (ACC3)		\
109 	: [ZERO] "w" (ZERO), [IP] "Q" (*ip))
110 
111 #define	NEON_FINI_LOOP()			\
112 	asm("st1 { %[ACC0].4s },%[DST0]\n"	\
113 	"st1 { %[ACC1].4s },%[DST1]\n"		\
114 	"st1 { %[ACC2].4s },%[DST2]\n"		\
115 	"st1 { %[ACC3].4s },%[DST3]\n"		\
116 	: [DST0] "=Q" (ctx->aarch64_neon[0]),	\
117 	[DST1] "=Q" (ctx->aarch64_neon[1]),	\
118 	[DST2] "=Q" (ctx->aarch64_neon[2]),	\
119 	[DST3] "=Q" (ctx->aarch64_neon[3])	\
120 	: [ACC0] "w" (ACC0), [ACC1] "w" (ACC1),	\
121 	[ACC2] "w" (ACC2), [ACC3] "w" (ACC3))
122 
123 static void
124 fletcher_4_aarch64_neon_native(fletcher_4_ctx_t *ctx,
125     const void *buf, uint64_t size)
126 {
127 	const uint64_t *ip = buf;
128 	const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
129 #if defined(_KERNEL)
130 register unsigned char ZERO asm("v0") __attribute__((vector_size(16)));
131 register unsigned char ACC0 asm("v1") __attribute__((vector_size(16)));
132 register unsigned char ACC1 asm("v2") __attribute__((vector_size(16)));
133 register unsigned char ACC2 asm("v3") __attribute__((vector_size(16)));
134 register unsigned char ACC3 asm("v4") __attribute__((vector_size(16)));
135 register unsigned char TMP1 asm("v5") __attribute__((vector_size(16)));
136 register unsigned char TMP2 asm("v6") __attribute__((vector_size(16)));
137 register unsigned char SRC asm("v7") __attribute__((vector_size(16)));
138 #else
139 unsigned char ZERO __attribute__((vector_size(16)));
140 unsigned char ACC0 __attribute__((vector_size(16)));
141 unsigned char ACC1 __attribute__((vector_size(16)));
142 unsigned char ACC2 __attribute__((vector_size(16)));
143 unsigned char ACC3 __attribute__((vector_size(16)));
144 unsigned char TMP1 __attribute__((vector_size(16)));
145 unsigned char TMP2 __attribute__((vector_size(16)));
146 unsigned char SRC __attribute__((vector_size(16)));
147 #endif
148 
149 	kfpu_begin();
150 
151 	NEON_INIT_LOOP();
152 
153 	for (; ip < ipend; ip += 2) {
154 		NEON_MAIN_LOOP(NEON_DONT_REVERSE);
155 	}
156 
157 	NEON_FINI_LOOP();
158 
159 	kfpu_end();
160 }
161 
162 static void
163 fletcher_4_aarch64_neon_byteswap(fletcher_4_ctx_t *ctx,
164     const void *buf, uint64_t size)
165 {
166 	const uint64_t *ip = buf;
167 	const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
168 #if defined(_KERNEL)
169 register unsigned char ZERO asm("v0") __attribute__((vector_size(16)));
170 register unsigned char ACC0 asm("v1") __attribute__((vector_size(16)));
171 register unsigned char ACC1 asm("v2") __attribute__((vector_size(16)));
172 register unsigned char ACC2 asm("v3") __attribute__((vector_size(16)));
173 register unsigned char ACC3 asm("v4") __attribute__((vector_size(16)));
174 register unsigned char TMP1 asm("v5") __attribute__((vector_size(16)));
175 register unsigned char TMP2 asm("v6") __attribute__((vector_size(16)));
176 register unsigned char SRC asm("v7") __attribute__((vector_size(16)));
177 #else
178 unsigned char ZERO __attribute__((vector_size(16)));
179 unsigned char ACC0 __attribute__((vector_size(16)));
180 unsigned char ACC1 __attribute__((vector_size(16)));
181 unsigned char ACC2 __attribute__((vector_size(16)));
182 unsigned char ACC3 __attribute__((vector_size(16)));
183 unsigned char TMP1 __attribute__((vector_size(16)));
184 unsigned char TMP2 __attribute__((vector_size(16)));
185 unsigned char SRC __attribute__((vector_size(16)));
186 #endif
187 
188 	kfpu_begin();
189 
190 	NEON_INIT_LOOP();
191 
192 	for (; ip < ipend; ip += 2) {
193 		NEON_MAIN_LOOP(NEON_DO_REVERSE);
194 	}
195 
196 	NEON_FINI_LOOP();
197 
198 	kfpu_end();
199 }
200 
201 static boolean_t fletcher_4_aarch64_neon_valid(void)
202 {
203 	return (kfpu_allowed());
204 }
205 
206 const fletcher_4_ops_t fletcher_4_aarch64_neon_ops = {
207 	.init_native = fletcher_4_aarch64_neon_init,
208 	.compute_native = fletcher_4_aarch64_neon_native,
209 	.fini_native = fletcher_4_aarch64_neon_fini,
210 	.init_byteswap = fletcher_4_aarch64_neon_init,
211 	.compute_byteswap = fletcher_4_aarch64_neon_byteswap,
212 	.fini_byteswap = fletcher_4_aarch64_neon_fini,
213 	.valid = fletcher_4_aarch64_neon_valid,
214 	.name = "aarch64_neon"
215 };
216 
217 #endif /* defined(__aarch64__) */
218