1 /****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 **************************************************************************/ 35 /** 36 37 @File dpaa_integration_ext.h 38 39 @Description P5020 FM external definitions and structures. 40 *//***************************************************************************/ 41 #ifndef __DPAA_INTEGRATION_EXT_H 42 #define __DPAA_INTEGRATION_EXT_H 43 44 #include "std_ext.h" 45 46 47 /**************************************************************************//** 48 @Description DPAA SW Portals Enumeration. 49 *//***************************************************************************/ 50 typedef enum 51 { 52 e_DPAA_SWPORTAL0 = 0, 53 e_DPAA_SWPORTAL1, 54 e_DPAA_SWPORTAL2, 55 e_DPAA_SWPORTAL3, 56 e_DPAA_SWPORTAL4, 57 e_DPAA_SWPORTAL5, 58 e_DPAA_SWPORTAL6, 59 e_DPAA_SWPORTAL7, 60 e_DPAA_SWPORTAL8, 61 e_DPAA_SWPORTAL9, 62 e_DPAA_SWPORTAL_DUMMY_LAST 63 } e_DpaaSwPortal; 64 65 /**************************************************************************//** 66 @Description DPAA Direct Connect Portals Enumeration. 67 *//***************************************************************************/ 68 typedef enum 69 { 70 e_DPAA_DCPORTAL0 = 0, 71 e_DPAA_DCPORTAL1, 72 e_DPAA_DCPORTAL2, 73 e_DPAA_DCPORTAL3, 74 e_DPAA_DCPORTAL4, 75 e_DPAA_DCPORTAL_DUMMY_LAST 76 } e_DpaaDcPortal; 77 78 #define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST 79 #define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST 80 81 /***************************************************************************** 82 QMan INTEGRATION-SPECIFIC DEFINITIONS 83 ******************************************************************************/ 84 #define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */ 85 #define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */ 86 #define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */ 87 #define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE) 88 /**< FQIDs range - 24 bits */ 89 90 /**************************************************************************//** 91 @Description Work Queue Channel assignments in QMan. 92 *//***************************************************************************/ 93 typedef enum 94 { 95 e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */ 96 e_QM_FQ_CHANNEL_SWPORTAL1, 97 e_QM_FQ_CHANNEL_SWPORTAL2, 98 e_QM_FQ_CHANNEL_SWPORTAL3, 99 e_QM_FQ_CHANNEL_SWPORTAL4, 100 e_QM_FQ_CHANNEL_SWPORTAL5, 101 e_QM_FQ_CHANNEL_SWPORTAL6, 102 e_QM_FQ_CHANNEL_SWPORTAL7, 103 e_QM_FQ_CHANNEL_SWPORTAL8, 104 e_QM_FQ_CHANNEL_SWPORTAL9, 105 106 e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */ 107 e_QM_FQ_CHANNEL_POOL2, 108 e_QM_FQ_CHANNEL_POOL3, 109 e_QM_FQ_CHANNEL_POOL4, 110 e_QM_FQ_CHANNEL_POOL5, 111 e_QM_FQ_CHANNEL_POOL6, 112 e_QM_FQ_CHANNEL_POOL7, 113 e_QM_FQ_CHANNEL_POOL8, 114 e_QM_FQ_CHANNEL_POOL9, 115 e_QM_FQ_CHANNEL_POOL10, 116 e_QM_FQ_CHANNEL_POOL11, 117 e_QM_FQ_CHANNEL_POOL12, 118 e_QM_FQ_CHANNEL_POOL13, 119 e_QM_FQ_CHANNEL_POOL14, 120 e_QM_FQ_CHANNEL_POOL15, 121 122 e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0: 123 connected to FMan 0; assigned in incrementing order to 124 each sub-portal (SP) in the portal */ 125 e_QM_FQ_CHANNEL_FMAN0_SP1, 126 e_QM_FQ_CHANNEL_FMAN0_SP2, 127 e_QM_FQ_CHANNEL_FMAN0_SP3, 128 e_QM_FQ_CHANNEL_FMAN0_SP4, 129 e_QM_FQ_CHANNEL_FMAN0_SP5, 130 e_QM_FQ_CHANNEL_FMAN0_SP6, 131 e_QM_FQ_CHANNEL_FMAN0_SP7, 132 e_QM_FQ_CHANNEL_FMAN0_SP8, 133 e_QM_FQ_CHANNEL_FMAN0_SP9, 134 e_QM_FQ_CHANNEL_FMAN0_SP10, 135 e_QM_FQ_CHANNEL_FMAN0_SP11, 136 137 e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */ 138 e_QM_FQ_CHANNEL_RMAN_SP3, 139 140 e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2: 141 connected to SEC 4.x */ 142 143 e_QM_FQ_CHANNEL_PME = 0xA0, /**< Dedicated channel serviced by Direct Connect Portal 3: 144 connected to PME */ 145 e_QM_FQ_CHANNEL_RAID = 0xC0 /**< Dedicated channel serviced by Direct Connect Portal 4: 146 connected to RAID */ 147 } e_QmFQChannel; 148 149 /***************************************************************************** 150 BMan INTEGRATION-SPECIFIC DEFINITIONS 151 ******************************************************************************/ 152 #define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */ 153 154 /***************************************************************************** 155 FM INTEGRATION-SPECIFIC DEFINITIONS 156 ******************************************************************************/ 157 #define INTG_MAX_NUM_OF_FM 1 158 159 /* Ports defines */ 160 #define FM_MAX_NUM_OF_1G_MACS 5 161 #define FM_MAX_NUM_OF_10G_MACS 1 162 #define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS) 163 #define FM_MAX_NUM_OF_OH_PORTS 7 164 165 #define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS 166 #define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS 167 #define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS) 168 169 #define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS 170 #define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS 171 #define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS) 172 173 #define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */ 174 #define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */ 175 #define FM_MAX_NUM_OF_SUB_PORTALS 12 176 #define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0 177 178 /* RAMs defines */ 179 #define FM_MURAM_SIZE (160 * KILOBYTE) 180 #define FM_IRAM_SIZE(a,b) ( 64 * KILOBYTE) 181 182 /* PCD defines */ 183 #define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */ 184 #define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */ 185 #define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */ 186 187 /* RTC defines */ 188 #define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */ 189 #define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */ 190 #define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */ 191 192 /* QMI defines */ 193 #define QMI_MAX_NUM_OF_TNUMS 64 194 #define MAX_QMI_DEQ_SUBPORTAL 12 195 #define QMI_DEF_TNUMS_THRESH 48 196 197 /* FPM defines */ 198 #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4 199 200 /* DMA defines */ 201 #define DMA_THRESH_MAX_COMMQ 31 202 #define DMA_THRESH_MAX_BUF 127 203 204 /* BMI defines */ 205 #define BMI_MAX_NUM_OF_TASKS 128 206 #define BMI_MAX_NUM_OF_DMAS 32 207 #define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE) 208 #define PORT_MAX_WEIGHT 16 209 210 211 #define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE 212 213 /* P5020 unique features */ 214 #define FM_QMI_DEQ_OPTIONS_SUPPORT 215 #define FM_NO_DISPATCH_RAM_ECC 216 #define FM_FIFO_ALLOCATION_OLD_ALG 217 #define FM_NO_WATCHDOG 218 #define FM_NO_TNUM_AGING 219 #define FM_NO_TGEC_LOOPBACK 220 #define FM_KG_NO_BYPASS_FQID_GEN 221 #define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN 222 #define FM_NO_BACKUP_POOLS 223 #define FM_NO_OP_OBSERVED_POOLS 224 #define FM_NO_ADVANCED_RATE_LIMITER 225 #define FM_NO_OP_OBSERVED_CGS 226 227 /* FM erratas (P5020, P3041) */ 228 #define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 229 #define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */ 230 #define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 231 #define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008 232 233 #define FM_NO_RX_PREAM_ERRATA_DTSECx1 234 #define FM_GRS_ERRATA_DTSEC_A002 235 #define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 236 #define FM_GTS_ERRATA_DTSEC_A004 237 #define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */ 238 #define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */ 239 #define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004 240 #define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3 241 #define FM_TX_LOCKUP_ERRATA_DTSEC6 242 243 #define FM_IM_TX_SYNC_SKIP_TNUM_ERRATA_FMAN_A001 /* Implemented by ucode */ 244 #define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */ 245 #define FM_IM_TX_SHARED_TNUM_ERRATA_FMAN4 /* Implemented by ucode */ 246 #define FM_IM_GS_DEADLOCK_ERRATA_FMAN5 /* Implemented by ucode */ 247 #define FM_IM_DEQ_PIPELINE_DEPTH_ERRATA_FMAN10 /* Implemented by ucode */ 248 #define FM_CC_GEN6_MISSMATCH_ERRATA_FMAN12 /* Implemented by ucode */ 249 #define FM_CC_CHANGE_SHARED_TNUM_ERRATA_FMAN13 /* Implemented by ucode */ 250 #define FM_IM_LARGE_MRBLR_ERRATA_FMAN15 /* Implemented by ucode */ 251 #define FM_BMI_TO_RISC_ENQ_ERRATA_FMANc /* No implementation, Out of LLD scope */ 252 #define FM_INVALID_SWPRS_DATA_ERRATA_FMANd 253 //#define FM_PRS_MPLS_SSA_ERRATA_FMANj /* No implementation, No patch yet */ 254 //#define FM_PRS_INITIAL_PLANID_ERRATA_FMANk /* No implementation, No patch yet */ 255 256 #define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001 257 258 #define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001 259 260 /* P2041 */ 261 #define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010 262 263 /* Common to all */ 264 #define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1 265 #define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173 266 #define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */ 267 #define FM_PRS_MEM_ERRATA_FMAN_SW003 268 #define FM_LEN_CHECK_ERRATA_FMAN_SW002 269 270 #define DPAA_VERSION 10 271 #define FM_PCD_SW_PRS_SIZE 0x00000800 272 #define FM_PCD_PRS_SW_PATCHES_SIZE 0x00000200 273 #define FM_NUM_OF_CTRL 2 274 275 #endif /* __DPAA_INTEGRATION_EXT_H */ 276