1 /****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 35 **************************************************************************/ 36 /****************************************************************************** 37 @File qman_private.h 38 39 @Description QM private header 40 *//***************************************************************************/ 41 #ifndef __QMAN_PRIVATE_H 42 #define __QMAN_PRIVATE_H 43 44 #include "fsl_qman.h" 45 46 47 #define __ERR_MODULE__ MODULE_QM 48 49 #if defined(DEBUG) || !defined(DISABLE_ASSERTIONS) 50 /* Optionally compile-in assertion-checking */ 51 #define QM_CHECKING 52 #endif /* defined(DEBUG) || ... */ 53 54 /* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers 55 * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or 56 * execution reordering with respect to other code/instructions that manipulate 57 * the same cacheline. */ 58 #ifdef CORE_E500MC 59 60 #if defined(_DIAB_TOOL) 61 #define hwsync() \ 62 do { \ 63 __asm__ __volatile__ ("sync"); \ 64 } while(0) 65 66 #define lwsync() \ 67 do { \ 68 __asm__ __volatile__ ("lwsync"); \ 69 } while(0) 70 71 __asm__ __volatile__ void dcbf (volatile void * addr) 72 { 73 %reg addr 74 dcbf r0, addr 75 } 76 77 __asm__ __volatile__ void dcbt_ro (volatile void * addr) 78 { 79 %reg addr 80 dcbt r0, addr 81 } 82 83 __asm__ __volatile__ void dcbt_rw (volatile void * addr) 84 { 85 %reg addr 86 dcbtst r0, addr 87 } 88 89 __asm__ __volatile__ void dcbzl (volatile void * addr) 90 { 91 %reg addr 92 dcbzl r0, addr 93 } 94 95 #define dcbz_64(p) \ 96 do { \ 97 dcbzl(p); \ 98 } while (0) 99 100 #define dcbf_64(p) \ 101 do { \ 102 dcbf(p); \ 103 } while (0) 104 105 /* Commonly used combo */ 106 #define dcbit_ro(p) \ 107 do { \ 108 dcbi(p); \ 109 dcbt_ro(p); \ 110 } while (0) 111 112 #else /* GNU C */ 113 #define hwsync() \ 114 do { \ 115 __asm__ __volatile__ ("sync" : : : "memory"); \ 116 } while(0) 117 118 #define lwsync() \ 119 do { \ 120 __asm__ __volatile__ ("lwsync" : : : "memory"); \ 121 } while(0) 122 123 #define dcbf(addr) \ 124 do { \ 125 __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \ 126 } while(0) 127 128 #define dcbt_ro(addr) \ 129 do { \ 130 __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \ 131 } while(0) 132 133 #define dcbt_rw(addr) \ 134 do { \ 135 __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \ 136 } while(0) 137 138 #define dcbzl(p) \ 139 do { \ 140 __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \ 141 } while(0) 142 143 #define dcbz_64(p) \ 144 do { \ 145 dcbzl(p); \ 146 } while (0) 147 148 #define dcbf_64(p) \ 149 do { \ 150 dcbf(p); \ 151 } while (0) 152 153 /* Commonly used combo */ 154 #define dcbit_ro(p) \ 155 do { \ 156 dcbi(p); \ 157 dcbt_ro(p); \ 158 } while (0) 159 160 #endif /* _DIAB_TOOL */ 161 162 #else 163 #define hwsync CORE_MemoryBarrier 164 #define lwsync hwsync 165 166 #define dcbf(p) \ 167 do { \ 168 __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \ 169 } while(0) 170 #define dcbt_ro(p) \ 171 do { \ 172 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \ 173 lwsync(); \ 174 } while(0) 175 #define dcbt_rw(p) \ 176 do { \ 177 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \ 178 } while(0) 179 #define dcbz(p) \ 180 do { \ 181 __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \ 182 } while (0) 183 #define dcbz_64(p) \ 184 do { \ 185 dcbz((uint32_t)p + 32); \ 186 dcbz(p); \ 187 } while (0) 188 #define dcbf_64(p) \ 189 do { \ 190 dcbf((uint32_t)p + 32); \ 191 dcbf(p); \ 192 } while (0) 193 /* Commonly used combo */ 194 #define dcbit_ro(p) \ 195 do { \ 196 dcbi(p); \ 197 dcbi((uint32_t)p + 32); \ 198 dcbt_ro(p); \ 199 dcbt_ro((uint32_t)p + 32); \ 200 } while (0) 201 202 #endif /* CORE_E500MC */ 203 204 #define dcbi(p) dcbf(p) 205 206 struct qm_addr { 207 void *addr_ce; /* cache-enabled */ 208 void *addr_ci; /* cache-inhibited */ 209 }; 210 211 /* EQCR state */ 212 struct qm_eqcr { 213 struct qm_eqcr_entry *ring, *cursor; 214 uint8_t ci, available, ithresh, vbit; 215 216 #ifdef QM_CHECKING 217 uint32_t busy; 218 e_QmPortalProduceMode pmode; 219 e_QmPortalEqcrConsumeMode cmode; 220 #endif /* QM_CHECKING */ 221 }; 222 223 /* DQRR state */ 224 struct qm_dqrr { 225 struct qm_dqrr_entry *ring, *cursor; 226 uint8_t pi, ci, fill, ithresh, vbit, flags; 227 228 #ifdef QM_CHECKING 229 e_QmPortalDequeueMode dmode; 230 e_QmPortalProduceMode pmode; 231 e_QmPortalDqrrConsumeMode cmode; 232 #endif /* QM_CHECKING */ 233 }; 234 #define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */ 235 #define QM_DQRR_FLAG_SE 0x02 /* Stash data */ 236 237 /* MR state */ 238 struct qm_mr { 239 struct qm_mr_entry *ring, *cursor; 240 uint8_t pi, ci, fill, ithresh, vbit; 241 242 #ifdef QM_CHECKING 243 e_QmPortalProduceMode pmode; 244 e_QmPortalMrConsumeMode cmode; 245 #endif /* QM_CHECKING */ 246 }; 247 248 /* MC state */ 249 struct qm_mc { 250 struct qm_mc_command *cr; 251 struct qm_mc_result *rr; 252 uint8_t rridx, vbit; 253 #ifdef QM_CHECKING 254 enum { 255 /* Can be _mc_start()ed */ 256 mc_idle, 257 /* Can be _mc_commit()ed or _mc_abort()ed */ 258 mc_user, 259 /* Can only be _mc_retry()ed */ 260 mc_hw 261 } state; 262 #endif /* QM_CHECKING */ 263 }; 264 265 /********************/ 266 /* Portal structure */ 267 /********************/ 268 269 struct qm_portal { 270 /* In the non-QM_CHECKING case, everything up to and 271 * including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a 272 * cause for a concern. In other words, don't rearrange this structure 273 * on a whim, there be dragons ... */ 274 struct qm_addr addr; 275 struct qm_eqcr eqcr; 276 struct qm_dqrr dqrr; 277 struct qm_mr mr; 278 struct qm_mc mc; 279 struct qm_portal_config config; 280 t_Handle bind_lock; 281 /* Logical index (not cell-index) */ 282 int index; 283 }; 284 285 #endif /* __QMAN_PRIVATE_H */ 286