1 /****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 35 **************************************************************************/ 36 /****************************************************************************** 37 @File qman_private.h 38 39 @Description QM private header 40 *//***************************************************************************/ 41 #ifndef __QMAN_PRIVATE_H 42 #define __QMAN_PRIVATE_H 43 44 #include "fsl_qman.h" 45 46 47 #define __ERR_MODULE__ MODULE_QM 48 49 #if defined(DEBUG) || !defined(DISABLE_ASSERTIONS) 50 /* Optionally compile-in assertion-checking */ 51 #define QM_CHECKING 52 #endif /* defined(DEBUG) || ... */ 53 54 /* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers 55 * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or 56 * execution reordering with respect to other code/instructions that manipulate 57 * the same cacheline. */ 58 59 #define dcbf(addr) \ 60 do { \ 61 __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \ 62 } while(0) 63 64 #ifdef CORE_E500MC 65 #define dcbt_ro(addr) \ 66 do { \ 67 __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \ 68 } while(0) 69 70 #define dcbt_rw(addr) \ 71 do { \ 72 __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \ 73 } while(0) 74 75 #define dcbzl(p) \ 76 do { \ 77 __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \ 78 } while(0) 79 80 #define dcbz_64(p) \ 81 do { \ 82 dcbzl(p); \ 83 } while (0) 84 85 #define dcbf_64(p) \ 86 do { \ 87 dcbf(p); \ 88 } while (0) 89 90 /* Commonly used combo */ 91 #define dcbit_ro(p) \ 92 do { \ 93 dcbi(p); \ 94 dcbt_ro(p); \ 95 } while (0) 96 97 #else 98 99 #define dcbt_ro(p) \ 100 do { \ 101 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \ 102 lwsync(); \ 103 } while(0) 104 #define dcbt_rw(p) \ 105 do { \ 106 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \ 107 } while(0) 108 #define dcbz(p) \ 109 do { \ 110 __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \ 111 } while (0) 112 #define dcbz_64(p) \ 113 do { \ 114 dcbz((char *)p + 32); \ 115 dcbz(p); \ 116 } while (0) 117 #define dcbf_64(p) \ 118 do { \ 119 dcbf((char *)p + 32); \ 120 dcbf(p); \ 121 } while (0) 122 /* Commonly used combo */ 123 #define dcbit_ro(p) \ 124 do { \ 125 dcbi(p); \ 126 dcbi((char *)p + 32); \ 127 dcbt_ro(p); \ 128 dcbt_ro((char *)p + 32); \ 129 } while (0) 130 131 #endif /* CORE_E500MC */ 132 133 #define dcbi(p) dcbf(p) 134 135 struct qm_addr { 136 void *addr_ce; /* cache-enabled */ 137 void *addr_ci; /* cache-inhibited */ 138 }; 139 140 /* EQCR state */ 141 struct qm_eqcr { 142 struct qm_eqcr_entry *ring, *cursor; 143 uint8_t ci, available, ithresh, vbit; 144 145 #ifdef QM_CHECKING 146 uint32_t busy; 147 e_QmPortalProduceMode pmode; 148 e_QmPortalEqcrConsumeMode cmode; 149 #endif /* QM_CHECKING */ 150 }; 151 152 /* DQRR state */ 153 struct qm_dqrr { 154 struct qm_dqrr_entry *ring, *cursor; 155 uint8_t pi, ci, fill, ithresh, vbit, flags; 156 157 #ifdef QM_CHECKING 158 e_QmPortalDequeueMode dmode; 159 e_QmPortalProduceMode pmode; 160 e_QmPortalDqrrConsumeMode cmode; 161 #endif /* QM_CHECKING */ 162 }; 163 #define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */ 164 #define QM_DQRR_FLAG_SE 0x02 /* Stash data */ 165 166 /* MR state */ 167 struct qm_mr { 168 struct qm_mr_entry *ring, *cursor; 169 uint8_t pi, ci, fill, ithresh, vbit; 170 171 #ifdef QM_CHECKING 172 e_QmPortalProduceMode pmode; 173 e_QmPortalMrConsumeMode cmode; 174 #endif /* QM_CHECKING */ 175 }; 176 177 /* MC state */ 178 struct qm_mc { 179 struct qm_mc_command *cr; 180 struct qm_mc_result *rr; 181 uint8_t rridx, vbit; 182 #ifdef QM_CHECKING 183 enum { 184 /* Can be _mc_start()ed */ 185 mc_idle, 186 /* Can be _mc_commit()ed or _mc_abort()ed */ 187 mc_user, 188 /* Can only be _mc_retry()ed */ 189 mc_hw 190 } state; 191 #endif /* QM_CHECKING */ 192 }; 193 194 /********************/ 195 /* Portal structure */ 196 /********************/ 197 198 struct qm_portal { 199 /* In the non-QM_CHECKING case, everything up to and 200 * including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a 201 * cause for a concern. In other words, don't rearrange this structure 202 * on a whim, there be dragons ... */ 203 struct qm_addr addr; 204 struct qm_eqcr eqcr; 205 struct qm_dqrr dqrr; 206 struct qm_mr mr; 207 struct qm_mc mc; 208 struct qm_portal_config config; 209 t_Handle bind_lock; 210 /* Logical index (not cell-index) */ 211 int index; 212 }; 213 214 #endif /* __QMAN_PRIVATE_H */ 215