1 /* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /****************************************************************************** 34 @File fm_pcd.h 35 36 @Description FM PCD ... 37 *//***************************************************************************/ 38 #ifndef __FM_PCD_H 39 #define __FM_PCD_H 40 41 #include "std_ext.h" 42 #include "error_ext.h" 43 #include "list_ext.h" 44 #include "fm_pcd_ext.h" 45 46 47 #define __ERR_MODULE__ MODULE_FM_PCD 48 49 50 /**************************************************************************//** 51 @Group FM_PCD_Runtime_grp FM PCD Runtime Unit 52 @{ 53 *//***************************************************************************/ 54 55 /****************************/ 56 /* Network defines */ 57 /****************************/ 58 #define UDP_HEADER_SIZE 8 59 60 #define ESP_SPI_OFFSET 0 61 #define ESP_SPI_SIZE 4 62 #define ESP_SEQ_NUM_OFFSET ESP_SPI_SIZE 63 #define ESP_SEQ_NUM_SIZE 4 64 65 /****************************/ 66 /* General defines */ 67 /****************************/ 68 #define ILLEGAL_CLS_PLAN 0xff 69 #define ILLEGAL_NETENV 0xff 70 /****************************/ 71 /* Error defines */ 72 /****************************/ 73 #define FM_PCD_EX_KG_DOUBLE_ECC 0x80000000 74 #define FM_PCD_EX_KG_KEYSIZE_OVERFLOW 0x40000000 75 76 #define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000 77 #define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000 78 #define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000 79 #define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000 80 81 #define FM_PCD_EX_PRS_DOUBLE_ECC 0x02000000 82 #define FM_PCD_EX_PRS_SINGLE_ECC 0x01000000 83 84 #define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \ 85 switch(exception){ \ 86 case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \ 87 bitMask = FM_PCD_EX_KG_DOUBLE_ECC; break; \ 88 case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \ 89 bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \ 90 case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \ 91 bitMask = FM_PCD_EX_KG_KEYSIZE_OVERFLOW; break; \ 92 case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \ 93 bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \ 94 case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \ 95 bitMask = FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE; break; \ 96 case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: \ 97 bitMask = FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE; break; \ 98 case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: \ 99 bitMask = FM_PCD_EX_PRS_DOUBLE_ECC; break; \ 100 case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: \ 101 bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \ 102 default: bitMask = 0;break;} 103 104 /***********************************************************************/ 105 /* SW parser L4 shells patch */ 106 /***********************************************************************/ 107 #ifdef FM_PRS_L4_SHELL_ERRATA_FMANb 108 #define SW_PRS_L4_PATCH \ 109 { 0x31,0x92,0x02,0x1f,0x00,0x32,0x00,0x78, \ 110 0x00,0x34,0x32,0xf0,0x00,0x50,0x00,0x0c, \ 111 0x28,0x5e,0x83,0x8e,0x29,0x32,0xaf,0x8e, \ 112 0x31,0xb2,0x9f,0xff,0x00,0x06,0xaf,0xbf, \ 113 0x00,0x06,0x29,0x36,0x00,0x01,0x1b,0xff, \ 114 0x32,0xf0,0x00,0x50,0x00,0x08,0x28,0x5e, \ 115 0x08,0x99,0x00,0x00,0x9f,0x8e,0x31,0xb2, \ 116 0x9f,0xff,0x00,0x06,0x29,0x36,0x00,0x01, \ 117 0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \ 118 0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \ 119 0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \ 120 0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \ 121 0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \ 122 0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \ 123 0x1b,0xff,0x00,0x00,0x00,0x00,0x00,0x00}; 124 125 #define SW_PRS_L4_PATCH_SIZE 120 126 #endif /* FM_PRS_L4_SHELL_ERRATA_FMANb */ 127 128 /****************************/ 129 /* Parser defines */ 130 /****************************/ 131 /* masks */ 132 #define PRS_ERR_CAP 0x80000000 133 #define PRS_ERR_TYPE_DOUBLE 0x40000000 134 #define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000 135 #define PRS_ERR_ADDR_MASK 0x000001FF 136 #define FM_PCD_PRS_RPIMAC_EN 0x00000001 137 #define FM_PCD_PRS_SINGLE_ECC 0x00004000 138 #define FM_PCD_PRS_PORT_IDLE_STS 0xffff0000 139 #define FM_PCD_PRS_DOUBLE_ECC 0x00004000 140 #define FM_PCD_PRS_PPSC_ALL_PORTS 0xffff0000 141 142 /* others */ 143 #define PRS_MAX_CYCLE_LIMIT 8191 144 #define PRS_SW_DATA 0x00000800 145 #define PRS_REGS_OFFSET 0x00000840 146 147 #define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \ 148 prsPortId = (uint8_t)(hardwarePortId & 0x0f) 149 150 #define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \ 151 bitMask = 0x80000000>>prsPortId 152 153 /***********************************************************************/ 154 /* Keygen defines */ 155 /***********************************************************************/ 156 /* Masks */ 157 #define FM_PCD_KG_KGGCR_EN 0x80000000 158 #define KG_SCH_GEN_VALID 0x80000000 159 #define KG_SCH_GEN_EXTRACT_TYPE 0x00008000 160 #define KG_ERR_CAP 0x80000000 161 #define KG_ERR_TYPE_DOUBLE 0x40000000 162 #define KG_ERR_ADDR_MASK 0x00000FFF 163 #define FM_PCD_KG_DOUBLE_ECC 0x80000000 164 #define FM_PCD_KG_KEYSIZE_OVERFLOW 0x40000000 165 #define KG_SCH_MODE_EN 0x80000000 166 167 /* shifts */ 168 #define FM_PCD_KG_PE_CPP_MASK_SHIFT 16 169 #define FM_PCD_KG_KGAR_WSEL_SHIFT 8 170 171 /* others */ 172 #define KG_DOUBLE_MEANING_REGS_OFFSET 0x100 173 #define NO_VALIDATION 0x70 174 #define KG_ACTION_REG_TO 1024 175 #define KG_MAX_PROFILE 255 176 #define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF 177 178 typedef struct { 179 bool known; 180 uint8_t id; 181 } t_FmPcdKgSchemesExtractsEntry; 182 183 typedef struct { 184 t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY]; 185 } t_FmPcdKgSchemesExtracts; 186 187 /***********************************************************************/ 188 /* Policer defines */ 189 /***********************************************************************/ 190 191 /* masks */ 192 #define FM_PCD_PLCR_PEMODE_PI 0x80000000 193 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000 194 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000 195 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000 196 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000 197 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000 198 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000 199 #define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000 200 #define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000 201 #define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000 202 #define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000 203 #define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000 204 #define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000 205 #define FM_PCD_PLCR_PEMODE_PKT 0x00800000 206 #define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000 207 #define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16 208 #define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000 209 #define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000 210 #define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000 211 #define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000 212 #define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000 213 #define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800 214 #define FM_PCD_PLCR_PEMODE_TRA 0x00000004 215 #define FM_PCD_PLCR_PEMODE_TRB 0x00000002 216 #define FM_PCD_PLCR_PEMODE_TRC 0x00000001 217 #define FM_PCD_PLCR_DOUBLE_ECC 0x80000000 218 #define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000 219 #define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000 220 #define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000 221 222 #define FM_PCD_PLCR_NIA_VALID 0x80000000 223 224 #define FM_PCD_PLCR_GCR_EN 0x80000000 225 #define FM_PCD_PLCR_GCR_STEN 0x40000000 226 #define FM_PCD_PLCR_GCR_DAR 0x20000000 227 #define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF 228 #define FM_PCD_PLCR_NIA_ABS 0x00000100 229 230 #define FM_PCD_PLCR_GSR_BSY 0x80000000 231 #define FM_PCD_PLCR_GSR_DQS 0x60000000 232 #define FM_PCD_PLCR_GSR_RPB 0x20000000 233 #define FM_PCD_PLCR_GSR_FQS 0x0C000000 234 #define FM_PCD_PLCR_GSR_LPALG 0x0000C000 235 #define FM_PCD_PLCR_GSR_LPCA 0x00003000 236 #define FM_PCD_PLCR_GSR_LPNUM 0x000000FF 237 238 #define FM_PCD_PLCR_EVR_PSIC 0x80000000 239 #define FM_PCD_PLCR_EVR_AAC 0x40000000 240 241 #define FM_PCD_PLCR_PAR_PSI 0x20000000 242 #define FM_PCD_PLCR_PAR_PNUM 0x00FF0000 243 /* PWSEL Selctive select options */ 244 #define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */ 245 #define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */ 246 #define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */ 247 #define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */ 248 #define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */ 249 #define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */ 250 #define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */ 251 #define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */ 252 #define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */ 253 #define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */ 254 #define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */ 255 #define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */ 256 #define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */ 257 #define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */ 258 #define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */ 259 #define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */ 260 261 #define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1] 262 1-> 2^N specific locations. */ 263 #define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}. 264 2-> 2^(N-1) base locations. */ 265 #define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}. 266 4-> 2^(N-2) base locations. */ 267 #define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}. 268 8->2^(N-3) base locations. */ 269 #define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}. 270 16-> 2^(N-4) base locations. */ 271 #define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}. 272 32-> 2^(N-5) base locations. */ 273 #define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}. 274 64-> 2^(N-6) base locations. */ 275 #define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}. 276 128-> 2^(N-7) base locations. */ 277 #define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}. 278 When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */ 279 280 #define FM_PCD_PLCR_PMR_V 0x80000000 281 #define PLCR_ERR_ECC_CAP 0x80000000 282 #define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000 283 #define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0 284 #define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F 285 286 #define PLCR_ERR_UNINIT_CAP 0x80000000 287 #define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF 288 #define PLCR_ERR_UNINIT_PID_MASK 0x003f0000 289 #define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000 290 291 /* shifts */ 292 #define PLCR_ERR_ECC_PNUM_SHIFT 4 293 #define PLCR_ERR_UNINIT_PID_SHIFT 16 294 295 #define FM_PCD_PLCR_PMR_BRN_SHIFT 16 296 297 /* others */ 298 #define WAIT_FOR_PLCR_EVR_AAC \ 299 {\ 300 uint32_t count = 0; \ 301 uint32_t tmpReg32; \ 302 while (count < FM_PCD_PLCR_POLL) \ 303 { \ 304 tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_evr);\ 305 if (!( tmpReg32 & FM_PCD_PLCR_EVR_AAC)) break;\ 306 count++;\ 307 }\ 308 } 309 310 #define WAIT_FOR_PLCR_PAR_GO \ 311 {\ 312 uint32_t count = 0; \ 313 uint32_t tmpReg32; \ 314 while (count < FM_PCD_PLCR_POLL) \ 315 { \ 316 tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_par);\ 317 if (!( tmpReg32 & FM_PCD_PLCR_PAR_GO)) break;\ 318 count++; \ 319 }\ 320 } 321 322 #define PLCR_PORT_WINDOW_SIZE(hardwarePortId) 323 324 /****************************/ 325 /* Defaults */ 326 /****************************/ 327 #define DEFAULT_plcrAutoRefresh FALSE 328 #define DEFAULT_prsMaxParseCycleLimit 0 329 #define DEFAULT_fmPcdKgErrorExceptions (FM_PCD_EX_KG_DOUBLE_ECC | FM_PCD_EX_KG_KEYSIZE_OVERFLOW) 330 #define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR) 331 #define DEFAULT_fmPcdPlcrExceptions 0 332 #define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC) 333 334 #define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC 335 #define DEFAULT_numOfUsedProfilesPerWindow 16 336 #define DEFAULT_numOfSharedPlcrProfiles 4 337 338 /***********************************************************************/ 339 /* Memory map */ 340 /***********************************************************************/ 341 #if defined(__MWERKS__) && !defined(__GNUC__) 342 #pragma pack(push,1) 343 #endif /* defined(__MWERKS__) && ... */ 344 #define MEM_MAP_START 345 346 typedef _Packed struct { 347 volatile uint32_t kgoe_sp; 348 volatile uint32_t kgoe_cpp; 349 } _PackedType t_FmPcdKgPortConfigRegs; 350 351 typedef _Packed struct { 352 volatile uint32_t kgcpe[8]; 353 } _PackedType t_FmPcdKgClsPlanRegs; 354 355 typedef _Packed union { 356 t_FmPcdKgInterModuleSchemeRegs schemeRegs; 357 t_FmPcdKgPortConfigRegs portRegs; 358 t_FmPcdKgClsPlanRegs clsPlanRegs; 359 } _PackedType u_FmPcdKgIndirectAccessRegs; 360 361 typedef _Packed struct { 362 volatile uint32_t kggcr; 363 volatile uint32_t res0; 364 volatile uint32_t res1; 365 volatile uint32_t kgeer; 366 volatile uint32_t kgeeer; 367 volatile uint32_t res2; 368 volatile uint32_t res3; 369 volatile uint32_t kgseer; 370 volatile uint32_t kgseeer; 371 volatile uint32_t kggsr; 372 volatile uint32_t kgtpc; 373 volatile uint32_t kgserc; 374 volatile uint32_t res4[4]; 375 volatile uint32_t kgfdor; 376 volatile uint32_t kggdv0r; 377 volatile uint32_t kggdv1r; 378 volatile uint32_t res5[5]; 379 volatile uint32_t kgfer; 380 volatile uint32_t kgfeer; 381 volatile uint32_t res6[38]; 382 u_FmPcdKgIndirectAccessRegs indirectAccessRegs; 383 volatile uint32_t res[42]; /*(0xfc-sizeof(u_FmPcdKgIndirectAccessRegs))/4 */ 384 volatile uint32_t kgar; 385 } _PackedType t_FmPcdKgRegs; 386 387 typedef _Packed struct { 388 /* General Configuration and Status Registers */ 389 volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */ 390 volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */ 391 volatile uint32_t fmpl_evr; /* 0x008 FMPL_EVR - FM Policer Event Register */ 392 volatile uint32_t fmpl_ier; /* 0x00C FMPL_IER - FM Policer Interrupt Enable Register */ 393 volatile uint32_t fmpl_ifr; /* 0x010 FMPL_IFR - FM Policer Interrupt Force Register */ 394 volatile uint32_t fmpl_eevr; /* 0x014 FMPL_EEVR - FM Policer Error Event Register */ 395 volatile uint32_t fmpl_eier; /* 0x018 FMPL_EIER - FM Policer Error Interrupt Enable Register */ 396 volatile uint32_t fmpl_eifr; /* 0x01C FMPL_EIFR - FM Policer Error Interrupt Force Register */ 397 /* Global Statistic Counters */ 398 volatile uint32_t fmpl_rpcnt; /* 0x020 FMPL_RPC - FM Policer RED Packets Counter */ 399 volatile uint32_t fmpl_ypcnt; /* 0x024 FMPL_YPC - FM Policer YELLOW Packets Counter */ 400 volatile uint32_t fmpl_rrpcnt; /* 0x028 FMPL_RRPC - FM Policer Recolored RED Packet Counter */ 401 volatile uint32_t fmpl_rypcnt; /* 0x02C FMPL_RYPC - FM Policer Recolored YELLOW Packet Counter */ 402 volatile uint32_t fmpl_tpcnt; /* 0x030 FMPL_TPC - FM Policer Total Packet Counter */ 403 volatile uint32_t fmpl_flmcnt; /* 0x034 FMPL_FLMC - FM Policer Frame Length Mismatch Counter */ 404 volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */ 405 /* Profile RAM Access Registers */ 406 volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/ 407 t_FmPcdPlcrInterModuleProfileRegs profileRegs; 408 /* Error Capture Registers */ 409 volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */ 410 volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */ 411 volatile uint32_t fmpl_res2; /* 0x108 Reserved */ 412 /* Debug Registers */ 413 volatile uint32_t fmpl_res3[61]; /* 0x10C-0x200 Reserved Debug*/ 414 /* Profile Selection Mapping Registers Per Port-ID (n=1-11, 16) */ 415 volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */ 416 volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers. 417 (for port-ID 1-11, only for supported Port-ID registers) */ 418 } _PackedType t_FmPcdPlcrRegs; 419 420 typedef _Packed struct { 421 volatile uint32_t rpclim; 422 volatile uint32_t rpimac; 423 volatile uint32_t pmeec; 424 volatile uint32_t res1[5]; 425 volatile uint32_t pevr; 426 volatile uint32_t pever; 427 volatile uint32_t pevfr; 428 volatile uint32_t perr; 429 volatile uint32_t perer; 430 volatile uint32_t perfr; 431 volatile uint32_t res2[0xA]; 432 volatile uint32_t ppsc; 433 volatile uint32_t res3; 434 volatile uint32_t pds; 435 volatile uint32_t l2rrs; 436 volatile uint32_t l3rrs; 437 volatile uint32_t l4rrs; 438 volatile uint32_t srrs; 439 volatile uint32_t l2rres; 440 volatile uint32_t l3rres; 441 volatile uint32_t l4rres; 442 volatile uint32_t srres; 443 volatile uint32_t spcs; 444 volatile uint32_t spscs; 445 volatile uint32_t hxscs; 446 volatile uint32_t mrcs; 447 volatile uint32_t mwcs; 448 volatile uint32_t mrscs; 449 volatile uint32_t mwscs; 450 volatile uint32_t fcscs; 451 } _PackedType t_FmPcdPrsRegs; 452 453 #define MEM_MAP_END 454 #if defined(__MWERKS__) && !defined(__GNUC__) 455 #pragma pack(pop) 456 #endif /* defined(__MWERKS__) && ... */ 457 458 459 /***********************************************************************/ 460 /* Driver's internal structures */ 461 /***********************************************************************/ 462 463 typedef struct { 464 t_Handle h_Manip; 465 bool keepRes; 466 e_FmPcdEngine nextEngine; 467 uint8_t parseCode; 468 } t_FmPcdInfoForManip; 469 470 /**************************************************************************//** 471 @Description A structure of parameters to communicate 472 between the port and PCD regarding the KG scheme. 473 *//***************************************************************************/ 474 typedef struct { 475 uint8_t netEnvId; /* in */ 476 uint8_t numOfDistinctionUnits; /* in */ 477 uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */ 478 uint32_t vector; /* out */ 479 } t_NetEnvParams; 480 481 typedef struct { 482 volatile bool lock; 483 bool used; 484 uint8_t owners; 485 uint8_t netEnvId; 486 uint8_t guestId; 487 uint8_t baseEntry; 488 uint16_t sizeOfGrp; 489 protocolOpt_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)]; 490 } t_FmPcdKgClsPlanGrp; 491 492 typedef struct { 493 volatile bool lock; 494 bool valid; 495 uint8_t netEnvId; 496 uint8_t owners; 497 uint32_t matchVector; 498 uint32_t ccUnits; 499 bool nextRelativePlcrProfile; 500 uint16_t relativeProfileId; 501 uint16_t numOfProfiles; 502 t_FmPcdKgKeyOrder orderedArray; 503 e_FmPcdEngine nextEngine; 504 e_FmPcdDoneAction doneAction; 505 uint8_t pointedOwners; 506 uint32_t requiredAction; 507 bool extractedOrs; 508 uint8_t bitOffsetInPlcrProfile; 509 bool directPlcr; 510 } t_FmPcdKgScheme; 511 512 typedef struct { 513 bool allocated; 514 uint8_t ownerId; /* guestId for KG in multi-partition only, 515 portId for PLCR in any environment */ 516 } t_FmPcdAllocMng; 517 518 typedef struct { 519 t_FmPcdKgRegs *p_FmPcdKgRegs; 520 uint32_t schemeExceptionsBitMask; 521 uint8_t numOfSchemes; 522 uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; 523 t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES]; 524 t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS]; 525 uint8_t emptyClsPlanGrpId; 526 t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */ 527 t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP]; 528 } t_FmPcdKg; 529 530 typedef struct { 531 uint16_t profilesBase; 532 uint16_t numOfProfiles; 533 t_Handle h_FmPort; 534 } t_FmPcdPlcrMapParam; 535 536 typedef struct { 537 bool valid; 538 volatile bool lock; 539 t_FmPcdAllocMng profilesMng; 540 uint8_t pointedOwners; 541 uint32_t requiredAction; 542 e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */ 543 u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */ 544 545 e_FmPcdEngine nextEngineOnYellow; /**< Yellow next engine type */ 546 u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Yellow next engine params */ 547 548 e_FmPcdEngine nextEngineOnRed; /**< Red next engine type */ 549 u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Red next engine params */ 550 } t_FmPcdPlcrProfile; 551 552 typedef struct { 553 t_FmPcdPlcrRegs *p_FmPcdPlcrRegs; 554 t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES]; 555 uint16_t numOfSharedProfiles; 556 uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES]; 557 t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS]; 558 } t_FmPcdPlcr; 559 560 typedef struct { 561 uint32_t *p_SwPrsCode; 562 uint32_t *p_CurrSwPrs; 563 uint8_t currLabel; 564 t_FmPcdPrsRegs *p_FmPcdPrsRegs; 565 t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS]; 566 uint32_t fmPcdPrsPortIdStatistics; 567 } t_FmPcdPrs; 568 569 typedef struct { 570 struct { 571 e_NetHeaderType hdr; 572 protocolOpt_t opt; /* only one option !! */ 573 } hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS]; 574 } t_FmPcdIntDistinctionUnit; 575 576 typedef struct { 577 e_NetHeaderType hdr; 578 e_NetHeaderType aliasHdr; 579 } t_FmPcdNetEnvAliases; 580 581 typedef struct { 582 volatile bool lock; 583 bool used; 584 uint8_t owners; 585 uint8_t clsPlanGrpId; 586 t_FmPcdIntDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; 587 uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; 588 uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS]; 589 uint32_t macsecVector; 590 t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_PRIVATE_HDRS]; 591 } t_FmPcdNetEnv; 592 593 typedef struct { 594 bool plcrAutoRefresh; 595 596 uint16_t prsMaxParseCycleLimit; 597 } t_FmPcdDriverParam; 598 599 typedef struct { 600 t_Handle h_Fm; 601 t_Handle h_FmMuram; 602 uint64_t physicalMuramBase; 603 volatile bool lock; 604 t_Handle h_Spinlock; 605 t_Handle h_IpcSession; /* relevant for guest only */ 606 bool enabled; 607 uint8_t guestId; /**< Guest Partition Id */ 608 uint8_t numOfEnabledGuestPartitionsPcds; 609 char fmPcdModuleName[MODULE_NAME_SIZE]; 610 char fmPcdIpcHandlerModuleName[MODULE_NAME_SIZE]; /* relevant for guest only - this is the master's name */ 611 t_FmPcdNetEnv netEnvs[FM_MAX_NUM_OF_PORTS]; 612 t_FmPcdKg *p_FmPcdKg; 613 t_FmPcdPlcr *p_FmPcdPlcr; 614 t_FmPcdPrs *p_FmPcdPrs; 615 616 t_Handle h_Hc; 617 618 uint32_t exceptions; 619 t_FmPcdExceptionCallback *f_Exception; 620 t_FmPcdIdExceptionCallback *f_FmPcdIndexedException; 621 t_Handle h_App; 622 623 t_FmPcdDriverParam *p_FmPcdDriverParam; 624 } t_FmPcd; 625 626 627 /***********************************************************************/ 628 /* PCD internal routines */ 629 /***********************************************************************/ 630 631 /**************************************************************************//** 632 633 @Group FM_PCD_InterModule_grp FM PCD Inter-Module Unit 634 635 @Description FM PCD Inter Module functions - 636 These are not User API routines but routines that may be called 637 from other modules. This will be the case in a single core environment, 638 where instead of useing the XX messeging mechanism, the routines may be 639 called from other modules. In a multicore environment, the other modules may 640 be run by other cores and therefor these routines may not be called directly. 641 642 @{ 643 *//***************************************************************************/ 644 645 t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector); 646 t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params); 647 bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector); 648 t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams); 649 void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId); 650 e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); 651 uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr); 652 653 t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams); 654 t_Error KgInit(t_FmPcd *p_FmPcd); 655 t_Error KgFree(t_FmPcd *p_FmPcd); 656 void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set); 657 bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId); 658 void KgEnable(t_FmPcd *p_FmPcd); 659 void KgDisable(t_FmPcd *p_FmPcd); 660 t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First); 661 void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base); 662 663 /* only for MULTI partittion */ 664 t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds); 665 t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds); 666 /* only for SINGLE partittion */ 667 t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg); 668 669 t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams); 670 t_Error PlcrInit(t_FmPcd *p_FmPcd); 671 t_Error PlcrFree(t_FmPcd *p_FmPcd); 672 void PlcrEnable(t_FmPcd *p_FmPcd); 673 void PlcrDisable(t_FmPcd *p_FmPcd); 674 t_Error PlcrFreeProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t num, uint16_t base); 675 t_Error PlcrAllocProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles, uint16_t *p_Base); 676 t_Error PlcrAllocSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds); 677 void PlcrFreeSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds); 678 679 t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams); 680 t_Error PrsInit(t_FmPcd *p_FmPcd); 681 void PrsEnable(t_FmPcd *p_FmPcd); 682 void PrsDisable(t_FmPcd *p_FmPcd); 683 void PrsFree(t_FmPcd *p_FmPcd ); 684 t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include); 685 686 t_Handle FmPcdCcConfig(t_Handle h_FmPcd, t_FmPcdParams *p_FmPcdParams); 687 t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase); 688 uint8_t FmPcdCcGetOffset(t_Handle h_CcNode); 689 uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode); 690 uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode); 691 692 void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add); 693 t_Error FmPcdManipCheckParamsForCcNextEgine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction); 694 void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew); 695 void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset); 696 uint32_t FmPcdManipCheckNia(t_Handle h_FmPcd, t_Handle h_Ad); 697 void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add); 698 t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode); 699 700 static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd) 701 { 702 t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; 703 ASSERT_COND(p_FmPcd); 704 return p_FmPcd->h_FmMuram; 705 } 706 707 static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd) 708 { 709 t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd; 710 ASSERT_COND(p_FmPcd); 711 return p_FmPcd->physicalMuramBase; 712 } 713 714 715 #endif /* __FM_PCD_H */ 716