1 /* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34 #include "error_ext.h" 35 #include "std_ext.h" 36 #include "fm_mac.h" 37 #include "tgec.h" 38 #include "xx_ext.h" 39 40 41 /*****************************************************************************/ 42 t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, 43 uint8_t phyAddr, 44 uint8_t reg, 45 uint16_t data) 46 { 47 t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; 48 t_TgecMiiAccessMemMap *p_MiiAccess; 49 50 SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); 51 SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); 52 53 p_MiiAccess = p_Tgec->p_MiiMemMap; 54 55 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 56 XX_UDelay (1); 57 58 WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); 59 60 WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); 61 62 CORE_MemoryBarrier(); 63 64 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 65 XX_UDelay (1); 66 67 WRITE_UINT32(p_MiiAccess->mdio_data, data); 68 69 CORE_MemoryBarrier(); 70 71 while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) 72 XX_UDelay (1); 73 74 return E_OK; 75 } 76 77 /*****************************************************************************/ 78 t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, 79 uint8_t phyAddr, 80 uint8_t reg, 81 uint16_t *p_Data) 82 { 83 t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; 84 t_TgecMiiAccessMemMap *p_MiiAccess; 85 uint32_t cfg_status; 86 87 SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); 88 SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); 89 90 p_MiiAccess = p_Tgec->p_MiiMemMap; 91 92 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 93 XX_UDelay (1); 94 95 WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); 96 97 WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); 98 99 CORE_MemoryBarrier(); 100 101 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 102 XX_UDelay (1); 103 104 WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE)); 105 106 CORE_MemoryBarrier(); 107 108 while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) 109 XX_UDelay (1); 110 111 *p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data); 112 113 cfg_status = GET_UINT32(p_MiiAccess->mdio_cfg_status); 114 115 if (cfg_status & MIIMIND_READ_ERROR) 116 RETURN_ERROR(MINOR, E_INVALID_VALUE, 117 ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfg_status 0x%x", 118 ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfg_status)); 119 120 return E_OK; 121 } 122