1 /* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /****************************************************************************** 34 @File tgec.h 35 36 @Description FM 10G MAC ... 37 *//***************************************************************************/ 38 #ifndef __TGEC_H 39 #define __TGEC_H 40 41 #include "std_ext.h" 42 #include "error_ext.h" 43 #include "list_ext.h" 44 #include "tgec_mii_acc.h" 45 #include "fm_mac.h" 46 47 48 /* Interrupt Mask Register (IMASK) */ 49 #define IMASK_MDIO_SCAN_EVENTMDIO 0x00010000 /* MDIO_SCAN_EVENTMDIO scan event interrupt mask. 50 * 0 masked 51 * 1 enabled 52 */ 53 #define IMASK_MDIO_CMD_CMPL 0x00008000 /* 16 MDIO_CMD_CMPL MDIO command completion interrupt mask. 54 * 0 masked 55 * 1 enabled 56 */ 57 #define IMASK_REM_FAULT 0x00004000 /* 17 REM_FAULT Remote fault interrupt mask. 58 * 0 masked 59 * 1 enabled 60 */ 61 #define IMASK_LOC_FAULT 0x00002000 /* 18 LOC_FAULT Local fault interrupt mask. 62 * 0 masked 63 * 1 enabled 64 */ 65 #define IMASK_1TX_ECC_ER 0x00001000 /* 19 TX_ECC_ER Transmit frame ECC error interrupt mask. 66 * 0 masked 67 * 1 enabled 68 */ 69 #define IMASK_TX_FIFO_UNFL 0x00000800 /* 20 TX_FIFO_UNFL Transmit FIFO underflow interrupt mask. 70 * 0 masked 71 * 1 enabled 72 */ 73 #define IMASK_TX_FIFO_OVFL 0x00000400 /* 21 TX_FIFO_OVFL Transmit FIFO overflow interrupt mask. 74 * 0 masked 75 * 1 enabled 76 */ 77 #define IMASK_TX_ER 0x00000200 /* 22 TX_ER Transmit frame error interrupt mask. 78 * 0 masked 79 * 1 enabled 80 */ 81 #define IMASK_RX_FIFO_OVFL 0x00000100 /* 23 RX_FIFO_OVFL Receive FIFO overflow interrupt mask. 82 * 0 masked 83 * 1 enabled 84 */ 85 #define IMASK_RX_ECC_ER 0x00000080 /* 24 RX_ECC_ER Receive frame ECC error interrupt mask. 86 * 0 masked 87 * 1 enabled 88 */ 89 #define IMASK_RX_JAB_FRM 0x00000040 /* 25 RX_JAB_FRM Receive jabber frame interrupt mask. 90 * 0 masked 91 * 1 enabled 92 */ 93 #define IMASK_RX_OVRSZ_FRM 0x00000020 /* 26 RX_OVRSZ_FRM Receive oversized frame interrupt mask. 94 * 0 masked 95 * 1 enabled 96 */ 97 #define IMASK_RX_RUNT_FRM 0x00000010 /* 27 RX_RUNT_FRM Receive runt frame interrupt mask. 98 * 0 masked 99 * 1 enabled 100 */ 101 #define IMASK_RX_FRAG_FRM 0x00000008 /* 28 RX_FRAG_FRM Receive fragment frame interrupt mask. 102 * 0 masked 103 * 1 enabled 104 */ 105 #define IMASK_RX_LEN_ER 0x00000004 /* 29 RX_LEN_ER Receive payload length error interrupt mask. 106 * 0 masked 107 * 1 enabled 108 */ 109 #define IMASK_RX_CRC_ER 0x00000002 /* 30 RX_CRC_ER Receive CRC error interrupt mask. 110 * 0 masked 111 * 1 enabled 112 */ 113 #define IMASK_RX_ALIGN_ER 0x00000001 /* 31 RX_ALIGN_ER Receive alignment error interrupt mask. 114 * 0 masked 115 * 1 enabled 116 */ 117 118 #define EVENTS_MASK ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \ 119 IMASK_MDIO_CMD_CMPL | \ 120 IMASK_REM_FAULT | \ 121 IMASK_LOC_FAULT | \ 122 IMASK_1TX_ECC_ER | \ 123 IMASK_TX_FIFO_UNFL | \ 124 IMASK_TX_FIFO_OVFL | \ 125 IMASK_TX_ER | \ 126 IMASK_RX_FIFO_OVFL | \ 127 IMASK_RX_ECC_ER | \ 128 IMASK_RX_JAB_FRM | \ 129 IMASK_RX_OVRSZ_FRM | \ 130 IMASK_RX_RUNT_FRM | \ 131 IMASK_RX_FRAG_FRM | \ 132 IMASK_RX_LEN_ER | \ 133 IMASK_RX_CRC_ER | \ 134 IMASK_RX_ALIGN_ER)) 135 136 #define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \ 137 case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \ 138 bitMask = IMASK_MDIO_SCAN_EVENTMDIO; break; \ 139 case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \ 140 bitMask = IMASK_MDIO_CMD_CMPL ; break; \ 141 case e_FM_MAC_EX_10G_REM_FAULT: \ 142 bitMask = IMASK_REM_FAULT ; break; \ 143 case e_FM_MAC_EX_10G_LOC_FAULT: \ 144 bitMask = IMASK_LOC_FAULT ; break; \ 145 case e_FM_MAC_EX_10G_1TX_ECC_ER: \ 146 bitMask = IMASK_1TX_ECC_ER ; break; \ 147 case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \ 148 bitMask = IMASK_TX_FIFO_UNFL ; break; \ 149 case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \ 150 bitMask = IMASK_TX_FIFO_OVFL ; break; \ 151 case e_FM_MAC_EX_10G_TX_ER: \ 152 bitMask = IMASK_TX_ER ; break; \ 153 case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \ 154 bitMask = IMASK_RX_FIFO_OVFL ; break; \ 155 case e_FM_MAC_EX_10G_RX_ECC_ER: \ 156 bitMask = IMASK_RX_ECC_ER ; break; \ 157 case e_FM_MAC_EX_10G_RX_JAB_FRM: \ 158 bitMask = IMASK_RX_JAB_FRM ; break; \ 159 case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \ 160 bitMask = IMASK_RX_OVRSZ_FRM ; break; \ 161 case e_FM_MAC_EX_10G_RX_RUNT_FRM: \ 162 bitMask = IMASK_RX_RUNT_FRM ; break; \ 163 case e_FM_MAC_EX_10G_RX_FRAG_FRM: \ 164 bitMask = IMASK_RX_FRAG_FRM ; break; \ 165 case e_FM_MAC_EX_10G_RX_LEN_ER: \ 166 bitMask = IMASK_RX_LEN_ER ; break; \ 167 case e_FM_MAC_EX_10G_RX_CRC_ER: \ 168 bitMask = IMASK_RX_CRC_ER ; break; \ 169 case e_FM_MAC_EX_10G_RX_ALIGN_ER: \ 170 bitMask = IMASK_RX_ALIGN_ER ; break; \ 171 default: bitMask = 0;break;} 172 173 174 /* Default Config Params */ 175 #define DEFAULT_wanModeEnable FALSE 176 #define DEFAULT_promiscuousModeEnable FALSE 177 178 179 #define DEFAULT_pauseForwardEnable FALSE 180 #define DEFAULT_pauseIgnore FALSE 181 #define DEFAULT_txAddrInsEnable FALSE 182 183 #define DEFAULT_loopbackEnable FALSE 184 #define DEFAULT_cmdFrameEnable FALSE 185 #define DEFAULT_rxErrorDiscard FALSE 186 #define DEFAULT_phyTxenaOn FALSE 187 #define DEFAULT_sendIdleEnable FALSE 188 #define DEFAULT_noLengthCheckEnable TRUE 189 #define DEFAULT_lgthCheckNostdr FALSE 190 #define DEFAULT_timeStampEnable FALSE 191 #define DEFAULT_rxSfdAny FALSE 192 #define DEFAULT_rxPblFwd FALSE 193 #define DEFAULT_txPblFwd FALSE 194 #define DEFAULT_txIpgLength 12 195 196 #define DEFAULT_maxFrameLength 0x600 197 198 #define DEFAULT_debugMode FALSE 199 #define DEFAULT_pauseTime 0xf000 200 #define DEFAULT_imask 0xf000 201 #ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 202 #define DEFAULT_skipFman11Workaround FALSE 203 #endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ 204 205 #define DEFAULT_exceptions ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \ 206 IMASK_REM_FAULT | \ 207 IMASK_LOC_FAULT | \ 208 IMASK_1TX_ECC_ER | \ 209 IMASK_TX_FIFO_UNFL | \ 210 IMASK_TX_FIFO_OVFL | \ 211 IMASK_TX_ER | \ 212 IMASK_RX_FIFO_OVFL | \ 213 IMASK_RX_ECC_ER | \ 214 IMASK_RX_JAB_FRM | \ 215 IMASK_RX_OVRSZ_FRM | \ 216 IMASK_RX_RUNT_FRM | \ 217 IMASK_RX_FRAG_FRM | \ 218 IMASK_RX_CRC_ER | \ 219 IMASK_RX_ALIGN_ER)) 220 221 #define MAX_PACKET_ALIGNMENT 31 222 #define MAX_INTER_PACKET_GAP 0x7f 223 #define MAX_INTER_PALTERNATE_BEB 0x0f 224 #define MAX_RETRANSMISSION 0x0f 225 #define MAX_COLLISION_WINDOW 0x03ff 226 227 228 #define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */ 229 230 #define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */ 231 232 #define HASH_TABLE_SIZE 512 /* Hash table size (= 32 bits * 8 regs) */ 233 234 #define TGEC_TO_MII_OFFSET 0x1030 /* Offset from the MEM map to the MDIO mem map */ 235 236 /* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */ 237 #define TGEC_ID_ID 0xffff0000 238 #define TGEC_ID_MAC_VERSION 0x0000FF00 239 #define TGEC_ID_MAC_REV 0x000000ff 240 241 /* Command and Configuration Register (COMMAND_CONFIG) */ 242 #define CMD_CFG_TX_PBL_FWD 0x00800000 /* 08 Transmit Preamble Forwarding (custom preamble). 243 */ 244 #define CMD_CFG_RX_PBL_FWD 0x00400000 /* 09 Receive Preamble Forwarding (custom preamble). 245 */ 246 #define RX_SFD_ANY 0x00200000 /* 10 Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted. 247 */ 248 #define CMD_CFG_EN_TIMESTAMP 0x00100000 /* 11 EN_TIMESTAMP IEEE 1588 timeStamp functionality control. 249 * 0 disabled 250 * 1 enabled 251 */ 252 #define CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* 12 TX_ADDR_INS_SEL Transmit MAC address select 253 * 0 insert using first MAC address 254 * 1 insert using second MAC address 255 */ 256 #define CMD_CFG_LEN_CHK_NOSTDR 0x00040000 /* 13 LEN_CHK_NOSTDR 257 */ 258 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 NO_LEN_CHK Payload length check disable 259 * 0 MAC compares the frame payload length with the frame length/type field. 260 * 1 Payload length check is disabled. 261 */ 262 #define CMD_CFG_SEND_IDLE 0x00010000 /* 15 SEND_IDLE Force idle generation 263 * 0 Normal operation. 264 * 1 MAC permanently sends XGMII idle sequences even when faults are received. 265 */ 266 #define CMD_CFG_PHY_TX_EN 0x00008000 /* 16 PHY_TX_EN PHY transmit enable 267 * 0 PHY transmit is disabled. 268 * 1 PHY transmit is enabled. 269 */ 270 #define CMD_CFG_RX_ER_DISC 0x00004000 /* 17 RX_ER_DISC Receive error frame discard enable 271 * 0 Received error frames are processed. 272 * 1 Any frame received with an error is discarded. 273 */ 274 #define CMD_CFG_CMD_FRM_EN 0x00002000 /* 18 CMD_FRM_EN Command frame reception enable 275 * 0 Only Pause frames are accepted (all other command frames are rejected). 276 * 1 All command frames are accepted. 277 */ 278 #define CMD_CFG_STAT_CLR 0x00001000 /* 19 STAT_CLR Clear statistics 279 * 0 Normal operations. 280 * 1 All statistics counters are cleared. 281 */ 282 #define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 LOOPBAC_EN PHY interface loopback enable 283 * 0 Configure PHY for normal operation. 284 * 1 Configure PHY for loopback mode. 285 */ 286 #define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 TX_ADDR_INS Transmit source MAC address insertion 287 * 0 MAC transmits the source MAC address unmodified. 288 * 1 MAC overwrites the source MAC address with address specified by COMMAND_CONFIG[TX_ADDR_INS_SEL]. 289 */ 290 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 PAUSE_IGNORE Ignore Pause frame quanta 291 * 0 MAC stops transmit process for the duration specified in the Pause frame quanta of a received Pause frame. 292 * 1 MAC ignores received Pause frames. 293 */ 294 #define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 PAUSE_FWD Terminate/forward received Pause frames 295 * 0 MAC terminates and discards received Pause frames. 296 * 1 MAC forwards Pause frames to the user application. 297 */ 298 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 PROMIS_EN Promiscuous operation enable 299 * 0 Unicast frames with a destination address not matching the core MAC address (defined by registers, MAC_ADDR_0 and MAC_ADDR_1) are rejected. 300 * 1 All frames are received without any MAC address filtering. 301 */ 302 #define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN_MODE WAN mode enable 303 * 0 Configure MAC for LAN mode. 304 * 1 Configure MAC for WAN mode. 305 */ 306 #define CMD_CFG_RX_EN 0x00000002 /* 30 RX_EN MAC receive path enable 307 * 0 MAC receive path is disabled 308 * 1 MAC receive path is enabled. 309 */ 310 #define CMD_CFG_TX_EN 0x00000001 /* 31 TX_EN MAC transmit path enable 311 * 0 MAC transmit path is disabled 312 * 1 MAC transmit path is enabled. 313 */ 314 315 /* Hashtable Control Register (HASHTABLE_CTRL) */ 316 #define HASH_CTRL_MCAST_SHIFT 23 317 318 #define HASH_CTRL_MCAST_RD 0x00000400 /* 22 MCAST_READ Entry Multicast frame reception for the hash entry. 319 * 0 disabled 320 * 1 enabled 321 */ 322 #define HASH_CTRL_MCAST_EN 0x00000200 /* 22 MCAST_EN Multicast frame reception for the hash entry. 323 * 0 disabled 324 * 1 enabled 325 */ 326 #define HASH_ADDR_MASK 0x000001ff /* 23-31 HASH_ADDR Hash table address code. 327 */ 328 329 /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */ 330 #define TX_IPG_LENGTH_MASK 0x000003ff 331 332 333 334 #if defined(__MWERKS__) && !defined(__GNUC__) 335 #pragma pack(push,1) 336 #endif /* defined(__MWERKS__) && ... */ 337 #define MEM_MAP_START 338 339 /* 340 * 10G memory map 341 */ 342 typedef _Packed struct { 343 /* 10Ge General Control and Status */ 344 volatile uint32_t tgec_id; /* 0x000 10GEC_ID - Controller ID register */ 345 volatile uint32_t scratch; /* 0x004 */ 346 volatile uint32_t cmd_conf_ctrl; /* 0x008 COMMAND_CONFIG - Control and configuration register */ 347 volatile uint32_t mac_addr_0; /* 0x00C MAC_ADDR_0 - Lower 32 bits of the first 48-bit MAC address */ 348 volatile uint32_t mac_addr_1; /* 0x010 MAC_ADDR_1 - Upper 16 bits of the first 48-bit MAC address */ 349 volatile uint32_t maxfrm; /* 0x014 MAXFRM - Maximum frame length register */ 350 volatile uint32_t pause_quant; /* 0x018 PAUSE_QUANT - Pause quanta register */ 351 volatile uint32_t rx_fifo_sections; /* 0x01c */ 352 volatile uint32_t tx_fifo_sections; /* 0x020 */ 353 volatile uint32_t rx_fifo_almost_f_e; /* 0x024 */ 354 volatile uint32_t tx_fifo_almost_f_e; /* 0x028 */ 355 volatile uint32_t hashtable_ctrl; /* 0x02C HASHTABLE_CTRL - Hash table control register */ 356 volatile uint32_t mdio_cfg_status; /* 0x030 */ 357 volatile uint32_t mdio_command; /* 0x034 */ 358 volatile uint32_t mdio_data; /* 0x038 */ 359 volatile uint32_t mdio_regaddr; /* 0x03c */ 360 volatile uint32_t status; /* 0x040 */ 361 volatile uint32_t tx_ipg_len; /* 0x044 TX_IPG_LENGTH - Transmitter inter-packet-gap register */ 362 volatile uint32_t mac_addr_2; /* 0x048 MAC_ADDR_2 - Lower 32 bits of the second 48-bit MAC address */ 363 volatile uint32_t mac_addr_3; /* 0x04C MAC_ADDR_3 - Upper 16 bits of the second 48-bit MAC address */ 364 volatile uint32_t rx_fifo_ptr_rd; /* 0x050 */ 365 volatile uint32_t rx_fifo_ptr_wr; /* 0x054 */ 366 volatile uint32_t tx_fifo_ptr_rd; /* 0x058 */ 367 volatile uint32_t tx_fifo_ptr_wr; /* 0x05c */ 368 volatile uint32_t imask; /* 0x060 IMASK - Interrupt mask register */ 369 volatile uint32_t ievent; /* 0x064 IEVENT - Interrupt event register */ 370 volatile uint32_t udp_port; /* 0x068 Defines a UDP Port number. When an UDP/IP frame is received with a matching UDP destination port, the receive status indication pin ff_rx_ts_frm will be asserted.*/ 371 volatile uint32_t type_1588v2; /* 0x06c Type field for 1588v2 layer 2 frames. IEEE1588 defines the type 0x88f7 for 1588 frames. */ 372 volatile uint32_t TENGEC_RESERVED4[4]; 373 /*10Ge Statistics Counter */ 374 volatile uint64_t TFRM; /* 80 aFramesTransmittedOK */ 375 volatile uint64_t RFRM; /* 88 aFramesReceivedOK */ 376 volatile uint64_t RFCS; /* 90 aFrameCheckSequenceErrors */ 377 volatile uint64_t RALN; /* 98 aAlignmentErrors */ 378 volatile uint64_t TXPF; /* A0 aPAUSEMACCtrlFramesTransmitted */ 379 volatile uint64_t RXPF; /* A8 aPAUSEMACCtrlFramesReceived */ 380 volatile uint64_t RLONG; /* B0 aFrameTooLongErrors */ 381 volatile uint64_t RFLR; /* B8 aInRangeLengthErrors */ 382 volatile uint64_t TVLAN; /* C0 VLANTransmittedOK */ 383 volatile uint64_t RVLAN; /* C8 VLANReceivedOK */ 384 volatile uint64_t TOCT; /* D0 ifOutOctets */ 385 volatile uint64_t ROCT; /* D8 ifInOctets */ 386 volatile uint64_t RUCA; /* E0 ifInUcastPkts */ 387 volatile uint64_t RMCA; /* E8 ifInMulticastPkts */ 388 volatile uint64_t RBCA; /* F0 ifInBroadcastPkts */ 389 volatile uint64_t TERR; /* F8 ifOutErrors */ 390 volatile uint32_t TENGEC_RESERVED6[2]; 391 volatile uint64_t TUCA; /* 108 ifOutUcastPkts */ 392 volatile uint64_t TMCA; /* 110 ifOutMulticastPkts */ 393 volatile uint64_t TBCA; /* 118 ifOutBroadcastPkts */ 394 volatile uint64_t RDRP; /* 120 etherStatsDropEvents */ 395 volatile uint64_t REOCT; /* 128 etherStatsOctets */ 396 volatile uint64_t RPKT; /* 130 etherStatsPkts */ 397 volatile uint64_t TRUND; /* 138 etherStatsUndersizePkts */ 398 volatile uint64_t R64; /* 140 etherStatsPkts64Octets */ 399 volatile uint64_t R127; /* 148 etherStatsPkts65to127Octets */ 400 volatile uint64_t R255; /* 150 etherStatsPkts128to255Octets */ 401 volatile uint64_t R511; /* 158 etherStatsPkts256to511Octets */ 402 volatile uint64_t R1023; /* 160 etherStatsPkts512to1023Octets */ 403 volatile uint64_t R1518; /* 168 etherStatsPkts1024to1518Octets */ 404 volatile uint64_t R1519X; /* 170 etherStatsPkts1519toX */ 405 volatile uint64_t TROVR; /* 178 etherStatsOversizePkts */ 406 volatile uint64_t TRJBR; /* 180 etherStatsJabbers */ 407 volatile uint64_t TRFRG; /* 188 etherStatsFragments */ 408 volatile uint64_t RERR; /* 190 ifInErrors */ 409 } _PackedType t_TgecMemMap; 410 411 #define MEM_MAP_END 412 #if defined(__MWERKS__) && !defined(__GNUC__) 413 #pragma pack(pop) 414 #endif /* defined(__MWERKS__) && ... */ 415 416 417 typedef struct { 418 bool wanModeEnable; /* WAN Mode Enable. Sets WAN mode (1) or LAN mode (0, default) of operation. */ 419 bool promiscuousModeEnable; /* Enables MAC promiscuous operation. When set to '1', all frames are received without any MAC address filtering, when set to '0' (Reset value) Unicast Frames with a destination address not matching the Core MAC Address (MAC Address programmed in Registers MAC_ADDR_0 and MAC_ADDR_1 or the MAC address programmed in Registers MAC_ADDR_2 and MAC_ADDR_3 ) are rejected. */ 420 bool pauseForwardEnable; /* Terminate / Forward Pause Frames. If set to '1' pause frames are forwarded to the user application. When set to '0' (Reset value) pause frames are terminated and discarded within the MAC. */ 421 bool pauseIgnore; /* Ignore Pause Frame Quanta. If set to '1' received pause frames are ignored by the MAC. When set to '0' (Reset value) the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame. */ 422 bool txAddrInsEnable; /* Set Source MAC Address on Transmit. 423 If set to '1' the MAC overwrites the source MAC address received from the Client Interface with one of the MAC addresses (Refer to section 10.4) 424 If set to '0' (Reset value), the source MAC address from the Client Interface is transmitted unmodified to the line. */ 425 bool loopbackEnable; /* PHY Interface Loopback. When set to '1', the signal loop_ena is set to '1', when set to '0' (Reset value) the signal loop_ena is set to '0'. */ 426 bool cmdFrameEnable; /* Enables reception of all command frames. When set to '1' all Command Frames are accepted, when set to '0' (Reset Value) only Pause Frames are accepted and all other Command Frames are rejected. */ 427 bool rxErrorDiscard; /* Receive Errored Frame Discard Enable. When set to �1�, any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to �0� (Reset value), errored Frames are forwarded to the Client interface with ff_rx_err asserted. */ 428 bool phyTxenaOn; /* PHY Transmit Enable. When set to '1', the signal phy_txena is set to '1', when set to '0' (Reset value) the signal phy_txena is set to '0' */ 429 bool sendIdleEnable; /* Force Idle Generation. When set to '1', the MAC permanently sends XGMII Idle sequences even when faults are received. */ 430 bool noLengthCheckEnable; /* Payload Length Check Disable. When set to �0� (Reset value), the Core checks the frame's payload length with the Frame Length/Type field, when set to �1�, the payload length check is disabled. */ 431 bool lgthCheckNostdr; /* The Core interprets the Length/Type field differently depending on the value of this Bit */ 432 bool timeStampEnable; /* This bit selects between enabling and disabling the IEEE 1588 functionality. 433 1: IEEE 1588 is enabled. 434 0: IEEE 1588 is disabled. */ 435 bool rxSfdAny; /* Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted. 436 If cleared (default) the frame is accepted only if the 8th byte of the preamble contains the SFD value 0xd5. If another value is received, the frame is discarded and the alignment error counter increments. */ 437 bool rxPblFwd; /* Receive Preamble Forwarding (custom preamble). 438 If set, the first word (ff_rx_sop) of every received frame contains the preamble of the frame. The frame data starts with the 2nd word from the FIFO. 439 If the bit is cleared (default) the preamble is removed from the frame before it is written into the receive FIFO. */ 440 bool txPblFwd; /* Transmit Preamble Forwarding (custom preamble). 441 If set, the first word written into the TX FIFO is considered as frame preamble. The MAC will not add a preamble in front of the frame. Note that bits 7:0 of the preamble word will still be overwritten with the XGMII start character upon transmission. 442 If cleared (default) the MAC */ 443 uint32_t txIpgLength; /*Transmit Inter-Packet-Gap (IPG) value. 444 A 6-bit value: Depending on LAN or WAN mode of operation (see COMMAND_CONFIG, 19.2.1 page 91) the value has the following meaning: 445 - LAN Mode: Number of octets in steps of 4. Valid values are 8, 12, 16, ... 100. DIC is fully supported (see 10.6.1 page 49) for any setting. A default of 12 (reset value) must be set to conform to IEEE802.3ae. Warning: When set to 8, PCS layers may not be able to perform clock rate compensation. 446 - WAN Mode: Stretch factor. Valid values are 4..15. The stretch factor is calculated as (value+1)*8. A default of 12 (reset value) must be set to conform to IEEE 802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). */ 447 /*.. */ 448 uint16_t maxFrameLength; 449 bool debugMode; 450 uint16_t pauseTime; 451 #ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 452 bool skipFman11Workaround; 453 #endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */ 454 } t_TgecDriverParam; 455 456 typedef struct { 457 t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */ 458 t_Handle h_App; /**< Handle to the upper layer application */ 459 t_TgecMemMap *p_MemMap; /**< pointer to 10G memory mapped registers. */ 460 t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */ 461 uint64_t addr; /**< MAC address of device; */ 462 e_EnetMode enetMode; /**< Ethernet physical interface */ 463 t_FmMacExceptionCallback *f_Exception; 464 int mdioIrq; 465 t_FmMacExceptionCallback *f_Event; 466 bool indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */ 467 uint64_t paddr[TGEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */ 468 uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */ 469 t_EthHash *p_MulticastAddrHash; /**< pointer to driver's global address hash table */ 470 t_EthHash *p_UnicastAddrHash; /**< pointer to driver's individual address hash table */ 471 bool debugMode; 472 uint8_t macId; 473 uint32_t exceptions; 474 t_TgecDriverParam *p_TgecDriverParam; 475 } t_Tgec; 476 477 478 t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data); 479 t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); 480 481 482 #endif /* __TGEC_H */ 483