1 /* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /****************************************************************************** 34 @File dtsec.h 35 36 @Description FM dTSEC ... 37 *//***************************************************************************/ 38 #ifndef __DTSEC_H 39 #define __DTSEC_H 40 41 #include "std_ext.h" 42 #include "error_ext.h" 43 #include "list_ext.h" 44 #include "dtsec_mii_acc.h" 45 #include "fm_mac.h" 46 47 48 #define PEMASK_TSRE 0x00010000 49 50 #define IMASK_BREN 0x80000000 51 #define IMASK_RXCEN 0x40000000 52 #define IMASK_MSROEN 0x04000000 53 #define IMASK_GTSCEN 0x02000000 54 #define IMASK_BTEN 0x01000000 55 #define IMASK_TXCEN 0x00800000 56 #define IMASK_TXEEN 0x00400000 57 #define IMASK_LCEN 0x00040000 58 #define IMASK_CRLEN 0x00020000 59 #define IMASK_XFUNEN 0x00010000 60 #define IMASK_ABRTEN 0x00008000 61 #define IMASK_IFERREN 0x00004000 62 #define IMASK_MAGEN 0x00000800 63 #define IMASK_MMRDEN 0x00000400 64 #define IMASK_MMWREN 0x00000200 65 #define IMASK_GRSCEN 0x00000100 66 #define IMASK_TDPEEN 0x00000002 67 #define IMASK_RDPEEN 0x00000001 68 69 #define EVENTS_MASK ((uint32_t)(IMASK_BREN | \ 70 IMASK_RXCEN | \ 71 IMASK_MSROEN | \ 72 IMASK_GTSCEN | \ 73 IMASK_BTEN | \ 74 IMASK_TXCEN | \ 75 IMASK_TXEEN | \ 76 IMASK_ABRTEN | \ 77 IMASK_LCEN | \ 78 IMASK_CRLEN | \ 79 IMASK_XFUNEN | \ 80 IMASK_IFERREN | \ 81 IMASK_MAGEN | \ 82 IMASK_MMRDEN | \ 83 IMASK_MMWREN | \ 84 IMASK_GRSCEN | \ 85 IMASK_TDPEEN | \ 86 IMASK_RDPEEN)) 87 88 #define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \ 89 case e_FM_MAC_EX_1G_BAB_RX: \ 90 bitMask = IMASK_BREN; break; \ 91 case e_FM_MAC_EX_1G_RX_CTL: \ 92 bitMask = IMASK_RXCEN; break; \ 93 case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \ 94 bitMask = IMASK_GTSCEN ; break; \ 95 case e_FM_MAC_EX_1G_BAB_TX: \ 96 bitMask = IMASK_BTEN ; break; \ 97 case e_FM_MAC_EX_1G_TX_CTL: \ 98 bitMask = IMASK_TXCEN ; break; \ 99 case e_FM_MAC_EX_1G_TX_ERR: \ 100 bitMask = IMASK_TXEEN ; break; \ 101 case e_FM_MAC_EX_1G_LATE_COL: \ 102 bitMask = IMASK_LCEN ; break; \ 103 case e_FM_MAC_EX_1G_COL_RET_LMT: \ 104 bitMask = IMASK_CRLEN ; break; \ 105 case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \ 106 bitMask = IMASK_XFUNEN ; break; \ 107 case e_FM_MAC_EX_1G_MAG_PCKT: \ 108 bitMask = IMASK_MAGEN ; break; \ 109 case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \ 110 bitMask = IMASK_MMRDEN; break; \ 111 case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \ 112 bitMask = IMASK_MMWREN ; break; \ 113 case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \ 114 bitMask = IMASK_GRSCEN; break; \ 115 case e_FM_MAC_EX_1G_TX_DATA_ERR: \ 116 bitMask = IMASK_TDPEEN; break; \ 117 case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \ 118 bitMask = IMASK_MSROEN ; break; \ 119 default: bitMask = 0;break;} 120 121 122 #define MAX_PACKET_ALIGNMENT 31 123 #define MAX_INTER_PACKET_GAP 0x7f 124 #define MAX_INTER_PALTERNATE_BEB 0x0f 125 #define MAX_RETRANSMISSION 0x0f 126 #define MAX_COLLISION_WINDOW 0x03ff 127 128 129 /********************* From mac ext ******************************************/ 130 typedef uint32_t t_ErrorDisable; 131 132 #define ERROR_DISABLE_TRANSMIT 0x00400000 133 #define ERROR_DISABLE_LATE_COLLISION 0x00040000 134 #define ERROR_DISABLE_COLLISION_RETRY_LIMIT 0x00020000 135 #define ERROR_DISABLE_TxFIFO_UNDERRUN 0x00010000 136 #define ERROR_DISABLE_TxABORT 0x00008000 137 #define ERROR_DISABLE_INTERFACE 0x00004000 138 #define ERROR_DISABLE_TxDATA_PARITY 0x00000002 139 #define ERROR_DISABLE_RxDATA_PARITY 0x00000001 140 141 /*****************************************************************************/ 142 #define DTSEC_NUM_OF_PADDRS 15 /* number of pattern match registers (entries) */ 143 144 #define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */ 145 146 #define HASH_TABLE_SIZE 256 /* Hash table size (= 32 bits * 8 regs) */ 147 148 #define DTSEC_TO_MII_OFFSET 0x1120 /* number of pattern match registers (entries) */ 149 150 #define DEFAULT_errorDisabled 0 151 #define DEFAULT_promiscuousEnable FALSE 152 #define DEFAULT_pauseExtended 0x0 153 #define DEFAULT_pauseTime 0xf000 154 #define DEFAULT_halfDuplex FALSE 155 #define DEFAULT_halfDulexFlowControlEn FALSE 156 #define DEFAULT_txTimeStampEn FALSE 157 #define DEFAULT_rxTimeStampEn FALSE 158 #define DEFAULT_packetAlignment 0 159 #define DEFAULT_controlFrameAccept FALSE 160 #define DEFAULT_groupHashExtend FALSE 161 #define DEFAULT_broadcReject FALSE 162 #define DEFAULT_rxShortFrame TRUE 163 #define DEFAULT_exactMatch FALSE 164 #define DEFAULT_debugMode FALSE 165 #define DEFAULT_loopback FALSE 166 #define DEFAULT_actOnRxPauseFrame TRUE 167 #define DEFAULT_actOnTxPauseFrame TRUE 168 169 #define DEFAULT_PreAmLength 0x7 170 #define DEFAULT_PreAmRxEn FALSE 171 #define DEFAULT_PreAmTxEn FALSE 172 #define DEFAULT_lengthCheckEnable FALSE 173 #define DEFAULT_padAndCrcEnable TRUE 174 #define DEFAULT_crcEnable FALSE 175 176 #define DEFAULT_nonBackToBackIpg1 0x40 177 #define DEFAULT_nonBackToBackIpg2 0x60 178 #define DEFAULT_minIfgEnforcement 0x50 179 #define DEFAULT_backToBackIpg 0x60 180 181 #define DEFAULT_altBackoffVal 0x0A 182 #define DEFAULT_altBackoffEnable FALSE 183 #define DEFAULT_backPressureNoBackoff FALSE 184 #define DEFAULT_noBackoff FALSE 185 #define DEFAULT_excessDefer TRUE 186 #define DEFAULT_maxRetransmission 0x0F 187 #define DEFAULT_collisionWindow 0x37 188 189 #define DEFAULT_maxFrameLength 0x600 190 191 #define DEFAULT_collisionWindow 0x37 192 193 #define DEFAULT_fifoTxThr 0x10 194 #define DEFAULT_fifoTxWatermarkH 0x7e 195 #define DEFAULT_fifoRxWatermarkL 0x08 196 #define DEFAULT_tbiPhyAddr 5 197 198 #define DEFAULT_exceptions ((uint32_t)(IMASK_BREN | \ 199 IMASK_RXCEN | \ 200 IMASK_BTEN | \ 201 IMASK_TXCEN | \ 202 IMASK_TXEEN | \ 203 IMASK_ABRTEN | \ 204 IMASK_LCEN | \ 205 IMASK_CRLEN | \ 206 IMASK_XFUNEN | \ 207 IMASK_IFERREN | \ 208 IMASK_MAGEN | \ 209 IMASK_TDPEEN | \ 210 IMASK_RDPEEN)) 211 212 213 #define MAX_PHYS 32 /* maximum number of phys */ 214 215 #define DTSEC_ID1_ID 0xffff0000 216 #define DTSEC_ID1_REV_MJ 0x0000FF00 217 #define DTSEC_ID1_REV_MN 0x000000ff 218 219 #define ID2_INT_REDUCED_OFF 0x00010000 220 #define ID2_INT_NORMAL_OFF 0x00020000 221 222 #define ECNTRL_CLRCNT 0x00004000 223 #define ECNTRL_AUTOZ 0x00002000 224 #define ECNTRL_STEN 0x00001000 225 #define ECNTRL_CFG_RO 0x80000000 226 #define ECNTRL_GMIIM 0x00000040 227 #define ECNTRL_TBIM 0x00000020 228 #define ECNTRL_SGMIIM 0x00000002 229 #define ECNTRL_RPM 0x00000010 230 #define ECNTRL_R100M 0x00000008 231 #define ECNTRL_RMM 0x00000004 232 #define ECNTRL_QSGMIIM 0x00000001 233 234 #define TCTRL_THDF 0x00000800 235 #define TCTRL_TTSE 0x00000040 236 #define TCTRL_GTS 0x00000020 237 #define TCTRL_TFC_PAUSE 0x00000010 238 239 /* PTV offsets */ 240 #define PTV_PTE_OFST 16 241 242 #define RCTRL_CFA 0x00008000 243 #define RCTRL_GHTX 0x00000400 244 #define RCTRL_RTSE 0x00000040 245 #define RCTRL_GRS 0x00000020 246 #define RCTRL_BC_REJ 0x00000010 247 #define RCTRL_MPROM 0x00000008 248 #define RCTRL_RSF 0x00000004 249 #define RCTRL_EMEN 0x00000002 250 #define RCTRL_UPROM 0x00000001 251 #define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM) 252 253 #define TMR_CTL_ESFDP 0x00000800 254 #define TMR_CTL_ESFDE 0x00000400 255 256 #define TSEC_ID1_DEBUG 0x00e00c00 257 #define DEBUG_ENABLE 0x80000000 258 #define DPERROR_Tx_ERROR_ON_SEC 0x00400000 259 #define DPERROR_Tx_ERROR_ON_WRITE 0x10000000 260 #define DPERROR_Rx_ERROR_ON_SEC 0x00000040 261 #define DPERROR_Rx_ERROR_ON_WRITE 0x00001000 262 #define DPERROR_STT 0x80000000 263 #define DPERROR_STR 0x00008000 264 265 #define MACCFG1_SOFT_RESET 0x80000000 266 #define MACCFG1_LOOPBACK 0x00000100 267 #define MACCFG1_RX_FLOW 0x00000020 268 #define MACCFG1_TX_FLOW 0x00000010 269 #define MACCFG1_TX_EN 0x00000001 270 #define MACCFG1_RX_EN 0x00000004 271 #define MACCFG1_RESET_RxMC 0x00080000 272 #define MACCFG1_RESET_TxMC 0x00040000 273 #define MACCFG1_RESET_RxFUN 0x00020000 274 #define MACCFG1_RESET_TxFUN 0x00010000 275 276 #define MACCFG2_NIBBLE_MODE 0x00000100 277 #define MACCFG2_BYTE_MODE 0x00000200 278 #define MACCFG2_PRE_AM_Rx_EN 0x00000080 279 #define MACCFG2_PRE_AM_Tx_EN 0x00000040 280 #define MACCFG2_LENGTH_CHECK 0x00000010 281 #define MACCFG2_MAGIC_PACKET_EN 0x00000008 282 #define MACCFG2_PAD_CRC_EN 0x00000004 283 #define MACCFG2_CRC_EN 0x00000002 284 #define MACCFG2_FULL_DUPLEX 0x00000001 285 286 #define PREAMBLE_LENGTH_SHIFT 12 287 288 #define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24 289 #define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16 290 #define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8 291 292 #define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000 293 #define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000 294 #define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00 295 #define IPGIFG_BACK_TO_BACK_IPG 0x0000007F 296 297 #define HAFDUP_ALT_BEB 0x00080000 298 #define HAFDUP_BP_NO_BACKOFF 0x00040000 299 #define HAFDUP_NO_BACKOFF 0x00020000 300 #define HAFDUP_EXCESS_DEFER 0x00010000 301 #define HAFDUP_COLLISION_WINDOW 0x000003ff 302 303 #define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20 304 #define HAFDUP_RETRANSMISSION_MAX_SHIFT 12 305 #define HAFDUP_RETRANSMISSION_MAX 0x0000f000 306 307 #define NUM_OF_HASH_REGS 8 /* Number of hash table registers */ 308 309 #define DEBUG_GET_FIFO_READ_INDEX 0x007f0000 310 #define DEBUG_GET_FIFO_WRITE_INDEX 0x0000007f 311 /* Pause Time Value Register */ 312 #define PTV_PTE_SHIFT 16 313 314 #define MASK22BIT 0x003FFFFF 315 #define MASK16BIT 0x0000FFFF 316 #define MASK12BIT 0x00000FFF 317 #define MASK8BIT 0x000000FF 318 319 #define VAL32BIT 0x100000000LL 320 #define VAL22BIT 0x00400000 321 #define VAL16BIT 0x00010000 322 #define VAL12BIT 0x00001000 323 324 /* PHY Control Register */ 325 #define PHY_CR_LOOPBACK 0x4000 326 #define PHY_CR_SPEED0 0x2000 327 #define PHY_CR_ANE 0x1000 328 #define PHY_CR_FULLDUPLEX 0x0100 329 #define PHY_CR_SPEED1 0x0040 330 331 #define PHY_TBICON_SRESET 0x8000 332 #define PHY_TBICON_SPEED2 0x0020 333 334 /* CAR1/2 bits */ 335 #define CAR1_TR64 0x80000000 336 #define CAR1_TR127 0x40000000 337 #define CAR1_TR255 0x20000000 338 #define CAR1_TR511 0x10000000 339 #define CAR1_TRK1 0x08000000 340 #define CAR1_TRMAX 0x04000000 341 #define CAR1_TRMGV 0x02000000 342 343 #define CAR1_RBYT 0x00010000 344 #define CAR1_RPKT 0x00008000 345 #define CAR1_RMCA 0x00002000 346 #define CAR1_RBCA 0x00001000 347 #define CAR1_RXPF 0x00000400 348 #define CAR1_RALN 0x00000100 349 #define CAR1_RFLR 0x00000080 350 #define CAR1_RCDE 0x00000040 351 #define CAR1_RCSE 0x00000020 352 #define CAR1_RUND 0x00000010 353 #define CAR1_ROVR 0x00000008 354 #define CAR1_RFRG 0x00000004 355 #define CAR1_RJBR 0x00000002 356 #define CAR1_RDRP 0x00000001 357 358 #define CAR2_TFCS 0x00040000 359 #define CAR2_TBYT 0x00002000 360 #define CAR2_TPKT 0x00001000 361 #define CAR2_TMCA 0x00000800 362 #define CAR2_TBCA 0x00000400 363 #define CAR2_TXPF 0x00000200 364 #define CAR2_TDRP 0x00000001 365 366 #define CAM1_ERRORS_ONLY (CAR1_RXPF | \ 367 CAR1_RALN | \ 368 CAR1_RFLR | \ 369 CAR1_RCDE | \ 370 CAR1_RCSE | \ 371 CAR1_RUND | \ 372 CAR1_ROVR | \ 373 CAR1_RFRG | \ 374 CAR1_RJBR | \ 375 CAR1_RDRP) 376 377 #define CAM2_ERRORS_ONLY (CAR2_TFCS | CAR2_TXPF | CAR2_TDRP) 378 379 typedef struct t_InternalStatistics 380 { 381 uint64_t tr64; 382 uint64_t tr127; 383 uint64_t tr255; 384 uint64_t tr511; 385 uint64_t tr1k; 386 uint64_t trmax; 387 uint64_t trmgv; 388 uint64_t rfrg; 389 uint64_t rjbr; 390 uint64_t rdrp; 391 uint64_t raln; 392 uint64_t rund; 393 uint64_t rovr; 394 uint64_t rxpf; 395 uint64_t txpf; 396 uint64_t rbyt; 397 uint64_t rpkt; 398 uint64_t rmca; 399 uint64_t rbca; 400 uint64_t rflr; 401 uint64_t rcde; 402 uint64_t rcse; 403 uint64_t tbyt; 404 uint64_t tpkt; 405 uint64_t tmca; 406 uint64_t tbca; 407 uint64_t tdrp; 408 uint64_t tfcs; 409 } t_InternalStatistics; 410 411 #if defined(__MWERKS__) && !defined(__GNUC__) 412 #pragma pack(push,1) 413 #endif /* defined(__MWERKS__) && ... */ 414 #define MEM_MAP_START 415 416 typedef _Packed struct 417 { 418 uint32_t exact_match1; /* octets 1-4 */ 419 uint32_t exact_match2; /* octets 5-6 */ 420 } _PackedType macRegs; 421 422 typedef _Packed struct 423 { 424 volatile uint32_t tsec_id1; /* 0x000 ETSEC_ID register */ 425 volatile uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */ 426 volatile uint32_t ievent; /* 0x008 Interrupt event register */ 427 volatile uint32_t imask; /* 0x00C Interrupt mask register */ 428 volatile uint32_t edis; /* 0x010 Error disabled register */ 429 volatile uint32_t ecntrl; /* 0x014 E control register */ 430 volatile uint32_t ptv; /* 0x018 Pause time value register */ 431 volatile uint32_t tbipa; /* 0x01C TBI PHY address register */ 432 volatile uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */ 433 volatile uint32_t tmr_pevent; /* 0x024 Time-stamp event register */ 434 volatile uint32_t tmr_pemask; /* 0x028 Timer event mask register */ 435 volatile uint32_t DTSEC_RESERVED2; /* 0x02C */ 436 volatile uint32_t iobistctl; /* 0x030 IO BIST Control register */ 437 volatile uint32_t DTSEC_RESERVED3[3]; /* 0x034 */ 438 439 volatile uint32_t tctrl; /* 0x040 Transmit control register */ 440 volatile uint32_t DTSEC_RESERVED4[3]; /* 0x044-0x04C */ 441 volatile uint32_t rctrl; /* 0x050 Receive control register */ 442 volatile uint32_t DTSEC_RESERVED5[11]; /* 0x054- 0x07C */ 443 444 volatile uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address registers 0-7 */ 445 volatile uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */ 446 volatile uint32_t ETSEC_RESERVED6[16]; /* 0x0C0-0x0FC */ 447 448 volatile uint32_t maccfg1; /* 0x100 MAC configuration #1 */ 449 volatile uint32_t maccfg2; /* 0x104 MAC configuration #2 */ 450 volatile uint32_t ipgifg; /* 0x108 IPG/IFG */ 451 volatile uint32_t hafdup; /* 0x10C Half-duplex */ 452 volatile uint32_t maxfrm; /* 0x110 Maximum frame */ 453 volatile uint32_t DTSEC_RESERVED7[3]; /* 0x114-0x11C register */ 454 t_MiiAccessMemMap miiMemMap; 455 volatile uint32_t ifctrl; /* 0x138 MII Mgmt:interface control */ 456 volatile uint32_t ifstat; /* 0x13C Interface status */ 457 volatile uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */ 458 volatile uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */ 459 volatile macRegs macaddr[DTSEC_NUM_OF_PADDRS]; /* 0x148-0x1BC mac exact match addresses 1-15, parts 1-2 */ 460 volatile uint32_t DTSEC_RESERVED8[16]; /* 0x1C0-0x1FC register */ 461 462 /* RMON MIB REGISTERS */ 463 /* TRANSMIT and RECEIVE COUNTERS */ 464 465 volatile uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */ 466 volatile uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame counter */ 467 volatile uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame counter */ 468 volatile uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame counter */ 469 volatile uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame counter */ 470 volatile uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame counter */ 471 volatile uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good VLAN frame count */ 472 473 /* RECEIVE COUNTERS */ 474 volatile uint32_t rbyt; /* 0x21C receive byte counter */ 475 volatile uint32_t rpkt; /* 0x220 receive packet counter */ 476 volatile uint32_t rfcs; /* 0x224 receive FCS error counter */ 477 volatile uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */ 478 volatile uint32_t rbca; /* 0x22C receive broadcast packet counter */ 479 volatile uint32_t rxcf; /* 0x230 receive control frame packet counter */ 480 volatile uint32_t rxpf; /* 0x234 receive PAUSE frame packet counter */ 481 volatile uint32_t rxuo; /* 0x238 receive unknown OP code counter */ 482 volatile uint32_t raln; /* 0x23C receive alignment error counter */ 483 volatile uint32_t rflr; /* 0x240 receive frame length error counter */ 484 volatile uint32_t rcde; /* 0x244 receive code error counter */ 485 volatile uint32_t rcse; /* 0x248 receive carrier sense error counter */ 486 volatile uint32_t rund; /* 0x24C receive undersize packet counter */ 487 volatile uint32_t rovr; /* 0x250 receive oversize packet counter */ 488 volatile uint32_t rfrg; /* 0x254 receive fragments counter */ 489 volatile uint32_t rjbr; /* 0x258 receive jabber counter */ 490 volatile uint32_t rdrp; /* 0x25C receive drop */ 491 492 /* TRANSMIT COUNTERS */ 493 volatile uint32_t tbyt; /* 0x260 transmit byte counter */ 494 volatile uint32_t tpkt; /* 0x264 transmit packet counter */ 495 volatile uint32_t tmca; /* 0x268 transmit multicast packet counter */ 496 volatile uint32_t tbca; /* 0x26C transmit broadcast packet counter */ 497 volatile uint32_t txpf; /* 0x270 transmit PAUSE control frame counter */ 498 volatile uint32_t tdfr; /* 0x274 transmit deferral packet counter */ 499 volatile uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */ 500 volatile uint32_t tscl; /* 0x27C transmit single collision packet counter */ 501 volatile uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */ 502 volatile uint32_t tlcl; /* 0x284 transmit late collision packet counter */ 503 volatile uint32_t txcl; /* 0x288 transmit excessive collision packet counter */ 504 volatile uint32_t tncl; /* 0x28C transmit total collision counter */ 505 volatile uint32_t DTSEC_RESERVED9; /* 0x290 */ 506 volatile uint32_t tdrp; /* 0x294 transmit drop frame counter */ 507 volatile uint32_t tjbr; /* 0x298 transmit jabber frame counter */ 508 volatile uint32_t tfcs; /* 0x29C transmit FCS error counter */ 509 volatile uint32_t txcf; /* 0x2A0 transmit control frame counter */ 510 volatile uint32_t tovr; /* 0x2A4 transmit oversize frame counter */ 511 volatile uint32_t tund; /* 0x2A8 transmit undersize frame counter */ 512 volatile uint32_t tfrg; /* 0x2AC transmit fragments frame counter */ 513 514 /* GENERAL REGISTERS */ 515 volatile uint32_t car1; /* 0x2B0 carry register one register* */ 516 volatile uint32_t car2; /* 0x2B4 carry register two register* */ 517 volatile uint32_t cam1; /* 0x2B8 carry register one mask register */ 518 volatile uint32_t cam2; /* 0x2BC carry register two mask register */ 519 volatile uint32_t DTSEC_RESERVED10[16]; /* 0x2C0-0x2FC */ 520 521 /* Debug and Factory Test Registers */ 522 volatile uint32_t debug; /* 0x300 DEBUG - Debug Register */ 523 volatile uint32_t dperror; /* 0x304 DPERROR - Parity Error Register */ 524 volatile uint32_t hwassert; /* 0x308 HWASSERT */ 525 volatile uint32_t RESERVED11; /* 0x30C Reserved */ 526 volatile uint32_t rx_fifo_ptr; /* 0x310 RXFIFOPTR - Rx FIFO R/W Pointer Register */ 527 volatile uint32_t rx_fifo_dath; /* 0x314 RXFIFODATH - Rx FIFO Data Register */ 528 volatile uint32_t rx_fifo_datl; /* 0x318 RXFIFODATL - Rx FIFO Data Register */ 529 volatile uint32_t rx_fifo_stat; /* 0x31C RXFIFOSTAT - Rx FIFO Status Register */ 530 volatile uint32_t tx_fifo_ptr; /* 0x320 TXFIFOPTR - Tx FIFO R/W Pointer Register */ 531 volatile uint32_t tx_fifo_dath; /* 0x324 TXFIFODATH - Rx FIFO Data Register */ 532 volatile uint32_t tx_fifo_datl; /* 0x328 TXFIFODATL - Rx FIFO Data Register */ 533 volatile uint32_t tx_fifo_stat; /* 0x32C TXFIFOSTAT - Tx FIFO Status Register */ 534 volatile uint32_t pkt_rcv_cnt; /* 0x330 PKTRCVCNT - Number of packets accepted and written to Rx FIFO */ 535 volatile uint32_t RESERVED12[3]; /* 0x334-0x33C Reserved */ 536 volatile uint32_t tx_threshold; /* 0x340 Transmit threshold; Number of entries (4 bytes units) before starting to transmit to the MAC */ 537 volatile uint32_t tx_watermark_high;/* 0x344 Transmit watermark high; Number of entries (4 byte units) before de-asserting Ready to packet Interface */ 538 volatile uint32_t rx_watermark_low; /* 0x348 Receive watermark low; Number of entries (4 byte units) before unloading to packet Interface */ 539 } _PackedType t_DtsecMemMap; 540 541 #define MEM_MAP_END 542 #if defined(__MWERKS__) && !defined(__GNUC__) 543 #pragma pack(pop) 544 #endif /* defined(__MWERKS__) && ... */ 545 546 547 typedef struct { 548 uint32_t errorDisabled; 549 bool halfDuplex; 550 uint16_t pauseTime; 551 uint16_t pauseExtended; 552 uint8_t tbiPhyAddr; /**< TBI Physical address (1-31) [DEFAULT_tbiPhyAddr] */ 553 554 bool autoZeroCounters; 555 bool promiscuousEnable; 556 557 bool halfDulexFlowControlEn; 558 bool txTimeStampEn; 559 bool rxTimeStampEn; 560 561 uint8_t packetAlignmentPadding; 562 bool controlFrameAccept; 563 bool groupHashExtend; 564 bool broadcReject; 565 bool rxShortFrame; 566 bool exactMatch; 567 568 bool debugMode; 569 570 bool loopback; 571 bool actOnRxPauseFrame; 572 bool actOnTxPauseFrame; 573 574 uint8_t nonBackToBackIpg1; 575 uint8_t nonBackToBackIpg2; 576 uint8_t minIfgEnforcement; 577 uint8_t backToBackIpg; 578 579 uint8_t preambleLength; 580 bool preambleRxEn; 581 bool preambleTxEn; 582 bool lengthCheckEnable; 583 bool magicPacketEnable; 584 bool padAndCrcEnable; 585 bool crcEnable; 586 587 bool alternateBackoffEnable; 588 uint8_t alternateBackoffVal; 589 bool backPressureNoBackoff; 590 bool noBackoff; 591 bool excessDefer; 592 uint8_t maxRetransmission; 593 uint16_t collisionWindow; 594 595 uint16_t maxFrameLength; 596 597 uint8_t fifoTxThr; 598 uint8_t fifoTxWatermarkH; 599 uint8_t fifoRxWatermarkL; 600 } t_DtsecDriverParam; 601 602 typedef struct { 603 t_FmMacControllerDriver fmMacControllerDriver; 604 t_Handle h_App; /**< Handle to the upper layer application */ 605 t_DtsecMemMap *p_MemMap; /**< pointer to dTSEC memory mapped registers. */ 606 t_MiiAccessMemMap *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */ 607 uint64_t addr; /**< MAC address of device; */ 608 e_EnetMode enetMode; /**< Ethernet physical interface */ 609 t_FmMacExceptionCallback *f_Exception; 610 int mdioIrq; 611 t_FmMacExceptionCallback *f_Event; 612 bool indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */ 613 uint64_t paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */ 614 uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */ 615 bool debugMode; 616 bool halfDuplex; 617 t_InternalStatistics internalStatistics; 618 t_EthHash *p_MulticastAddrHash; /* pointer to driver's global address hash table */ 619 t_EthHash *p_UnicastAddrHash; /* pointer to driver's individual address hash table */ 620 uint8_t macId; 621 uint32_t exceptions; 622 bool ptpTsuEnabled; 623 bool enTsuErrExeption; 624 e_FmMacStatisticsLevel statisticsLevel; 625 626 t_DtsecDriverParam *p_DtsecDriverParam; 627 } t_Dtsec; 628 629 630 t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data); 631 t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data); 632 633 634 #endif /* __DTSEC_H */ 635