1 /****************************************************************************** 2 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4 All rights reserved. 5 6 This is proprietary source code of Freescale Semiconductor Inc., 7 and its use is subject to the NetComm Device Drivers EULA. 8 The copyright notice above does not evidence any actual or intended 9 publication of such source code. 10 11 ALTERNATIVELY, redistribution and use in source and binary forms, with 12 or without modification, are permitted provided that the following 13 conditions are met: 14 * Redistributions of source code must retain the above copyright 15 notice, this list of conditions and the following disclaimer. 16 * Redistributions in binary form must reproduce the above copyright 17 notice, this list of conditions and the following disclaimer in the 18 documentation and/or other materials provided with the distribution. 19 * Neither the name of Freescale Semiconductor nor the 20 names of its contributors may be used to endorse or promote products 21 derived from this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 35 **************************************************************************/ 36 /****************************************************************************** 37 @File bman_private.h 38 39 @Description BM header 40 *//***************************************************************************/ 41 #ifndef __BMAN_PRIV_H 42 #define __BMAN_PRIV_H 43 44 #include "fsl_bman.h" 45 46 #define __ERR_MODULE__ MODULE_BM 47 48 #if defined(DEBUG) || !defined(DISABLE_ASSERTIONS) 49 /* Optionally compile-in assertion-checking */ 50 #define BM_CHECKING 51 #endif /* defined(DEBUG) || ... */ 52 53 /* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers 54 * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or 55 * execution reordering with respect to other code/instructions that manipulate 56 * the same cacheline. */ 57 #ifdef CORE_E500MC 58 59 #if defined(_DIAB_TOOL) 60 #define hwsync() \ 61 do { \ 62 __asm__ __volatile__ ("sync"); \ 63 } while(0) 64 65 #define lwsync() \ 66 do { \ 67 __asm__ __volatile__ ("lwsync"); \ 68 } while(0) 69 70 __asm__ __volatile__ void dcbf (volatile void * addr) 71 { 72 %reg addr 73 dcbf r0, addr 74 } 75 76 __asm__ __volatile__ void dcbt_ro (volatile void * addr) 77 { 78 %reg addr 79 dcbt r0, addr 80 } 81 82 __asm__ __volatile__ void dcbt_rw (volatile void * addr) 83 { 84 %reg addr 85 dcbtst r0, addr 86 } 87 88 __asm__ __volatile__ void dcbzl (volatile void * addr) 89 { 90 %reg addr 91 dcbzl r0, addr 92 } 93 94 #define dcbz_64(p) \ 95 do { \ 96 dcbzl(p); \ 97 } while (0) 98 99 #define dcbf_64(p) \ 100 do { \ 101 dcbf(p); \ 102 } while (0) 103 104 /* Commonly used combo */ 105 #define dcbit_ro(p) \ 106 do { \ 107 dcbi(p); \ 108 dcbt_ro(p); \ 109 } while (0) 110 111 #else /* GNU C */ 112 #define hwsync() \ 113 do { \ 114 __asm__ __volatile__ ("sync" : : : "memory"); \ 115 } while(0) 116 117 #define lwsync() \ 118 do { \ 119 __asm__ __volatile__ ("lwsync" : : : "memory"); \ 120 } while(0) 121 122 #define dcbf(addr) \ 123 do { \ 124 __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \ 125 } while(0) 126 127 #define dcbt_ro(addr) \ 128 do { \ 129 __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \ 130 } while(0) 131 132 #define dcbt_rw(addr) \ 133 do { \ 134 __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \ 135 } while(0) 136 137 #define dcbzl(p) \ 138 do { \ 139 __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \ 140 } while(0) 141 142 #define dcbz_64(p) \ 143 do { \ 144 dcbzl(p); \ 145 } while (0) 146 147 #define dcbf_64(p) \ 148 do { \ 149 dcbf(p); \ 150 } while (0) 151 152 /* Commonly used combo */ 153 #define dcbit_ro(p) \ 154 do { \ 155 dcbi(p); \ 156 dcbt_ro(p); \ 157 } while (0) 158 159 #endif /* _DIAB_TOOL */ 160 161 #else 162 #define hwsync CORE_MemoryBarrier 163 #define lwsync hwsync 164 165 #define dcbf(p) \ 166 do { \ 167 __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \ 168 } while(0) 169 #define dcbt_ro(p) \ 170 do { \ 171 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \ 172 lwsync(); \ 173 } while(0) 174 #define dcbt_rw(p) \ 175 do { \ 176 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \ 177 } while(0) 178 #define dcbz(p) \ 179 do { \ 180 __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \ 181 } while (0) 182 #define dcbz_64(p) \ 183 do { \ 184 dcbz((uint32_t)p + 32); \ 185 dcbz(p); \ 186 } while (0) 187 #define dcbf_64(p) \ 188 do { \ 189 dcbf((uint32_t)p + 32); \ 190 dcbf(p); \ 191 } while (0) 192 /* Commonly used combo */ 193 #define dcbit_ro(p) \ 194 do { \ 195 dcbi(p); \ 196 dcbi((uint32_t)p + 32); \ 197 dcbt_ro(p); \ 198 dcbt_ro((uint32_t)p + 32); \ 199 } while (0) 200 201 #endif /* CORE_E500MC */ 202 203 #define dcbi(p) dcbf(p) 204 205 struct bm_addr { 206 void *addr_ce; /* cache-enabled */ 207 void *addr_ci; /* cache-inhibited */ 208 }; 209 210 /* RCR state */ 211 struct bm_rcr { 212 struct bm_rcr_entry *ring, *cursor; 213 uint8_t ci, available, ithresh, vbit; 214 #ifdef BM_CHECKING 215 uint32_t busy; 216 e_BmPortalProduceMode pmode; 217 e_BmPortalRcrConsumeMode cmode; 218 #endif /* BM_CHECKING */ 219 }; 220 221 /* MC state */ 222 struct bm_mc { 223 struct bm_mc_command *cr; 224 struct bm_mc_result *rr; 225 uint8_t rridx, vbit; 226 #ifdef BM_CHECKING 227 enum { 228 /* Can only be _mc_start()ed */ 229 mc_idle, 230 /* Can only be _mc_commit()ed or _mc_abort()ed */ 231 mc_user, 232 /* Can only be _mc_retry()ed */ 233 mc_hw 234 } state; 235 #endif /* BM_CHECKING */ 236 }; 237 238 /********************/ 239 /* Portal structure */ 240 /********************/ 241 242 struct bm_portal { 243 struct bm_addr addr; 244 struct bm_rcr rcr; 245 struct bm_mc mc; 246 }; 247 248 249 #endif /* __BMAN_PRIV_H */ 250