1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2021 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef ENA_PLAT_H_ 35 #define ENA_PLAT_H_ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 43 #include <sys/bus.h> 44 #include <sys/condvar.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/kthread.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/proc.h> 53 #include <sys/smp.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/sysctl.h> 57 #include <sys/taskqueue.h> 58 #include <sys/eventhandler.h> 59 #include <sys/types.h> 60 #include <sys/timetc.h> 61 #include <sys/cdefs.h> 62 63 #include <machine/atomic.h> 64 #include <machine/bus.h> 65 #include <machine/in_cksum.h> 66 #include <machine/pcpu.h> 67 #include <machine/resource.h> 68 #include <machine/_inttypes.h> 69 70 #include <net/bpf.h> 71 #include <net/ethernet.h> 72 #include <net/if.h> 73 #include <net/if_var.h> 74 #include <net/if_arp.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/if_types.h> 79 #include <net/if_vlan_var.h> 80 81 #include <netinet/in_systm.h> 82 #include <netinet/in.h> 83 #include <netinet/if_ether.h> 84 #include <netinet/ip.h> 85 #include <netinet/ip6.h> 86 #include <netinet/tcp.h> 87 #include <netinet/tcp_lro.h> 88 #include <netinet/udp.h> 89 90 #include <dev/led/led.h> 91 #include <dev/pci/pcivar.h> 92 #include <dev/pci/pcireg.h> 93 94 #include "ena_fbsd_log.h" 95 96 extern struct ena_bus_space ebs; 97 98 #define DEFAULT_ALLOC_ALIGNMENT 8 99 #define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */ 100 101 extern int ena_log_level; 102 103 #define container_of(ptr, type, member) \ 104 ({ \ 105 const __typeof(((type *)0)->member) *__p = (ptr); \ 106 (type *)((uintptr_t)__p - offsetof(type, member)); \ 107 }) 108 109 #define ena_trace(ctx, level, fmt, args...) \ 110 ena_log((ctx)->dmadev, level, "%s() [TID:%d]: " \ 111 fmt, __func__, curthread->td_tid, ##args) 112 113 #define ena_trc_dbg(ctx, format, arg...) \ 114 ena_trace(ctx, DBG, format, ##arg) 115 #define ena_trc_info(ctx, format, arg...) \ 116 ena_trace(ctx, INFO, format, ##arg) 117 #define ena_trc_warn(ctx, format, arg...) \ 118 ena_trace(ctx, WARN, format, ##arg) 119 #define ena_trc_err(ctx, format, arg...) \ 120 ena_trace(ctx, ERR, format, ##arg) 121 122 #define unlikely(x) __predict_false(!!(x)) 123 #define likely(x) __predict_true(!!(x)) 124 125 #define __iomem 126 #define ____cacheline_aligned __aligned(CACHE_LINE_SIZE) 127 128 #define MAX_ERRNO 4095 129 #define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO) 130 131 #define ENA_WARN(cond, ctx, format, arg...) \ 132 do { \ 133 if (unlikely((cond))) { \ 134 ena_trc_warn(ctx, format, ##arg); \ 135 } \ 136 } while (0) 137 138 static inline long IS_ERR(const void *ptr) 139 { 140 return IS_ERR_VALUE((unsigned long)ptr); 141 } 142 143 static inline void *ERR_PTR(long error) 144 { 145 return (void *)error; 146 } 147 148 static inline long PTR_ERR(const void *ptr) 149 { 150 return (long) ptr; 151 } 152 153 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) 154 #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) 155 #define BIT(x) (1UL << (x)) 156 157 #define ENA_ABORT() BUG() 158 #define BUG() panic("ENA BUG") 159 160 #define SZ_256 (256) 161 #define SZ_4K (4096) 162 163 #define ENA_COM_OK 0 164 #define ENA_COM_FAULT EFAULT 165 #define ENA_COM_INVAL EINVAL 166 #define ENA_COM_NO_MEM ENOMEM 167 #define ENA_COM_NO_SPACE ENOSPC 168 #define ENA_COM_TRY_AGAIN -1 169 #define ENA_COM_UNSUPPORTED EOPNOTSUPP 170 #define ENA_COM_NO_DEVICE ENODEV 171 #define ENA_COM_PERMISSION EPERM 172 #define ENA_COM_TIMER_EXPIRED ETIMEDOUT 173 #define ENA_COM_EIO EIO 174 175 #define ENA_MSLEEP(x) pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0) 176 #define ENA_USLEEP(x) pause_sbt("ena", SBT_1US * (x), SBT_1US, 0) 177 #define ENA_UDELAY(x) DELAY(x) 178 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 179 ((long)cputick2usec(cpu_ticks()) + (timeout_us)) 180 #define ENA_TIME_EXPIRE(timeout) ((timeout) < cputick2usec(cpu_ticks())) 181 #define ENA_MIGHT_SLEEP() 182 183 #define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y)) 184 #define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y)) 185 186 #define ENA_MIN32(x,y) MIN(x, y) 187 #define ENA_MIN16(x,y) MIN(x, y) 188 #define ENA_MIN8(x,y) MIN(x, y) 189 190 #define ENA_MAX32(x,y) MAX(x, y) 191 #define ENA_MAX16(x,y) MAX(x, y) 192 #define ENA_MAX8(x,y) MAX(x, y) 193 194 /* Spinlock related methods */ 195 #define ena_spinlock_t struct mtx 196 #define ENA_SPINLOCK_INIT(spinlock) \ 197 mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN) 198 #define ENA_SPINLOCK_DESTROY(spinlock) \ 199 do { \ 200 if (mtx_initialized(&(spinlock))) \ 201 mtx_destroy(&(spinlock)); \ 202 } while (0) 203 #define ENA_SPINLOCK_LOCK(spinlock, flags) \ 204 do { \ 205 (void)(flags); \ 206 mtx_lock_spin(&(spinlock)); \ 207 } while (0) 208 #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ 209 do { \ 210 (void)(flags); \ 211 mtx_unlock_spin(&(spinlock)); \ 212 } while (0) 213 214 215 /* Wait queue related methods */ 216 #define ena_wait_event_t struct { struct cv wq; struct mtx mtx; } 217 #define ENA_WAIT_EVENT_INIT(waitqueue) \ 218 do { \ 219 cv_init(&((waitqueue).wq), "cv"); \ 220 mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF); \ 221 } while (0) 222 #define ENA_WAIT_EVENTS_DESTROY(admin_queue) \ 223 do { \ 224 struct ena_comp_ctx *comp_ctx; \ 225 int i; \ 226 for (i = 0; i < admin_queue->q_depth; i++) { \ 227 comp_ctx = get_comp_ctxt(admin_queue, i, false); \ 228 if (comp_ctx != NULL) { \ 229 cv_destroy(&((comp_ctx->wait_event).wq)); \ 230 mtx_destroy(&((comp_ctx->wait_event).mtx)); \ 231 } \ 232 } \ 233 } while (0) 234 #define ENA_WAIT_EVENT_CLEAR(waitqueue) \ 235 cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description) 236 #define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us) \ 237 do { \ 238 mtx_lock(&((waitqueue).mtx)); \ 239 cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx), \ 240 timeout_us * hz / 1000 / 1000 ); \ 241 mtx_unlock(&((waitqueue).mtx)); \ 242 } while (0) 243 #define ENA_WAIT_EVENT_SIGNAL(waitqueue) \ 244 do { \ 245 mtx_lock(&((waitqueue).mtx)); \ 246 cv_broadcast(&((waitqueue).wq)); \ 247 mtx_unlock(&((waitqueue).mtx)); \ 248 } while (0) 249 250 #define dma_addr_t bus_addr_t 251 #define u8 uint8_t 252 #define u16 uint16_t 253 #define u32 uint32_t 254 #define u64 uint64_t 255 256 typedef struct { 257 bus_addr_t paddr; 258 caddr_t vaddr; 259 bus_dma_tag_t tag; 260 bus_dmamap_t map; 261 bus_dma_segment_t seg; 262 int nseg; 263 } ena_mem_handle_t; 264 265 struct ena_bus { 266 bus_space_handle_t reg_bar_h; 267 bus_space_tag_t reg_bar_t; 268 bus_space_handle_t mem_bar_h; 269 bus_space_tag_t mem_bar_t; 270 }; 271 272 typedef uint32_t ena_atomic32_t; 273 274 #define ENA_PRIu64 PRIu64 275 276 typedef uint64_t ena_time_t; 277 typedef struct ifnet ena_netdev; 278 279 void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, 280 int error); 281 int ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma, 282 int mapflags, bus_size_t alignment); 283 284 static inline uint32_t 285 ena_reg_read32(struct ena_bus *bus, bus_size_t offset) 286 { 287 uint32_t v = bus_space_read_4(bus->reg_bar_t, bus->reg_bar_h, offset); 288 rmb(); 289 return v; 290 } 291 292 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ 293 do { \ 294 int count, i; \ 295 volatile uint64_t *to = (volatile uint64_t *)(dst); \ 296 const uint64_t *from = (const uint64_t *)(src); \ 297 count = (size) / 8; \ 298 \ 299 for (i = 0; i < count; i++, from++, to++) \ 300 *to = *from; \ 301 } while (0) 302 303 #define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO) 304 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL) 305 #define ENA_MEM_FREE(dmadev, ptr, size) \ 306 do { \ 307 (void)(size); \ 308 free(ptr, M_DEVBUF); \ 309 } while (0) 310 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys, \ 311 handle, node, dev_node, alignment) \ 312 do { \ 313 ((virt) = NULL); \ 314 (void)(dev_node); \ 315 } while (0) 316 317 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, \ 318 node, dev_node) \ 319 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, \ 320 phys, handle, node, dev_node, DEFAULT_ALLOC_ALIGNMENT) 321 322 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, dma, \ 323 alignment) \ 324 do { \ 325 ena_dma_alloc((dmadev), (size), &(dma), 0, alignment); \ 326 (virt) = (void *)(dma).vaddr; \ 327 (phys) = (dma).paddr; \ 328 } while (0) 329 330 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \ 331 ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, \ 332 phys, dma, DEFAULT_ALLOC_ALIGNMENT) 333 334 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \ 335 do { \ 336 (void)size; \ 337 bus_dmamap_unload((dma).tag, (dma).map); \ 338 bus_dmamem_free((dma).tag, (virt), (dma).map); \ 339 bus_dma_tag_destroy((dma).tag); \ 340 (dma).tag = NULL; \ 341 (virt) = NULL; \ 342 } while (0) 343 344 /* Register R/W methods */ 345 #define ENA_REG_WRITE32(bus, value, offset) \ 346 do { \ 347 wmb(); \ 348 ENA_REG_WRITE32_RELAXED(bus, value, offset); \ 349 } while (0) 350 351 #define ENA_REG_WRITE32_RELAXED(bus, value, offset) \ 352 bus_space_write_4( \ 353 ((struct ena_bus*)bus)->reg_bar_t, \ 354 ((struct ena_bus*)bus)->reg_bar_h, \ 355 (bus_size_t)(offset), (value)) 356 357 #define ENA_REG_READ32(bus, offset) \ 358 ena_reg_read32((struct ena_bus*)(bus), (bus_size_t)(offset)) 359 360 #define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync( \ 361 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE) 362 #define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync( \ 363 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD) 364 #define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync( \ 365 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD) 366 #define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle) 367 368 #define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0) 369 370 #define VLAN_HLEN sizeof(struct ether_vlan_header) 371 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 372 373 #define prefetch(x) (void)(x) 374 #define prefetchw(x) (void)(x) 375 376 /* DMA buffers access */ 377 #define dma_unmap_addr(p, name) ((p)->dma->name) 378 #define dma_unmap_addr_set(p, name, v) (((p)->dma->name) = (v)) 379 #define dma_unmap_len(p, name) ((p)->name) 380 #define dma_unmap_len_set(p, name, v) (((p)->name) = (v)) 381 382 #define memcpy_toio memcpy 383 384 #define ATOMIC32_INC(I32_PTR) atomic_add_int(I32_PTR, 1) 385 #define ATOMIC32_DEC(I32_PTR) atomic_add_int(I32_PTR, -1) 386 #define ATOMIC32_READ(I32_PTR) atomic_load_acq_int(I32_PTR) 387 #define ATOMIC32_SET(I32_PTR, VAL) atomic_store_rel_int(I32_PTR, VAL) 388 389 #define barrier() __asm__ __volatile__("": : :"memory") 390 #define dma_rmb() barrier() 391 #define mmiowb() barrier() 392 393 #define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x)) 394 #define READ_ONCE(x) ({ \ 395 __typeof(x) __var; \ 396 barrier(); \ 397 __var = ACCESS_ONCE(x); \ 398 barrier(); \ 399 __var; \ 400 }) 401 #define READ_ONCE8(x) READ_ONCE(x) 402 #define READ_ONCE16(x) READ_ONCE(x) 403 #define READ_ONCE32(x) READ_ONCE(x) 404 405 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 406 #define lower_32_bits(n) ((uint32_t)(n)) 407 408 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 409 410 #define ENA_FFS(x) ffs(x) 411 412 void ena_rss_key_fill(void *key, size_t size); 413 414 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) 415 416 #include "ena_defs/ena_includes.h" 417 418 #endif /* ENA_PLAT_H_ */ 419