1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2021 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef ENA_PLAT_H_ 35 #define ENA_PLAT_H_ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 43 #include <sys/bus.h> 44 #include <sys/condvar.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/kthread.h> 48 #include <sys/malloc.h> 49 #include <sys/mbuf.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/proc.h> 53 #include <sys/smp.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/sysctl.h> 57 #include <sys/taskqueue.h> 58 #include <sys/eventhandler.h> 59 #include <sys/types.h> 60 #include <sys/timetc.h> 61 #include <sys/cdefs.h> 62 63 #include <machine/atomic.h> 64 #include <machine/bus.h> 65 #include <machine/in_cksum.h> 66 #include <machine/pcpu.h> 67 #include <machine/resource.h> 68 #include <machine/_inttypes.h> 69 70 #include <net/bpf.h> 71 #include <net/ethernet.h> 72 #include <net/if.h> 73 #include <net/if_var.h> 74 #include <net/if_arp.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/if_types.h> 79 #include <net/if_vlan_var.h> 80 81 #include <netinet/in_systm.h> 82 #include <netinet/in.h> 83 #include <netinet/if_ether.h> 84 #include <netinet/ip.h> 85 #include <netinet/ip6.h> 86 #include <netinet/tcp.h> 87 #include <netinet/tcp_lro.h> 88 #include <netinet/udp.h> 89 90 #include <dev/led/led.h> 91 #include <dev/pci/pcivar.h> 92 #include <dev/pci/pcireg.h> 93 94 #include "ena_fbsd_log.h" 95 96 extern struct ena_bus_space ebs; 97 98 #define DEFAULT_ALLOC_ALIGNMENT 8 99 #define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */ 100 101 #define container_of(ptr, type, member) \ 102 ({ \ 103 const __typeof(((type *)0)->member) *__p = (ptr); \ 104 (type *)((uintptr_t)__p - offsetof(type, member)); \ 105 }) 106 107 #define ena_trace(ctx, level, fmt, args...) \ 108 ena_log((ctx)->dmadev, level, "%s() [TID:%d]: " \ 109 fmt, __func__, curthread->td_tid, ##args) 110 111 #define ena_trc_dbg(ctx, format, arg...) \ 112 ena_trace(ctx, DBG, format, ##arg) 113 #define ena_trc_info(ctx, format, arg...) \ 114 ena_trace(ctx, INFO, format, ##arg) 115 #define ena_trc_warn(ctx, format, arg...) \ 116 ena_trace(ctx, WARN, format, ##arg) 117 #define ena_trc_err(ctx, format, arg...) \ 118 ena_trace(ctx, ERR, format, ##arg) 119 120 #define unlikely(x) __predict_false(!!(x)) 121 #define likely(x) __predict_true(!!(x)) 122 123 #define __iomem 124 #define ____cacheline_aligned __aligned(CACHE_LINE_SIZE) 125 126 #define MAX_ERRNO 4095 127 #define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO) 128 129 #define ENA_WARN(cond, ctx, format, arg...) \ 130 do { \ 131 if (unlikely((cond))) { \ 132 ena_trc_warn(ctx, format, ##arg); \ 133 } \ 134 } while (0) 135 136 static inline long IS_ERR(const void *ptr) 137 { 138 return IS_ERR_VALUE((unsigned long)ptr); 139 } 140 141 static inline void *ERR_PTR(long error) 142 { 143 return (void *)error; 144 } 145 146 static inline long PTR_ERR(const void *ptr) 147 { 148 return (long) ptr; 149 } 150 151 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) 152 #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) 153 #define BIT(x) (1UL << (x)) 154 155 #define ENA_ABORT() BUG() 156 #define BUG() panic("ENA BUG") 157 158 #define SZ_256 (256) 159 #define SZ_4K (4096) 160 161 #define ENA_COM_OK 0 162 #define ENA_COM_FAULT EFAULT 163 #define ENA_COM_INVAL EINVAL 164 #define ENA_COM_NO_MEM ENOMEM 165 #define ENA_COM_NO_SPACE ENOSPC 166 #define ENA_COM_TRY_AGAIN -1 167 #define ENA_COM_UNSUPPORTED EOPNOTSUPP 168 #define ENA_COM_NO_DEVICE ENODEV 169 #define ENA_COM_PERMISSION EPERM 170 #define ENA_COM_TIMER_EXPIRED ETIMEDOUT 171 #define ENA_COM_EIO EIO 172 173 #define ENA_MSLEEP(x) pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0) 174 #define ENA_USLEEP(x) pause_sbt("ena", SBT_1US * (x), SBT_1US, 0) 175 #define ENA_UDELAY(x) DELAY(x) 176 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 177 ((long)cputick2usec(cpu_ticks()) + (timeout_us)) 178 #define ENA_TIME_EXPIRE(timeout) ((timeout) < cputick2usec(cpu_ticks())) 179 #define ENA_MIGHT_SLEEP() 180 181 #define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y)) 182 #define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y)) 183 184 #define ENA_MIN32(x,y) MIN(x, y) 185 #define ENA_MIN16(x,y) MIN(x, y) 186 #define ENA_MIN8(x,y) MIN(x, y) 187 188 #define ENA_MAX32(x,y) MAX(x, y) 189 #define ENA_MAX16(x,y) MAX(x, y) 190 #define ENA_MAX8(x,y) MAX(x, y) 191 192 /* Spinlock related methods */ 193 #define ena_spinlock_t struct mtx 194 #define ENA_SPINLOCK_INIT(spinlock) \ 195 mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN) 196 #define ENA_SPINLOCK_DESTROY(spinlock) \ 197 do { \ 198 if (mtx_initialized(&(spinlock))) \ 199 mtx_destroy(&(spinlock)); \ 200 } while (0) 201 #define ENA_SPINLOCK_LOCK(spinlock, flags) \ 202 do { \ 203 (void)(flags); \ 204 mtx_lock_spin(&(spinlock)); \ 205 } while (0) 206 #define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ 207 do { \ 208 (void)(flags); \ 209 mtx_unlock_spin(&(spinlock)); \ 210 } while (0) 211 212 213 /* Wait queue related methods */ 214 #define ena_wait_event_t struct { struct cv wq; struct mtx mtx; } 215 #define ENA_WAIT_EVENT_INIT(waitqueue) \ 216 do { \ 217 cv_init(&((waitqueue).wq), "cv"); \ 218 mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF); \ 219 } while (0) 220 #define ENA_WAIT_EVENTS_DESTROY(admin_queue) \ 221 do { \ 222 struct ena_comp_ctx *comp_ctx; \ 223 int i; \ 224 for (i = 0; i < admin_queue->q_depth; i++) { \ 225 comp_ctx = get_comp_ctxt(admin_queue, i, false); \ 226 if (comp_ctx != NULL) { \ 227 cv_destroy(&((comp_ctx->wait_event).wq)); \ 228 mtx_destroy(&((comp_ctx->wait_event).mtx)); \ 229 } \ 230 } \ 231 } while (0) 232 #define ENA_WAIT_EVENT_CLEAR(waitqueue) \ 233 cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description) 234 #define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us) \ 235 do { \ 236 mtx_lock(&((waitqueue).mtx)); \ 237 cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx), \ 238 timeout_us * hz / 1000 / 1000 ); \ 239 mtx_unlock(&((waitqueue).mtx)); \ 240 } while (0) 241 #define ENA_WAIT_EVENT_SIGNAL(waitqueue) \ 242 do { \ 243 mtx_lock(&((waitqueue).mtx)); \ 244 cv_broadcast(&((waitqueue).wq)); \ 245 mtx_unlock(&((waitqueue).mtx)); \ 246 } while (0) 247 248 #define dma_addr_t bus_addr_t 249 #define u8 uint8_t 250 #define u16 uint16_t 251 #define u32 uint32_t 252 #define u64 uint64_t 253 254 typedef struct { 255 bus_addr_t paddr; 256 caddr_t vaddr; 257 bus_dma_tag_t tag; 258 bus_dmamap_t map; 259 bus_dma_segment_t seg; 260 int nseg; 261 } ena_mem_handle_t; 262 263 struct ena_bus { 264 bus_space_handle_t reg_bar_h; 265 bus_space_tag_t reg_bar_t; 266 bus_space_handle_t mem_bar_h; 267 bus_space_tag_t mem_bar_t; 268 }; 269 270 typedef uint32_t ena_atomic32_t; 271 272 #define ENA_PRIu64 PRIu64 273 274 typedef uint64_t ena_time_t; 275 typedef struct ifnet ena_netdev; 276 277 void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, 278 int error); 279 int ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma, 280 int mapflags, bus_size_t alignment); 281 282 static inline uint32_t 283 ena_reg_read32(struct ena_bus *bus, bus_size_t offset) 284 { 285 uint32_t v = bus_space_read_4(bus->reg_bar_t, bus->reg_bar_h, offset); 286 rmb(); 287 return v; 288 } 289 290 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ 291 do { \ 292 int count, i; \ 293 volatile uint64_t *to = (volatile uint64_t *)(dst); \ 294 const uint64_t *from = (const uint64_t *)(src); \ 295 count = (size) / 8; \ 296 \ 297 for (i = 0; i < count; i++, from++, to++) \ 298 *to = *from; \ 299 } while (0) 300 301 #define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO) 302 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL) 303 #define ENA_MEM_FREE(dmadev, ptr, size) \ 304 do { \ 305 (void)(size); \ 306 free(ptr, M_DEVBUF); \ 307 } while (0) 308 #define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, phys, \ 309 handle, node, dev_node, alignment) \ 310 do { \ 311 ((virt) = NULL); \ 312 (void)(dev_node); \ 313 } while (0) 314 315 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, \ 316 node, dev_node) \ 317 ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(dmadev, size, virt, \ 318 phys, handle, node, dev_node, DEFAULT_ALLOC_ALIGNMENT) 319 320 #define ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, phys, dma, \ 321 alignment) \ 322 do { \ 323 ena_dma_alloc((dmadev), (size), &(dma), 0, alignment); \ 324 (virt) = (void *)(dma).vaddr; \ 325 (phys) = (dma).paddr; \ 326 } while (0) 327 328 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \ 329 ENA_MEM_ALLOC_COHERENT_ALIGNED(dmadev, size, virt, \ 330 phys, dma, DEFAULT_ALLOC_ALIGNMENT) 331 332 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \ 333 do { \ 334 (void)size; \ 335 bus_dmamap_unload((dma).tag, (dma).map); \ 336 bus_dmamem_free((dma).tag, (virt), (dma).map); \ 337 bus_dma_tag_destroy((dma).tag); \ 338 (dma).tag = NULL; \ 339 (virt) = NULL; \ 340 } while (0) 341 342 /* Register R/W methods */ 343 #define ENA_REG_WRITE32(bus, value, offset) \ 344 do { \ 345 wmb(); \ 346 ENA_REG_WRITE32_RELAXED(bus, value, offset); \ 347 } while (0) 348 349 #define ENA_REG_WRITE32_RELAXED(bus, value, offset) \ 350 bus_space_write_4( \ 351 ((struct ena_bus*)bus)->reg_bar_t, \ 352 ((struct ena_bus*)bus)->reg_bar_h, \ 353 (bus_size_t)(offset), (value)) 354 355 #define ENA_REG_READ32(bus, offset) \ 356 ena_reg_read32((struct ena_bus*)(bus), (bus_size_t)(offset)) 357 358 #define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync( \ 359 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE) 360 #define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync( \ 361 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD) 362 #define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync( \ 363 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD) 364 #define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle) 365 366 #define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0) 367 368 #define VLAN_HLEN sizeof(struct ether_vlan_header) 369 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 370 371 #define prefetch(x) (void)(x) 372 #define prefetchw(x) (void)(x) 373 374 /* DMA buffers access */ 375 #define dma_unmap_addr(p, name) ((p)->dma->name) 376 #define dma_unmap_addr_set(p, name, v) (((p)->dma->name) = (v)) 377 #define dma_unmap_len(p, name) ((p)->name) 378 #define dma_unmap_len_set(p, name, v) (((p)->name) = (v)) 379 380 #define memcpy_toio memcpy 381 382 #define ATOMIC32_INC(I32_PTR) atomic_add_int(I32_PTR, 1) 383 #define ATOMIC32_DEC(I32_PTR) atomic_add_int(I32_PTR, -1) 384 #define ATOMIC32_READ(I32_PTR) atomic_load_acq_int(I32_PTR) 385 #define ATOMIC32_SET(I32_PTR, VAL) atomic_store_rel_int(I32_PTR, VAL) 386 387 #define barrier() __asm__ __volatile__("": : :"memory") 388 #define dma_rmb() barrier() 389 #define mmiowb() barrier() 390 391 #define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x)) 392 #define READ_ONCE(x) ({ \ 393 __typeof(x) __var; \ 394 barrier(); \ 395 __var = ACCESS_ONCE(x); \ 396 barrier(); \ 397 __var; \ 398 }) 399 #define READ_ONCE8(x) READ_ONCE(x) 400 #define READ_ONCE16(x) READ_ONCE(x) 401 #define READ_ONCE32(x) READ_ONCE(x) 402 403 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 404 #define lower_32_bits(n) ((uint32_t)(n)) 405 406 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 407 408 #define ENA_FFS(x) ffs(x) 409 410 void ena_rss_key_fill(void *key, size_t size); 411 412 #define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) 413 414 #include "ena_defs/ena_includes.h" 415 416 #endif /* ENA_PLAT_H_ */ 417