xref: /freebsd/sys/contrib/ena-com/ena_defs/ena_regs_defs.h (revision d3d381b2b194b4d24853e92eecef55f262688d1a)
1 /*-
2  * BSD LICENSE
3  *
4  * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * * Redistributions of source code must retain the above copyright
12  * notice, this list of conditions and the following disclaimer.
13  * * Redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in
15  * the documentation and/or other materials provided with the
16  * distribution.
17  * * Neither the name of copyright holder nor the names of its
18  * contributors may be used to endorse or promote products derived
19  * from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 #ifndef _ENA_REGS_H_
34 #define _ENA_REGS_H_
35 
36 enum ena_regs_reset_reason_types {
37 	ENA_REGS_RESET_NORMAL			= 0,
38 
39 	ENA_REGS_RESET_KEEP_ALIVE_TO		= 1,
40 
41 	ENA_REGS_RESET_ADMIN_TO			= 2,
42 
43 	ENA_REGS_RESET_MISS_TX_CMPL		= 3,
44 
45 	ENA_REGS_RESET_INV_RX_REQ_ID		= 4,
46 
47 	ENA_REGS_RESET_INV_TX_REQ_ID		= 5,
48 
49 	ENA_REGS_RESET_TOO_MANY_RX_DESCS	= 6,
50 
51 	ENA_REGS_RESET_INIT_ERR			= 7,
52 
53 	ENA_REGS_RESET_DRIVER_INVALID_STATE	= 8,
54 
55 	ENA_REGS_RESET_OS_TRIGGER		= 9,
56 
57 	ENA_REGS_RESET_OS_NETDEV_WD		= 10,
58 
59 	ENA_REGS_RESET_SHUTDOWN			= 11,
60 
61 	ENA_REGS_RESET_USER_TRIGGER		= 12,
62 
63 	ENA_REGS_RESET_GENERIC			= 13,
64 };
65 
66 /* ena_registers offsets */
67 #define ENA_REGS_VERSION_OFF		0x0
68 #define ENA_REGS_CONTROLLER_VERSION_OFF		0x4
69 #define ENA_REGS_CAPS_OFF		0x8
70 #define ENA_REGS_CAPS_EXT_OFF		0xc
71 #define ENA_REGS_AQ_BASE_LO_OFF		0x10
72 #define ENA_REGS_AQ_BASE_HI_OFF		0x14
73 #define ENA_REGS_AQ_CAPS_OFF		0x18
74 #define ENA_REGS_ACQ_BASE_LO_OFF		0x20
75 #define ENA_REGS_ACQ_BASE_HI_OFF		0x24
76 #define ENA_REGS_ACQ_CAPS_OFF		0x28
77 #define ENA_REGS_AQ_DB_OFF		0x2c
78 #define ENA_REGS_ACQ_TAIL_OFF		0x30
79 #define ENA_REGS_AENQ_CAPS_OFF		0x34
80 #define ENA_REGS_AENQ_BASE_LO_OFF		0x38
81 #define ENA_REGS_AENQ_BASE_HI_OFF		0x3c
82 #define ENA_REGS_AENQ_HEAD_DB_OFF		0x40
83 #define ENA_REGS_AENQ_TAIL_OFF		0x44
84 #define ENA_REGS_INTR_MASK_OFF		0x4c
85 #define ENA_REGS_DEV_CTL_OFF		0x54
86 #define ENA_REGS_DEV_STS_OFF		0x58
87 #define ENA_REGS_MMIO_REG_READ_OFF		0x5c
88 #define ENA_REGS_MMIO_RESP_LO_OFF		0x60
89 #define ENA_REGS_MMIO_RESP_HI_OFF		0x64
90 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF		0x68
91 
92 /* version register */
93 #define ENA_REGS_VERSION_MINOR_VERSION_MASK		0xff
94 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT		8
95 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK		0xff00
96 
97 /* controller_version register */
98 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK		0xff
99 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT		8
100 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK		0xff00
101 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT		16
102 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK		0xff0000
103 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT		24
104 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK		0xff000000
105 
106 /* caps register */
107 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK		0x1
108 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT		1
109 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK		0x3e
110 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT		8
111 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK		0xff00
112 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT		16
113 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK		0xf0000
114 
115 /* aq_caps register */
116 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK		0xffff
117 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT		16
118 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK		0xffff0000
119 
120 /* acq_caps register */
121 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK		0xffff
122 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT		16
123 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK		0xffff0000
124 
125 /* aenq_caps register */
126 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK		0xffff
127 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT		16
128 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK		0xffff0000
129 
130 /* dev_ctl register */
131 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK		0x1
132 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT		1
133 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK		0x2
134 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT		2
135 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK		0x4
136 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT		3
137 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK		0x8
138 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT		28
139 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK		0xf0000000
140 
141 /* dev_sts register */
142 #define ENA_REGS_DEV_STS_READY_MASK		0x1
143 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT		1
144 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK		0x2
145 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT		2
146 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK		0x4
147 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT		3
148 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK		0x8
149 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT		4
150 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK		0x10
151 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT		5
152 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK		0x20
153 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT		6
154 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK		0x40
155 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT		7
156 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK		0x80
157 
158 /* mmio_reg_read register */
159 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK		0xffff
160 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT		16
161 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK		0xffff0000
162 
163 /* rss_ind_entry_update register */
164 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK		0xffff
165 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT		16
166 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK		0xffff0000
167 
168 #endif /*_ENA_REGS_H_ */
169