1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _ENA_ETH_IO_H_ 34 #define _ENA_ETH_IO_H_ 35 36 enum ena_eth_io_l3_proto_index { 37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 38 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 39 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 40 ENA_ETH_IO_L3_PROTO_FCOE = 21, 41 ENA_ETH_IO_L3_PROTO_ROCE = 22, 42 }; 43 44 enum ena_eth_io_l4_proto_index { 45 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 46 ENA_ETH_IO_L4_PROTO_TCP = 12, 47 ENA_ETH_IO_L4_PROTO_UDP = 13, 48 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 49 }; 50 51 struct ena_eth_io_tx_desc { 52 /* 15:0 : length - Buffer length in bytes, must 53 * include any packet trailers that the ENA supposed 54 * to update like End-to-End CRC, Authentication GMAC 55 * etc. This length must not include the 56 * 'Push_Buffer' length. This length must not include 57 * the 4-byte added in the end for 802.3 Ethernet FCS 58 * 21:16 : req_id_hi - Request ID[15:10] 59 * 22 : reserved22 - MBZ 60 * 23 : meta_desc - MBZ 61 * 24 : phase 62 * 25 : reserved1 - MBZ 63 * 26 : first - Indicates first descriptor in 64 * transaction 65 * 27 : last - Indicates last descriptor in 66 * transaction 67 * 28 : comp_req - Indicates whether completion 68 * should be posted, after packet is transmitted. 69 * Valid only for first descriptor 70 * 30:29 : reserved29 - MBZ 71 * 31 : reserved31 - MBZ 72 */ 73 uint32_t len_ctrl; 74 75 /* 3:0 : l3_proto_idx - L3 protocol. This field 76 * required when l3_csum_en,l3_csum or tso_en are set. 77 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 78 * DF flags of the IPv4 header is 0. Otherwise must 79 * be set to 1 80 * 6:5 : reserved5 81 * 7 : tso_en - Enable TSO, For TCP only. 82 * 12:8 : l4_proto_idx - L4 protocol. This field need 83 * to be set when l4_csum_en or tso_en are set. 84 * 13 : l3_csum_en - enable IPv4 header checksum. 85 * 14 : l4_csum_en - enable TCP/UDP checksum. 86 * 15 : ethernet_fcs_dis - when set, the controller 87 * will not append the 802.3 Ethernet Frame Check 88 * Sequence to the packet 89 * 16 : reserved16 90 * 17 : l4_csum_partial - L4 partial checksum. when 91 * set to 0, the ENA calculates the L4 checksum, 92 * where the Destination Address required for the 93 * TCP/UDP pseudo-header is taken from the actual 94 * packet L3 header. when set to 1, the ENA doesn't 95 * calculate the sum of the pseudo-header, instead, 96 * the checksum field of the L4 is used instead. When 97 * TSO enabled, the checksum of the pseudo-header 98 * must not include the tcp length field. L4 partial 99 * checksum should be used for IPv6 packet that 100 * contains Routing Headers. 101 * 20:18 : reserved18 - MBZ 102 * 21 : reserved21 - MBZ 103 * 31:22 : req_id_lo - Request ID[9:0] 104 */ 105 uint32_t meta_ctrl; 106 107 uint32_t buff_addr_lo; 108 109 /* address high and header size 110 * 15:0 : addr_hi - Buffer Pointer[47:32] 111 * 23:16 : reserved16_w2 112 * 31:24 : header_length - Header length. For Low 113 * Latency Queues, this fields indicates the number 114 * of bytes written to the headers' memory. For 115 * normal queues, if packet is TCP or UDP, and longer 116 * than max_header_size, then this field should be 117 * set to the sum of L4 header offset and L4 header 118 * size(without options), otherwise, this field 119 * should be set to 0. For both modes, this field 120 * must not exceed the max_header_size. 121 * max_header_size value is reported by the Max 122 * Queues Feature descriptor 123 */ 124 uint32_t buff_addr_hi_hdr_sz; 125 }; 126 127 struct ena_eth_io_tx_meta_desc { 128 /* 9:0 : req_id_lo - Request ID[9:0] 129 * 11:10 : reserved10 - MBZ 130 * 12 : reserved12 - MBZ 131 * 13 : reserved13 - MBZ 132 * 14 : ext_valid - if set, offset fields in Word2 133 * are valid Also MSS High in Word 0 and bits [31:24] 134 * in Word 3 135 * 15 : reserved15 136 * 19:16 : mss_hi 137 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 138 * Extended Metadata Descriptor 139 * 21 : meta_store - Store extended metadata in queue 140 * cache 141 * 22 : reserved22 - MBZ 142 * 23 : meta_desc - MBO 143 * 24 : phase 144 * 25 : reserved25 - MBZ 145 * 26 : first - Indicates first descriptor in 146 * transaction 147 * 27 : last - Indicates last descriptor in 148 * transaction 149 * 28 : comp_req - Indicates whether completion 150 * should be posted, after packet is transmitted. 151 * Valid only for first descriptor 152 * 30:29 : reserved29 - MBZ 153 * 31 : reserved31 - MBZ 154 */ 155 uint32_t len_ctrl; 156 157 /* 5:0 : req_id_hi 158 * 31:6 : reserved6 - MBZ 159 */ 160 uint32_t word1; 161 162 /* 7:0 : l3_hdr_len 163 * 15:8 : l3_hdr_off 164 * 21:16 : l4_hdr_len_in_words - counts the L4 header 165 * length in words. there is an explicit assumption 166 * that L4 header appears right after L3 header and 167 * L4 offset is based on l3_hdr_off+l3_hdr_len 168 * 31:22 : mss_lo 169 */ 170 uint32_t word2; 171 172 uint32_t reserved; 173 }; 174 175 struct ena_eth_io_tx_cdesc { 176 /* Request ID[15:0] */ 177 uint16_t req_id; 178 179 uint8_t status; 180 181 /* flags 182 * 0 : phase 183 * 7:1 : reserved1 184 */ 185 uint8_t flags; 186 187 uint16_t sub_qid; 188 189 uint16_t sq_head_idx; 190 }; 191 192 struct ena_eth_io_rx_desc { 193 /* In bytes. 0 means 64KB */ 194 uint16_t length; 195 196 /* MBZ */ 197 uint8_t reserved2; 198 199 /* 0 : phase 200 * 1 : reserved1 - MBZ 201 * 2 : first - Indicates first descriptor in 202 * transaction 203 * 3 : last - Indicates last descriptor in transaction 204 * 4 : comp_req 205 * 5 : reserved5 - MBO 206 * 7:6 : reserved6 - MBZ 207 */ 208 uint8_t ctrl; 209 210 uint16_t req_id; 211 212 /* MBZ */ 213 uint16_t reserved6; 214 215 uint32_t buff_addr_lo; 216 217 uint16_t buff_addr_hi; 218 219 /* MBZ */ 220 uint16_t reserved16_w3; 221 }; 222 223 /* 4-word format Note: all ethernet parsing information are valid only when 224 * last=1 225 */ 226 struct ena_eth_io_rx_cdesc_base { 227 /* 4:0 : l3_proto_idx 228 * 6:5 : src_vlan_cnt 229 * 7 : reserved7 - MBZ 230 * 12:8 : l4_proto_idx 231 * 13 : l3_csum_err - when set, either the L3 232 * checksum error detected, or, the controller didn't 233 * validate the checksum. This bit is valid only when 234 * l3_proto_idx indicates IPv4 packet 235 * 14 : l4_csum_err - when set, either the L4 236 * checksum error detected, or, the controller didn't 237 * validate the checksum. This bit is valid only when 238 * l4_proto_idx indicates TCP/UDP packet, and, 239 * ipv4_frag is not set. This bit is valid only when 240 * l4_csum_checked below is set. 241 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 242 * 16 : l4_csum_checked - L4 checksum was verified 243 * (could be OK or error), when cleared the status of 244 * checksum is unknown 245 * 23:17 : reserved17 - MBZ 246 * 24 : phase 247 * 25 : l3_csum2 - second checksum engine result 248 * 26 : first - Indicates first descriptor in 249 * transaction 250 * 27 : last - Indicates last descriptor in 251 * transaction 252 * 29:28 : reserved28 253 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 254 * Descriptor was used 255 * 31 : reserved31 256 */ 257 uint32_t status; 258 259 uint16_t length; 260 261 uint16_t req_id; 262 263 /* 32-bit hash result */ 264 uint32_t hash; 265 266 uint16_t sub_qid; 267 268 uint16_t reserved; 269 }; 270 271 /* 8-word format */ 272 struct ena_eth_io_rx_cdesc_ext { 273 struct ena_eth_io_rx_cdesc_base base; 274 275 uint32_t buff_addr_lo; 276 277 uint16_t buff_addr_hi; 278 279 uint16_t reserved16; 280 281 uint32_t reserved_w6; 282 283 uint32_t reserved_w7; 284 }; 285 286 struct ena_eth_io_intr_reg { 287 /* 14:0 : rx_intr_delay 288 * 29:15 : tx_intr_delay 289 * 30 : intr_unmask 290 * 31 : reserved 291 */ 292 uint32_t intr_control; 293 }; 294 295 struct ena_eth_io_numa_node_cfg_reg { 296 /* 7:0 : numa 297 * 30:8 : reserved 298 * 31 : enabled 299 */ 300 uint32_t numa_cfg; 301 }; 302 303 /* tx_desc */ 304 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 305 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 306 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 307 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 308 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 309 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 310 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 311 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 312 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 313 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 314 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 315 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 316 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 317 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 318 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 319 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 320 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 321 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 322 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 323 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 324 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 325 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 326 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 327 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 328 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 329 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 330 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 331 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 332 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 333 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 334 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 335 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 336 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 337 338 /* tx_meta_desc */ 339 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 340 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 341 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 342 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 343 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 344 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 345 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 346 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 347 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 348 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 349 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 350 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 351 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 352 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 353 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 354 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 355 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 356 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 357 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 358 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 359 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 360 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 361 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 362 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 363 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 364 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 365 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 366 367 /* tx_cdesc */ 368 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 369 370 /* rx_desc */ 371 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 372 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 373 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 374 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 375 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 376 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 377 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 378 379 /* rx_cdesc_base */ 380 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 381 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 382 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 383 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 384 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 385 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 386 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 387 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 388 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 389 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 390 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 391 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 392 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) 393 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 394 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 395 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 396 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 397 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 398 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 399 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 400 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 401 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 402 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 403 404 /* intr_reg */ 405 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 406 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 407 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 408 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 409 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 410 411 /* numa_node_cfg_reg */ 412 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 413 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 414 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 415 416 #if !defined(DEFS_LINUX_MAINLINE) 417 static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) 418 { 419 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 420 } 421 422 static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) 423 { 424 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 425 } 426 427 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) 428 { 429 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; 430 } 431 432 static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 433 { 434 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; 435 } 436 437 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) 438 { 439 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; 440 } 441 442 static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) 443 { 444 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; 445 } 446 447 static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) 448 { 449 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; 450 } 451 452 static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) 453 { 454 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; 455 } 456 457 static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) 458 { 459 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; 460 } 461 462 static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) 463 { 464 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; 465 } 466 467 static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) 468 { 469 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; 470 } 471 472 static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) 473 { 474 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; 475 } 476 477 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) 478 { 479 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; 480 } 481 482 static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) 483 { 484 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; 485 } 486 487 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) 488 { 489 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 490 } 491 492 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 493 { 494 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 495 } 496 497 static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) 498 { 499 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; 500 } 501 502 static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) 503 { 504 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; 505 } 506 507 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) 508 { 509 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; 510 } 511 512 static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) 513 { 514 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; 515 } 516 517 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) 518 { 519 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; 520 } 521 522 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 523 { 524 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; 525 } 526 527 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) 528 { 529 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; 530 } 531 532 static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 533 { 534 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; 535 } 536 537 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) 538 { 539 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; 540 } 541 542 static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 543 { 544 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; 545 } 546 547 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) 548 { 549 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; 550 } 551 552 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) 553 { 554 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; 555 } 556 557 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) 558 { 559 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; 560 } 561 562 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) 563 { 564 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; 565 } 566 567 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) 568 { 569 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; 570 } 571 572 static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) 573 { 574 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; 575 } 576 577 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) 578 { 579 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 580 } 581 582 static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 583 { 584 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 585 } 586 587 static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) 588 { 589 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; 590 } 591 592 static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) 593 { 594 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; 595 } 596 597 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) 598 { 599 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 600 } 601 602 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 603 { 604 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 605 } 606 607 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) 608 { 609 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; 610 } 611 612 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 613 { 614 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; 615 } 616 617 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) 618 { 619 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; 620 } 621 622 static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 623 { 624 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; 625 } 626 627 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) 628 { 629 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; 630 } 631 632 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 633 { 634 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; 635 } 636 637 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) 638 { 639 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; 640 } 641 642 static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 643 { 644 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; 645 } 646 647 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) 648 { 649 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; 650 } 651 652 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 653 { 654 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; 655 } 656 657 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) 658 { 659 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; 660 } 661 662 static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 663 { 664 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; 665 } 666 667 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) 668 { 669 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; 670 } 671 672 static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 673 { 674 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; 675 } 676 677 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) 678 { 679 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; 680 } 681 682 static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 683 { 684 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; 685 } 686 687 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) 688 { 689 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; 690 } 691 692 static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 693 { 694 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; 695 } 696 697 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) 698 { 699 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 700 } 701 702 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 703 { 704 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 705 } 706 707 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) 708 { 709 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 710 } 711 712 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 713 { 714 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 715 } 716 717 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) 718 { 719 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; 720 } 721 722 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 723 { 724 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; 725 } 726 727 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) 728 { 729 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; 730 } 731 732 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 733 { 734 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; 735 } 736 737 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) 738 { 739 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; 740 } 741 742 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 743 { 744 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; 745 } 746 747 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) 748 { 749 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 750 } 751 752 static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) 753 { 754 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 755 } 756 757 static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) 758 { 759 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; 760 } 761 762 static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) 763 { 764 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; 765 } 766 767 static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) 768 { 769 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; 770 } 771 772 static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) 773 { 774 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; 775 } 776 777 static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) 778 { 779 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; 780 } 781 782 static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) 783 { 784 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; 785 } 786 787 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) 788 { 789 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; 790 } 791 792 static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) 793 { 794 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; 795 } 796 797 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 798 { 799 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 800 } 801 802 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 803 { 804 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 805 } 806 807 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) 808 { 809 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; 810 } 811 812 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 813 { 814 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; 815 } 816 817 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 818 { 819 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; 820 } 821 822 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 823 { 824 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; 825 } 826 827 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 828 { 829 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; 830 } 831 832 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 833 { 834 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; 835 } 836 837 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 838 { 839 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; 840 } 841 842 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 843 { 844 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; 845 } 846 847 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) 848 { 849 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; 850 } 851 852 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 853 { 854 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; 855 } 856 857 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p) 858 { 859 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT; 860 } 861 862 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 863 { 864 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; 865 } 866 867 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) 868 { 869 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; 870 } 871 872 static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 873 { 874 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; 875 } 876 877 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) 878 { 879 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; 880 } 881 882 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 883 { 884 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; 885 } 886 887 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) 888 { 889 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; 890 } 891 892 static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 893 { 894 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; 895 } 896 897 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) 898 { 899 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; 900 } 901 902 static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 903 { 904 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; 905 } 906 907 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) 908 { 909 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; 910 } 911 912 static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 913 { 914 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; 915 } 916 917 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) 918 { 919 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 920 } 921 922 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 923 { 924 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 925 } 926 927 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) 928 { 929 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; 930 } 931 932 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 933 { 934 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 935 } 936 937 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) 938 { 939 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; 940 } 941 942 static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) 943 { 944 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 945 } 946 947 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) 948 { 949 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 950 } 951 952 static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 953 { 954 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 955 } 956 957 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) 958 { 959 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; 960 } 961 962 static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 963 { 964 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; 965 } 966 967 #endif /* !defined(DEFS_LINUX_MAINLINE) */ 968 #endif /*_ENA_ETH_IO_H_ */ 969