1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETH_IO_H_ 35 #define _ENA_ETH_IO_H_ 36 37 enum ena_eth_io_l3_proto_index { 38 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 39 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 40 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 41 ENA_ETH_IO_L3_PROTO_FCOE = 21, 42 ENA_ETH_IO_L3_PROTO_ROCE = 22, 43 }; 44 45 enum ena_eth_io_l4_proto_index { 46 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 47 ENA_ETH_IO_L4_PROTO_TCP = 12, 48 ENA_ETH_IO_L4_PROTO_UDP = 13, 49 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 50 }; 51 52 struct ena_eth_io_tx_desc { 53 /* 15:0 : length - Buffer length in bytes, must 54 * include any packet trailers that the ENA supposed 55 * to update like End-to-End CRC, Authentication GMAC 56 * etc. This length must not include the 57 * 'Push_Buffer' length. This length must not include 58 * the 4-byte added in the end for 802.3 Ethernet FCS 59 * 21:16 : req_id_hi - Request ID[15:10] 60 * 22 : reserved22 - MBZ 61 * 23 : meta_desc - MBZ 62 * 24 : phase 63 * 25 : reserved1 - MBZ 64 * 26 : first - Indicates first descriptor in 65 * transaction 66 * 27 : last - Indicates last descriptor in 67 * transaction 68 * 28 : comp_req - Indicates whether completion 69 * should be posted, after packet is transmitted. 70 * Valid only for first descriptor 71 * 30:29 : reserved29 - MBZ 72 * 31 : reserved31 - MBZ 73 */ 74 uint32_t len_ctrl; 75 76 /* 3:0 : l3_proto_idx - L3 protocol. This field 77 * required when l3_csum_en,l3_csum or tso_en are set. 78 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 79 * DF flags of the IPv4 header is 0. Otherwise must 80 * be set to 1 81 * 6:5 : reserved5 82 * 7 : tso_en - Enable TSO, For TCP only. 83 * 12:8 : l4_proto_idx - L4 protocol. This field need 84 * to be set when l4_csum_en or tso_en are set. 85 * 13 : l3_csum_en - enable IPv4 header checksum. 86 * 14 : l4_csum_en - enable TCP/UDP checksum. 87 * 15 : ethernet_fcs_dis - when set, the controller 88 * will not append the 802.3 Ethernet Frame Check 89 * Sequence to the packet 90 * 16 : reserved16 91 * 17 : l4_csum_partial - L4 partial checksum. when 92 * set to 0, the ENA calculates the L4 checksum, 93 * where the Destination Address required for the 94 * TCP/UDP pseudo-header is taken from the actual 95 * packet L3 header. when set to 1, the ENA doesn't 96 * calculate the sum of the pseudo-header, instead, 97 * the checksum field of the L4 is used instead. When 98 * TSO enabled, the checksum of the pseudo-header 99 * must not include the tcp length field. L4 partial 100 * checksum should be used for IPv6 packet that 101 * contains Routing Headers. 102 * 20:18 : reserved18 - MBZ 103 * 21 : reserved21 - MBZ 104 * 31:22 : req_id_lo - Request ID[9:0] 105 */ 106 uint32_t meta_ctrl; 107 108 uint32_t buff_addr_lo; 109 110 /* address high and header size 111 * 15:0 : addr_hi - Buffer Pointer[47:32] 112 * 23:16 : reserved16_w2 113 * 31:24 : header_length - Header length. For Low 114 * Latency Queues, this fields indicates the number 115 * of bytes written to the headers' memory. For 116 * normal queues, if packet is TCP or UDP, and longer 117 * than max_header_size, then this field should be 118 * set to the sum of L4 header offset and L4 header 119 * size(without options), otherwise, this field 120 * should be set to 0. For both modes, this field 121 * must not exceed the max_header_size. 122 * max_header_size value is reported by the Max 123 * Queues Feature descriptor 124 */ 125 uint32_t buff_addr_hi_hdr_sz; 126 }; 127 128 struct ena_eth_io_tx_meta_desc { 129 /* 9:0 : req_id_lo - Request ID[9:0] 130 * 11:10 : reserved10 - MBZ 131 * 12 : reserved12 - MBZ 132 * 13 : reserved13 - MBZ 133 * 14 : ext_valid - if set, offset fields in Word2 134 * are valid Also MSS High in Word 0 and bits [31:24] 135 * in Word 3 136 * 15 : reserved15 137 * 19:16 : mss_hi 138 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 139 * Extended Metadata Descriptor 140 * 21 : meta_store - Store extended metadata in queue 141 * cache 142 * 22 : reserved22 - MBZ 143 * 23 : meta_desc - MBO 144 * 24 : phase 145 * 25 : reserved25 - MBZ 146 * 26 : first - Indicates first descriptor in 147 * transaction 148 * 27 : last - Indicates last descriptor in 149 * transaction 150 * 28 : comp_req - Indicates whether completion 151 * should be posted, after packet is transmitted. 152 * Valid only for first descriptor 153 * 30:29 : reserved29 - MBZ 154 * 31 : reserved31 - MBZ 155 */ 156 uint32_t len_ctrl; 157 158 /* 5:0 : req_id_hi 159 * 31:6 : reserved6 - MBZ 160 */ 161 uint32_t word1; 162 163 /* 7:0 : l3_hdr_len 164 * 15:8 : l3_hdr_off 165 * 21:16 : l4_hdr_len_in_words - counts the L4 header 166 * length in words. there is an explicit assumption 167 * that L4 header appears right after L3 header and 168 * L4 offset is based on l3_hdr_off+l3_hdr_len 169 * 31:22 : mss_lo 170 */ 171 uint32_t word2; 172 173 uint32_t reserved; 174 }; 175 176 struct ena_eth_io_tx_cdesc { 177 /* Request ID[15:0] */ 178 uint16_t req_id; 179 180 uint8_t status; 181 182 /* flags 183 * 0 : phase 184 * 5:1 : reserved1 185 * 7:6 : mbz6 - MBZ 186 */ 187 uint8_t flags; 188 189 uint16_t sub_qid; 190 191 uint16_t sq_head_idx; 192 }; 193 194 struct ena_eth_io_rx_desc { 195 /* In bytes. 0 means 64KB */ 196 uint16_t length; 197 198 /* MBZ */ 199 uint8_t reserved2; 200 201 /* 0 : phase 202 * 1 : reserved1 - MBZ 203 * 2 : first - Indicates first descriptor in 204 * transaction 205 * 3 : last - Indicates last descriptor in transaction 206 * 4 : comp_req 207 * 5 : reserved5 - MBO 208 * 7:6 : reserved6 - MBZ 209 */ 210 uint8_t ctrl; 211 212 uint16_t req_id; 213 214 /* MBZ */ 215 uint16_t reserved6; 216 217 uint32_t buff_addr_lo; 218 219 uint16_t buff_addr_hi; 220 221 /* MBZ */ 222 uint16_t reserved16_w3; 223 }; 224 225 /* 4-word format Note: all ethernet parsing information are valid only when 226 * last=1 227 */ 228 struct ena_eth_io_rx_cdesc_base { 229 /* 4:0 : l3_proto_idx 230 * 6:5 : src_vlan_cnt 231 * 7 : mbz7 - MBZ 232 * 12:8 : l4_proto_idx 233 * 13 : l3_csum_err - when set, either the L3 234 * checksum error detected, or, the controller didn't 235 * validate the checksum. This bit is valid only when 236 * l3_proto_idx indicates IPv4 packet 237 * 14 : l4_csum_err - when set, either the L4 238 * checksum error detected, or, the controller didn't 239 * validate the checksum. This bit is valid only when 240 * l4_proto_idx indicates TCP/UDP packet, and, 241 * ipv4_frag is not set. This bit is valid only when 242 * l4_csum_checked below is set. 243 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 244 * 16 : l4_csum_checked - L4 checksum was verified 245 * (could be OK or error), when cleared the status of 246 * checksum is unknown 247 * 17 : mbz17 - MBZ 248 * 23:18 : reserved18 249 * 24 : phase 250 * 25 : l3_csum2 - second checksum engine result 251 * 26 : first - Indicates first descriptor in 252 * transaction 253 * 27 : last - Indicates last descriptor in 254 * transaction 255 * 29:28 : reserved28 256 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 257 * Descriptor was used 258 * 31 : reserved31 259 */ 260 uint32_t status; 261 262 uint16_t length; 263 264 uint16_t req_id; 265 266 /* 32-bit hash result */ 267 uint32_t hash; 268 269 uint16_t sub_qid; 270 271 uint8_t offset; 272 273 uint8_t reserved; 274 }; 275 276 /* 8-word format */ 277 struct ena_eth_io_rx_cdesc_ext { 278 struct ena_eth_io_rx_cdesc_base base; 279 280 uint32_t buff_addr_lo; 281 282 uint16_t buff_addr_hi; 283 284 uint16_t reserved16; 285 286 uint32_t reserved_w6; 287 288 uint32_t reserved_w7; 289 }; 290 291 struct ena_eth_io_intr_reg { 292 /* 14:0 : rx_intr_delay 293 * 29:15 : tx_intr_delay 294 * 30 : intr_unmask 295 * 31 : no_moderation_update - 0 - moderation 296 * updated, 1 - moderation not updated 297 */ 298 uint32_t intr_control; 299 }; 300 301 struct ena_eth_io_numa_node_cfg_reg { 302 /* 7:0 : numa 303 * 30:8 : reserved 304 * 31 : enabled 305 */ 306 uint32_t numa_cfg; 307 }; 308 309 /* tx_desc */ 310 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 311 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 312 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 313 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 314 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 315 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 316 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 317 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 318 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 319 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 320 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 321 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 322 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 323 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 324 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 325 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 326 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 327 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 328 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 329 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 330 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 331 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 332 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 333 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 334 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 335 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 336 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 337 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 338 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 339 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 340 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 341 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 342 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 343 344 /* tx_meta_desc */ 345 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 346 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 347 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 348 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 349 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 350 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 351 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 352 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 353 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 354 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 355 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 356 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 357 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 358 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 359 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 360 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 361 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 362 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 363 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 364 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 365 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 366 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 367 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 368 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 369 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 370 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 371 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 372 373 /* tx_cdesc */ 374 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 375 #define ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT 6 376 #define ENA_ETH_IO_TX_CDESC_MBZ6_MASK GENMASK(7, 6) 377 378 /* rx_desc */ 379 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 380 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 381 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 382 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 383 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 384 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 385 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 386 387 /* rx_cdesc_base */ 388 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 389 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 390 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 391 #define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT 7 392 #define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK BIT(7) 393 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 394 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 395 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 396 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 397 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 398 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 399 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 400 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 401 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 402 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) 403 #define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT 17 404 #define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK BIT(17) 405 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 406 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 407 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 408 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 409 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 410 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 411 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 412 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 413 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 414 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 415 416 /* intr_reg */ 417 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 418 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 419 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 420 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 421 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 422 #define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT 31 423 #define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK BIT(31) 424 425 /* numa_node_cfg_reg */ 426 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 427 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 428 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 429 430 #if !defined(DEFS_LINUX_MAINLINE) 431 static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) 432 { 433 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 434 } 435 436 static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) 437 { 438 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 439 } 440 441 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) 442 { 443 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; 444 } 445 446 static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 447 { 448 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; 449 } 450 451 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) 452 { 453 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; 454 } 455 456 static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) 457 { 458 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; 459 } 460 461 static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) 462 { 463 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; 464 } 465 466 static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) 467 { 468 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; 469 } 470 471 static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) 472 { 473 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; 474 } 475 476 static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) 477 { 478 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; 479 } 480 481 static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) 482 { 483 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; 484 } 485 486 static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) 487 { 488 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; 489 } 490 491 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) 492 { 493 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; 494 } 495 496 static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) 497 { 498 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; 499 } 500 501 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) 502 { 503 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 504 } 505 506 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 507 { 508 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 509 } 510 511 static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) 512 { 513 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; 514 } 515 516 static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) 517 { 518 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; 519 } 520 521 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) 522 { 523 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; 524 } 525 526 static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) 527 { 528 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; 529 } 530 531 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) 532 { 533 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; 534 } 535 536 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 537 { 538 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; 539 } 540 541 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) 542 { 543 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; 544 } 545 546 static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 547 { 548 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; 549 } 550 551 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) 552 { 553 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; 554 } 555 556 static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 557 { 558 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; 559 } 560 561 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) 562 { 563 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; 564 } 565 566 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) 567 { 568 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; 569 } 570 571 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) 572 { 573 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; 574 } 575 576 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) 577 { 578 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; 579 } 580 581 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) 582 { 583 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; 584 } 585 586 static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) 587 { 588 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; 589 } 590 591 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) 592 { 593 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 594 } 595 596 static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 597 { 598 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 599 } 600 601 static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) 602 { 603 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; 604 } 605 606 static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) 607 { 608 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; 609 } 610 611 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) 612 { 613 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 614 } 615 616 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 617 { 618 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 619 } 620 621 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) 622 { 623 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; 624 } 625 626 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 627 { 628 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; 629 } 630 631 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) 632 { 633 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; 634 } 635 636 static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 637 { 638 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; 639 } 640 641 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) 642 { 643 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; 644 } 645 646 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 647 { 648 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; 649 } 650 651 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) 652 { 653 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; 654 } 655 656 static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 657 { 658 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; 659 } 660 661 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) 662 { 663 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; 664 } 665 666 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 667 { 668 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; 669 } 670 671 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) 672 { 673 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; 674 } 675 676 static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 677 { 678 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; 679 } 680 681 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) 682 { 683 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; 684 } 685 686 static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 687 { 688 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; 689 } 690 691 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) 692 { 693 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; 694 } 695 696 static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 697 { 698 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; 699 } 700 701 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) 702 { 703 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; 704 } 705 706 static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 707 { 708 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; 709 } 710 711 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) 712 { 713 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 714 } 715 716 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 717 { 718 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 719 } 720 721 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) 722 { 723 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 724 } 725 726 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 727 { 728 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 729 } 730 731 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) 732 { 733 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; 734 } 735 736 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 737 { 738 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; 739 } 740 741 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) 742 { 743 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; 744 } 745 746 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 747 { 748 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; 749 } 750 751 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) 752 { 753 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; 754 } 755 756 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 757 { 758 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; 759 } 760 761 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) 762 { 763 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 764 } 765 766 static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) 767 { 768 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 769 } 770 771 static inline uint8_t get_ena_eth_io_tx_cdesc_mbz6(const struct ena_eth_io_tx_cdesc *p) 772 { 773 return (p->flags & ENA_ETH_IO_TX_CDESC_MBZ6_MASK) >> ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT; 774 } 775 static inline void set_ena_eth_io_tx_cdesc_mbz6(struct ena_eth_io_tx_cdesc *p, uint8_t val) 776 { 777 p->flags |= (val << ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT) & ENA_ETH_IO_TX_CDESC_MBZ6_MASK; 778 } 779 780 static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) 781 { 782 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; 783 } 784 785 static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) 786 { 787 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; 788 } 789 790 static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) 791 { 792 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; 793 } 794 795 static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) 796 { 797 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; 798 } 799 800 static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) 801 { 802 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; 803 } 804 805 static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) 806 { 807 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; 808 } 809 810 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) 811 { 812 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; 813 } 814 815 static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) 816 { 817 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; 818 } 819 820 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 821 { 822 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 823 } 824 825 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 826 { 827 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 828 } 829 830 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) 831 { 832 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; 833 } 834 835 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 836 { 837 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; 838 } 839 840 static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz7(const struct ena_eth_io_rx_cdesc_base *p) 841 { 842 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT; 843 } 844 845 static inline void set_ena_eth_io_rx_cdesc_base_mbz7(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 846 { 847 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK; 848 } 849 850 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 851 { 852 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; 853 } 854 855 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 856 { 857 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; 858 } 859 860 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 861 { 862 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; 863 } 864 865 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 866 { 867 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; 868 } 869 870 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 871 { 872 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; 873 } 874 875 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 876 { 877 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; 878 } 879 880 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) 881 { 882 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; 883 } 884 885 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 886 { 887 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; 888 } 889 890 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p) 891 { 892 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT; 893 } 894 895 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 896 { 897 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; 898 } 899 900 static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz17(const struct ena_eth_io_rx_cdesc_base *p) 901 { 902 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT; 903 } 904 905 static inline void set_ena_eth_io_rx_cdesc_base_mbz17(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 906 { 907 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK; 908 } 909 910 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) 911 { 912 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; 913 } 914 915 static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 916 { 917 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; 918 } 919 920 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) 921 { 922 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; 923 } 924 925 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 926 { 927 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; 928 } 929 930 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) 931 { 932 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; 933 } 934 935 static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 936 { 937 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; 938 } 939 940 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) 941 { 942 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; 943 } 944 945 static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 946 { 947 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; 948 } 949 950 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) 951 { 952 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; 953 } 954 955 static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 956 { 957 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; 958 } 959 960 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) 961 { 962 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 963 } 964 965 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 966 { 967 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 968 } 969 970 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) 971 { 972 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; 973 } 974 975 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 976 { 977 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 978 } 979 980 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) 981 { 982 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; 983 } 984 985 static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) 986 { 987 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 988 } 989 990 static inline uint32_t get_ena_eth_io_intr_reg_no_moderation_update(const struct ena_eth_io_intr_reg *p) 991 { 992 return (p->intr_control & ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK) >> ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT; 993 } 994 995 static inline void set_ena_eth_io_intr_reg_no_moderation_update(struct ena_eth_io_intr_reg *p, uint32_t val) 996 { 997 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) & ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK; 998 } 999 1000 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) 1001 { 1002 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 1003 } 1004 1005 static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 1006 { 1007 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 1008 } 1009 1010 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) 1011 { 1012 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; 1013 } 1014 1015 static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 1016 { 1017 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; 1018 } 1019 1020 #endif /* !defined(DEFS_LINUX_MAINLINE) */ 1021 #endif /* _ENA_ETH_IO_H_ */ 1022