1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETH_IO_H_ 35 #define _ENA_ETH_IO_H_ 36 37 enum ena_eth_io_l3_proto_index { 38 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 39 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 40 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 41 ENA_ETH_IO_L3_PROTO_FCOE = 21, 42 ENA_ETH_IO_L3_PROTO_ROCE = 22, 43 }; 44 45 enum ena_eth_io_l4_proto_index { 46 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 47 ENA_ETH_IO_L4_PROTO_TCP = 12, 48 ENA_ETH_IO_L4_PROTO_UDP = 13, 49 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 50 }; 51 52 struct ena_eth_io_tx_desc { 53 /* 15:0 : length - Buffer length in bytes, must 54 * include any packet trailers that the ENA supposed 55 * to update like End-to-End CRC, Authentication GMAC 56 * etc. This length must not include the 57 * 'Push_Buffer' length. This length must not include 58 * the 4-byte added in the end for 802.3 Ethernet FCS 59 * 21:16 : req_id_hi - Request ID[15:10] 60 * 22 : reserved22 - MBZ 61 * 23 : meta_desc - MBZ 62 * 24 : phase 63 * 25 : reserved1 - MBZ 64 * 26 : first - Indicates first descriptor in 65 * transaction 66 * 27 : last - Indicates last descriptor in 67 * transaction 68 * 28 : comp_req - Indicates whether completion 69 * should be posted, after packet is transmitted. 70 * Valid only for first descriptor 71 * 30:29 : reserved29 - MBZ 72 * 31 : reserved31 - MBZ 73 */ 74 uint32_t len_ctrl; 75 76 /* 3:0 : l3_proto_idx - L3 protocol. This field 77 * required when l3_csum_en,l3_csum or tso_en are set. 78 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 79 * DF flags of the IPv4 header is 0. Otherwise must 80 * be set to 1 81 * 6:5 : reserved5 82 * 7 : tso_en - Enable TSO, For TCP only. 83 * 12:8 : l4_proto_idx - L4 protocol. This field need 84 * to be set when l4_csum_en or tso_en are set. 85 * 13 : l3_csum_en - enable IPv4 header checksum. 86 * 14 : l4_csum_en - enable TCP/UDP checksum. 87 * 15 : ethernet_fcs_dis - when set, the controller 88 * will not append the 802.3 Ethernet Frame Check 89 * Sequence to the packet 90 * 16 : reserved16 91 * 17 : l4_csum_partial - L4 partial checksum. when 92 * set to 0, the ENA calculates the L4 checksum, 93 * where the Destination Address required for the 94 * TCP/UDP pseudo-header is taken from the actual 95 * packet L3 header. when set to 1, the ENA doesn't 96 * calculate the sum of the pseudo-header, instead, 97 * the checksum field of the L4 is used instead. When 98 * TSO enabled, the checksum of the pseudo-header 99 * must not include the tcp length field. L4 partial 100 * checksum should be used for IPv6 packet that 101 * contains Routing Headers. 102 * 20:18 : reserved18 - MBZ 103 * 21 : reserved21 - MBZ 104 * 31:22 : req_id_lo - Request ID[9:0] 105 */ 106 uint32_t meta_ctrl; 107 108 uint32_t buff_addr_lo; 109 110 /* address high and header size 111 * 15:0 : addr_hi - Buffer Pointer[47:32] 112 * 23:16 : reserved16_w2 113 * 31:24 : header_length - Header length. For Low 114 * Latency Queues, this fields indicates the number 115 * of bytes written to the headers' memory. For 116 * normal queues, if packet is TCP or UDP, and longer 117 * than max_header_size, then this field should be 118 * set to the sum of L4 header offset and L4 header 119 * size(without options), otherwise, this field 120 * should be set to 0. For both modes, this field 121 * must not exceed the max_header_size. 122 * max_header_size value is reported by the Max 123 * Queues Feature descriptor 124 */ 125 uint32_t buff_addr_hi_hdr_sz; 126 }; 127 128 struct ena_eth_io_tx_meta_desc { 129 /* 9:0 : req_id_lo - Request ID[9:0] 130 * 11:10 : reserved10 - MBZ 131 * 12 : reserved12 - MBZ 132 * 13 : reserved13 - MBZ 133 * 14 : ext_valid - if set, offset fields in Word2 134 * are valid Also MSS High in Word 0 and bits [31:24] 135 * in Word 3 136 * 15 : reserved15 137 * 19:16 : mss_hi 138 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 139 * Extended Metadata Descriptor 140 * 21 : meta_store - Store extended metadata in queue 141 * cache 142 * 22 : reserved22 - MBZ 143 * 23 : meta_desc - MBO 144 * 24 : phase 145 * 25 : reserved25 - MBZ 146 * 26 : first - Indicates first descriptor in 147 * transaction 148 * 27 : last - Indicates last descriptor in 149 * transaction 150 * 28 : comp_req - Indicates whether completion 151 * should be posted, after packet is transmitted. 152 * Valid only for first descriptor 153 * 30:29 : reserved29 - MBZ 154 * 31 : reserved31 - MBZ 155 */ 156 uint32_t len_ctrl; 157 158 /* 5:0 : req_id_hi 159 * 31:6 : reserved6 - MBZ 160 */ 161 uint32_t word1; 162 163 /* 7:0 : l3_hdr_len 164 * 15:8 : l3_hdr_off 165 * 21:16 : l4_hdr_len_in_words - counts the L4 header 166 * length in words. there is an explicit assumption 167 * that L4 header appears right after L3 header and 168 * L4 offset is based on l3_hdr_off+l3_hdr_len 169 * 31:22 : mss_lo 170 */ 171 uint32_t word2; 172 173 uint32_t reserved; 174 }; 175 176 struct ena_eth_io_tx_cdesc { 177 /* Request ID[15:0] */ 178 uint16_t req_id; 179 180 uint8_t status; 181 182 /* flags 183 * 0 : phase 184 * 7:1 : reserved1 185 */ 186 uint8_t flags; 187 188 uint16_t sub_qid; 189 190 uint16_t sq_head_idx; 191 }; 192 193 struct ena_eth_io_rx_desc { 194 /* In bytes. 0 means 64KB */ 195 uint16_t length; 196 197 /* MBZ */ 198 uint8_t reserved2; 199 200 /* 0 : phase 201 * 1 : reserved1 - MBZ 202 * 2 : first - Indicates first descriptor in 203 * transaction 204 * 3 : last - Indicates last descriptor in transaction 205 * 4 : comp_req 206 * 5 : reserved5 - MBO 207 * 7:6 : reserved6 - MBZ 208 */ 209 uint8_t ctrl; 210 211 uint16_t req_id; 212 213 /* MBZ */ 214 uint16_t reserved6; 215 216 uint32_t buff_addr_lo; 217 218 uint16_t buff_addr_hi; 219 220 /* MBZ */ 221 uint16_t reserved16_w3; 222 }; 223 224 /* 4-word format Note: all ethernet parsing information are valid only when 225 * last=1 226 */ 227 struct ena_eth_io_rx_cdesc_base { 228 /* 4:0 : l3_proto_idx 229 * 6:5 : src_vlan_cnt 230 * 7 : reserved7 - MBZ 231 * 12:8 : l4_proto_idx 232 * 13 : l3_csum_err - when set, either the L3 233 * checksum error detected, or, the controller didn't 234 * validate the checksum. This bit is valid only when 235 * l3_proto_idx indicates IPv4 packet 236 * 14 : l4_csum_err - when set, either the L4 237 * checksum error detected, or, the controller didn't 238 * validate the checksum. This bit is valid only when 239 * l4_proto_idx indicates TCP/UDP packet, and, 240 * ipv4_frag is not set. This bit is valid only when 241 * l4_csum_checked below is set. 242 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 243 * 16 : l4_csum_checked - L4 checksum was verified 244 * (could be OK or error), when cleared the status of 245 * checksum is unknown 246 * 23:17 : reserved17 - MBZ 247 * 24 : phase 248 * 25 : l3_csum2 - second checksum engine result 249 * 26 : first - Indicates first descriptor in 250 * transaction 251 * 27 : last - Indicates last descriptor in 252 * transaction 253 * 29:28 : reserved28 254 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 255 * Descriptor was used 256 * 31 : reserved31 257 */ 258 uint32_t status; 259 260 uint16_t length; 261 262 uint16_t req_id; 263 264 /* 32-bit hash result */ 265 uint32_t hash; 266 267 uint16_t sub_qid; 268 269 uint8_t offset; 270 271 uint8_t reserved; 272 }; 273 274 /* 8-word format */ 275 struct ena_eth_io_rx_cdesc_ext { 276 struct ena_eth_io_rx_cdesc_base base; 277 278 uint32_t buff_addr_lo; 279 280 uint16_t buff_addr_hi; 281 282 uint16_t reserved16; 283 284 uint32_t reserved_w6; 285 286 uint32_t reserved_w7; 287 }; 288 289 struct ena_eth_io_intr_reg { 290 /* 14:0 : rx_intr_delay 291 * 29:15 : tx_intr_delay 292 * 30 : intr_unmask 293 * 31 : no_moderation_update - 0 - moderation 294 * updated, 1 - moderation not updated 295 */ 296 uint32_t intr_control; 297 }; 298 299 struct ena_eth_io_numa_node_cfg_reg { 300 /* 7:0 : numa 301 * 30:8 : reserved 302 * 31 : enabled 303 */ 304 uint32_t numa_cfg; 305 }; 306 307 /* tx_desc */ 308 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 309 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 310 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 311 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 312 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 313 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 314 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 315 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 316 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 317 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 318 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 319 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 320 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 321 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 322 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 323 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 324 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 325 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 326 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 327 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 328 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 329 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 330 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 331 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 332 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 333 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 334 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 335 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 336 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 337 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 338 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 339 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 340 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 341 342 /* tx_meta_desc */ 343 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 344 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 345 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 346 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 347 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 348 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 349 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 350 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 351 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 352 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 353 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 354 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 355 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 356 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 357 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 358 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 359 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 360 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 361 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 362 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 363 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 364 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 365 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 366 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 367 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 368 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 369 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 370 371 /* tx_cdesc */ 372 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 373 374 /* rx_desc */ 375 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 376 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 377 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 378 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 379 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 380 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 381 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 382 383 /* rx_cdesc_base */ 384 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 385 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 386 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 387 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 388 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 389 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 390 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 391 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 392 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 393 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 394 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 395 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16 396 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16) 397 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 398 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 399 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 400 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 401 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 402 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 403 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 404 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 405 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 406 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 407 408 /* intr_reg */ 409 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 410 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 411 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 412 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 413 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 414 #define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT 31 415 #define ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK BIT(31) 416 417 /* numa_node_cfg_reg */ 418 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 419 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 420 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 421 422 #if !defined(DEFS_LINUX_MAINLINE) 423 static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p) 424 { 425 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 426 } 427 428 static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val) 429 { 430 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK; 431 } 432 433 static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p) 434 { 435 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT; 436 } 437 438 static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 439 { 440 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK; 441 } 442 443 static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p) 444 { 445 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT; 446 } 447 448 static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val) 449 { 450 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK; 451 } 452 453 static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p) 454 { 455 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT; 456 } 457 458 static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val) 459 { 460 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK; 461 } 462 463 static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p) 464 { 465 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT; 466 } 467 468 static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val) 469 { 470 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK; 471 } 472 473 static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p) 474 { 475 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT; 476 } 477 478 static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val) 479 { 480 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK; 481 } 482 483 static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p) 484 { 485 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT; 486 } 487 488 static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val) 489 { 490 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK; 491 } 492 493 static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p) 494 { 495 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 496 } 497 498 static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 499 { 500 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK; 501 } 502 503 static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p) 504 { 505 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT; 506 } 507 508 static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val) 509 { 510 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK; 511 } 512 513 static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p) 514 { 515 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT; 516 } 517 518 static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val) 519 { 520 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK; 521 } 522 523 static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p) 524 { 525 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT; 526 } 527 528 static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val) 529 { 530 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK; 531 } 532 533 static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p) 534 { 535 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT; 536 } 537 538 static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 539 { 540 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK; 541 } 542 543 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p) 544 { 545 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT; 546 } 547 548 static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val) 549 { 550 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK; 551 } 552 553 static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p) 554 { 555 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT; 556 } 557 558 static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val) 559 { 560 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK; 561 } 562 563 static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p) 564 { 565 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT; 566 } 567 568 static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val) 569 { 570 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK; 571 } 572 573 static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p) 574 { 575 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT; 576 } 577 578 static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val) 579 { 580 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK; 581 } 582 583 static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p) 584 { 585 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 586 } 587 588 static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val) 589 { 590 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK; 591 } 592 593 static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p) 594 { 595 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT; 596 } 597 598 static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val) 599 { 600 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK; 601 } 602 603 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p) 604 { 605 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 606 } 607 608 static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 609 { 610 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK; 611 } 612 613 static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p) 614 { 615 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT; 616 } 617 618 static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 619 { 620 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK; 621 } 622 623 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p) 624 { 625 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT; 626 } 627 628 static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 629 { 630 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK; 631 } 632 633 static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p) 634 { 635 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT; 636 } 637 638 static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 639 { 640 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK; 641 } 642 643 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p) 644 { 645 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT; 646 } 647 648 static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 649 { 650 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK; 651 } 652 653 static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p) 654 { 655 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT; 656 } 657 658 static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 659 { 660 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK; 661 } 662 663 static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p) 664 { 665 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT; 666 } 667 668 static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 669 { 670 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK; 671 } 672 673 static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p) 674 { 675 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT; 676 } 677 678 static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 679 { 680 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK; 681 } 682 683 static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p) 684 { 685 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT; 686 } 687 688 static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 689 { 690 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK; 691 } 692 693 static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p) 694 { 695 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT; 696 } 697 698 static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 699 { 700 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK; 701 } 702 703 static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p) 704 { 705 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 706 } 707 708 static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 709 { 710 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK; 711 } 712 713 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p) 714 { 715 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 716 } 717 718 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 719 { 720 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK; 721 } 722 723 static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p) 724 { 725 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT; 726 } 727 728 static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 729 { 730 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK; 731 } 732 733 static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p) 734 { 735 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT; 736 } 737 738 static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 739 { 740 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK; 741 } 742 743 static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p) 744 { 745 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT; 746 } 747 748 static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val) 749 { 750 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK; 751 } 752 753 static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p) 754 { 755 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 756 } 757 758 static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val) 759 { 760 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK; 761 } 762 763 static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p) 764 { 765 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK; 766 } 767 768 static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val) 769 { 770 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK; 771 } 772 773 static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p) 774 { 775 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT; 776 } 777 778 static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val) 779 { 780 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK; 781 } 782 783 static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p) 784 { 785 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT; 786 } 787 788 static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val) 789 { 790 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK; 791 } 792 793 static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p) 794 { 795 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT; 796 } 797 798 static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val) 799 { 800 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK; 801 } 802 803 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 804 { 805 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 806 } 807 808 static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 809 { 810 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK; 811 } 812 813 static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p) 814 { 815 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT; 816 } 817 818 static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 819 { 820 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK; 821 } 822 823 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p) 824 { 825 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT; 826 } 827 828 static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 829 { 830 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK; 831 } 832 833 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 834 { 835 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT; 836 } 837 838 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 839 { 840 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK; 841 } 842 843 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p) 844 { 845 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT; 846 } 847 848 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 849 { 850 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK; 851 } 852 853 static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p) 854 { 855 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT; 856 } 857 858 static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 859 { 860 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK; 861 } 862 863 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p) 864 { 865 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT; 866 } 867 868 static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 869 { 870 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK; 871 } 872 873 static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p) 874 { 875 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT; 876 } 877 878 static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 879 { 880 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK; 881 } 882 883 static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p) 884 { 885 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT; 886 } 887 888 static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 889 { 890 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK; 891 } 892 893 static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p) 894 { 895 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT; 896 } 897 898 static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 899 { 900 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK; 901 } 902 903 static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p) 904 { 905 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT; 906 } 907 908 static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 909 { 910 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK; 911 } 912 913 static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p) 914 { 915 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT; 916 } 917 918 static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val) 919 { 920 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK; 921 } 922 923 static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p) 924 { 925 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 926 } 927 928 static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 929 { 930 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 931 } 932 933 static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p) 934 { 935 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT; 936 } 937 938 static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val) 939 { 940 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 941 } 942 943 static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p) 944 { 945 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT; 946 } 947 948 static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val) 949 { 950 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 951 } 952 953 static inline uint32_t get_ena_eth_io_intr_reg_no_moderation_update(const struct ena_eth_io_intr_reg *p) 954 { 955 return (p->intr_control & ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK) >> ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT; 956 } 957 958 static inline void set_ena_eth_io_intr_reg_no_moderation_update(struct ena_eth_io_intr_reg *p, uint32_t val) 959 { 960 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_SHIFT) & ENA_ETH_IO_INTR_REG_NO_MODERATION_UPDATE_MASK; 961 } 962 963 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p) 964 { 965 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 966 } 967 968 static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 969 { 970 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK; 971 } 972 973 static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p) 974 { 975 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT; 976 } 977 978 static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val) 979 { 980 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK; 981 } 982 983 #endif /* !defined(DEFS_LINUX_MAINLINE) */ 984 #endif /* _ENA_ETH_IO_H_ */ 985