1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2015-2021 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _ENA_ADMIN_H_ 34 #define _ENA_ADMIN_H_ 35 36 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 37 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 38 39 #define ENA_ADMIN_RSS_KEY_PARTS 10 40 41 enum ena_admin_aq_opcode { 42 ENA_ADMIN_CREATE_SQ = 1, 43 ENA_ADMIN_DESTROY_SQ = 2, 44 ENA_ADMIN_CREATE_CQ = 3, 45 ENA_ADMIN_DESTROY_CQ = 4, 46 ENA_ADMIN_GET_FEATURE = 8, 47 ENA_ADMIN_SET_FEATURE = 9, 48 ENA_ADMIN_GET_STATS = 11, 49 }; 50 51 enum ena_admin_aq_completion_status { 52 ENA_ADMIN_SUCCESS = 0, 53 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 54 ENA_ADMIN_BAD_OPCODE = 2, 55 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 56 ENA_ADMIN_MALFORMED_REQUEST = 4, 57 /* Additional status is provided in ACQ entry extended_status */ 58 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 59 ENA_ADMIN_UNKNOWN_ERROR = 6, 60 ENA_ADMIN_RESOURCE_BUSY = 7, 61 }; 62 63 /* subcommands for the set/get feature admin commands */ 64 enum ena_admin_aq_feature_id { 65 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 66 ENA_ADMIN_MAX_QUEUES_NUM = 2, 67 ENA_ADMIN_HW_HINTS = 3, 68 ENA_ADMIN_LLQ = 4, 69 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5, 70 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6, 71 ENA_ADMIN_MAX_QUEUES_EXT = 7, 72 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 73 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 74 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, 75 ENA_ADMIN_MTU = 14, 76 ENA_ADMIN_RSS_HASH_INPUT = 18, 77 ENA_ADMIN_INTERRUPT_MODERATION = 20, 78 ENA_ADMIN_AENQ_CONFIG = 26, 79 ENA_ADMIN_LINK_CONFIG = 27, 80 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 81 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 82 }; 83 84 enum ena_admin_placement_policy_type { 85 /* descriptors and headers are in host memory */ 86 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 87 /* descriptors and headers are in device memory (a.k.a Low Latency 88 * Queue) 89 */ 90 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 91 }; 92 93 enum ena_admin_link_types { 94 ENA_ADMIN_LINK_SPEED_1G = 0x1, 95 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 96 ENA_ADMIN_LINK_SPEED_5G = 0x4, 97 ENA_ADMIN_LINK_SPEED_10G = 0x8, 98 ENA_ADMIN_LINK_SPEED_25G = 0x10, 99 ENA_ADMIN_LINK_SPEED_40G = 0x20, 100 ENA_ADMIN_LINK_SPEED_50G = 0x40, 101 ENA_ADMIN_LINK_SPEED_100G = 0x80, 102 ENA_ADMIN_LINK_SPEED_200G = 0x100, 103 ENA_ADMIN_LINK_SPEED_400G = 0x200, 104 }; 105 106 enum ena_admin_completion_policy_type { 107 /* completion queue entry for each sq descriptor */ 108 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 109 /* completion queue entry upon request in sq descriptor */ 110 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 111 /* current queue head pointer is updated in OS memory upon sq 112 * descriptor request 113 */ 114 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 115 /* current queue head pointer is updated in OS memory for each sq 116 * descriptor 117 */ 118 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 119 }; 120 121 /* basic stats return ena_admin_basic_stats while extanded stats return a 122 * buffer (string format) with additional statistics per queue and per 123 * device id 124 */ 125 enum ena_admin_get_stats_type { 126 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 127 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 128 /* extra HW stats for specific network interface */ 129 ENA_ADMIN_GET_STATS_TYPE_ENI = 2, 130 }; 131 132 enum ena_admin_get_stats_scope { 133 ENA_ADMIN_SPECIFIC_QUEUE = 0, 134 ENA_ADMIN_ETH_TRAFFIC = 1, 135 }; 136 137 struct ena_admin_aq_common_desc { 138 /* 11:0 : command_id 139 * 15:12 : reserved12 140 */ 141 uint16_t command_id; 142 143 /* as appears in ena_admin_aq_opcode */ 144 uint8_t opcode; 145 146 /* 0 : phase 147 * 1 : ctrl_data - control buffer address valid 148 * 2 : ctrl_data_indirect - control buffer address 149 * points to list of pages with addresses of control 150 * buffers 151 * 7:3 : reserved3 152 */ 153 uint8_t flags; 154 }; 155 156 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 157 * page list chunk. Used also at the end of indirect mode page list chunks, 158 * for chaining. 159 */ 160 struct ena_admin_ctrl_buff_info { 161 uint32_t length; 162 163 struct ena_common_mem_addr address; 164 }; 165 166 struct ena_admin_sq { 167 uint16_t sq_idx; 168 169 /* 4:0 : reserved 170 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 171 */ 172 uint8_t sq_identity; 173 174 uint8_t reserved1; 175 }; 176 177 struct ena_admin_aq_entry { 178 struct ena_admin_aq_common_desc aq_common_descriptor; 179 180 union { 181 uint32_t inline_data_w1[3]; 182 183 struct ena_admin_ctrl_buff_info control_buffer; 184 } u; 185 186 uint32_t inline_data_w4[12]; 187 }; 188 189 struct ena_admin_acq_common_desc { 190 /* command identifier to associate it with the aq descriptor 191 * 11:0 : command_id 192 * 15:12 : reserved12 193 */ 194 uint16_t command; 195 196 uint8_t status; 197 198 /* 0 : phase 199 * 7:1 : reserved1 200 */ 201 uint8_t flags; 202 203 uint16_t extended_status; 204 205 /* indicates to the driver which AQ entry has been consumed by the 206 * device and could be reused 207 */ 208 uint16_t sq_head_indx; 209 }; 210 211 struct ena_admin_acq_entry { 212 struct ena_admin_acq_common_desc acq_common_descriptor; 213 214 uint32_t response_specific_data[14]; 215 }; 216 217 struct ena_admin_aq_create_sq_cmd { 218 struct ena_admin_aq_common_desc aq_common_descriptor; 219 220 /* 4:0 : reserved0_w1 221 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 222 */ 223 uint8_t sq_identity; 224 225 uint8_t reserved8_w1; 226 227 /* 3:0 : placement_policy - Describing where the SQ 228 * descriptor ring and the SQ packet headers reside: 229 * 0x1 - descriptors and headers are in OS memory, 230 * 0x3 - descriptors and headers in device memory 231 * (a.k.a Low Latency Queue) 232 * 6:4 : completion_policy - Describing what policy 233 * to use for generation completion entry (cqe) in 234 * the CQ associated with this SQ: 0x0 - cqe for each 235 * sq descriptor, 0x1 - cqe upon request in sq 236 * descriptor, 0x2 - current queue head pointer is 237 * updated in OS memory upon sq descriptor request 238 * 0x3 - current queue head pointer is updated in OS 239 * memory for each sq descriptor 240 * 7 : reserved15_w1 241 */ 242 uint8_t sq_caps_2; 243 244 /* 0 : is_physically_contiguous - Described if the 245 * queue ring memory is allocated in physical 246 * contiguous pages or split. 247 * 7:1 : reserved17_w1 248 */ 249 uint8_t sq_caps_3; 250 251 /* associated completion queue id. This CQ must be created prior to SQ 252 * creation 253 */ 254 uint16_t cq_idx; 255 256 /* submission queue depth in entries */ 257 uint16_t sq_depth; 258 259 /* SQ physical base address in OS memory. This field should not be 260 * used for Low Latency queues. Has to be page aligned. 261 */ 262 struct ena_common_mem_addr sq_ba; 263 264 /* specifies queue head writeback location in OS memory. Valid if 265 * completion_policy is set to completion_policy_head_on_demand or 266 * completion_policy_head. Has to be cache aligned 267 */ 268 struct ena_common_mem_addr sq_head_writeback; 269 270 uint32_t reserved0_w7; 271 272 uint32_t reserved0_w8; 273 }; 274 275 enum ena_admin_sq_direction { 276 ENA_ADMIN_SQ_DIRECTION_TX = 1, 277 ENA_ADMIN_SQ_DIRECTION_RX = 2, 278 }; 279 280 struct ena_admin_acq_create_sq_resp_desc { 281 struct ena_admin_acq_common_desc acq_common_desc; 282 283 uint16_t sq_idx; 284 285 uint16_t reserved; 286 287 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 288 uint32_t sq_doorbell_offset; 289 290 /* low latency queue ring base address as an offset to PCIe MMIO 291 * LLQ_MEM BAR 292 */ 293 uint32_t llq_descriptors_offset; 294 295 /* low latency queue headers' memory as an offset to PCIe MMIO 296 * LLQ_MEM BAR 297 */ 298 uint32_t llq_headers_offset; 299 }; 300 301 struct ena_admin_aq_destroy_sq_cmd { 302 struct ena_admin_aq_common_desc aq_common_descriptor; 303 304 struct ena_admin_sq sq; 305 }; 306 307 struct ena_admin_acq_destroy_sq_resp_desc { 308 struct ena_admin_acq_common_desc acq_common_desc; 309 }; 310 311 struct ena_admin_aq_create_cq_cmd { 312 struct ena_admin_aq_common_desc aq_common_descriptor; 313 314 /* 4:0 : reserved5 315 * 5 : interrupt_mode_enabled - if set, cq operates 316 * in interrupt mode, otherwise - polling 317 * 7:6 : reserved6 318 */ 319 uint8_t cq_caps_1; 320 321 /* 4:0 : cq_entry_size_words - size of CQ entry in 322 * 32-bit words, valid values: 4, 8. 323 * 7:5 : reserved7 324 */ 325 uint8_t cq_caps_2; 326 327 /* completion queue depth in # of entries. must be power of 2 */ 328 uint16_t cq_depth; 329 330 /* msix vector assigned to this cq */ 331 uint32_t msix_vector; 332 333 /* cq physical base address in OS memory. CQ must be physically 334 * contiguous 335 */ 336 struct ena_common_mem_addr cq_ba; 337 }; 338 339 struct ena_admin_acq_create_cq_resp_desc { 340 struct ena_admin_acq_common_desc acq_common_desc; 341 342 uint16_t cq_idx; 343 344 /* actual cq depth in number of entries */ 345 uint16_t cq_actual_depth; 346 347 uint32_t numa_node_register_offset; 348 349 uint32_t cq_head_db_register_offset; 350 351 uint32_t cq_interrupt_unmask_register_offset; 352 }; 353 354 struct ena_admin_aq_destroy_cq_cmd { 355 struct ena_admin_aq_common_desc aq_common_descriptor; 356 357 uint16_t cq_idx; 358 359 uint16_t reserved1; 360 }; 361 362 struct ena_admin_acq_destroy_cq_resp_desc { 363 struct ena_admin_acq_common_desc acq_common_desc; 364 }; 365 366 /* ENA AQ Get Statistics command. Extended statistics are placed in control 367 * buffer pointed by AQ entry 368 */ 369 struct ena_admin_aq_get_stats_cmd { 370 struct ena_admin_aq_common_desc aq_common_descriptor; 371 372 union { 373 /* command specific inline data */ 374 uint32_t inline_data_w1[3]; 375 376 struct ena_admin_ctrl_buff_info control_buffer; 377 } u; 378 379 /* stats type as defined in enum ena_admin_get_stats_type */ 380 uint8_t type; 381 382 /* stats scope defined in enum ena_admin_get_stats_scope */ 383 uint8_t scope; 384 385 uint16_t reserved3; 386 387 /* queue id. used when scope is specific_queue */ 388 uint16_t queue_idx; 389 390 /* device id, value 0xFFFF means mine. only privileged device can get 391 * stats of other device 392 */ 393 uint16_t device_id; 394 }; 395 396 /* Basic Statistics Command. */ 397 struct ena_admin_basic_stats { 398 uint32_t tx_bytes_low; 399 400 uint32_t tx_bytes_high; 401 402 uint32_t tx_pkts_low; 403 404 uint32_t tx_pkts_high; 405 406 uint32_t rx_bytes_low; 407 408 uint32_t rx_bytes_high; 409 410 uint32_t rx_pkts_low; 411 412 uint32_t rx_pkts_high; 413 414 uint32_t rx_drops_low; 415 416 uint32_t rx_drops_high; 417 418 uint32_t tx_drops_low; 419 420 uint32_t tx_drops_high; 421 }; 422 423 /* ENI Statistics Command. */ 424 struct ena_admin_eni_stats { 425 /* The number of packets shaped due to inbound aggregate BW 426 * allowance being exceeded 427 */ 428 uint64_t bw_in_allowance_exceeded; 429 430 /* The number of packets shaped due to outbound aggregate BW 431 * allowance being exceeded 432 */ 433 uint64_t bw_out_allowance_exceeded; 434 435 /* The number of packets shaped due to PPS allowance being exceeded */ 436 uint64_t pps_allowance_exceeded; 437 438 /* The number of packets shaped due to connection tracking 439 * allowance being exceeded and leading to failure in establishment 440 * of new connections 441 */ 442 uint64_t conntrack_allowance_exceeded; 443 444 /* The number of packets shaped due to linklocal packet rate 445 * allowance being exceeded 446 */ 447 uint64_t linklocal_allowance_exceeded; 448 }; 449 450 struct ena_admin_acq_get_stats_resp { 451 struct ena_admin_acq_common_desc acq_common_desc; 452 453 union { 454 uint64_t raw[7]; 455 456 struct ena_admin_basic_stats basic_stats; 457 458 struct ena_admin_eni_stats eni_stats; 459 } u; 460 }; 461 462 struct ena_admin_get_set_feature_common_desc { 463 /* 1:0 : select - 0x1 - current value; 0x3 - default 464 * value 465 * 7:3 : reserved3 466 */ 467 uint8_t flags; 468 469 /* as appears in ena_admin_aq_feature_id */ 470 uint8_t feature_id; 471 472 /* The driver specifies the max feature version it supports and the 473 * device responds with the currently supported feature version. The 474 * field is zero based 475 */ 476 uint8_t feature_version; 477 478 uint8_t reserved8; 479 }; 480 481 struct ena_admin_device_attr_feature_desc { 482 uint32_t impl_id; 483 484 uint32_t device_version; 485 486 /* bitmap of ena_admin_aq_feature_id, which represents supported 487 * subcommands for the set/get feature admin commands. 488 */ 489 uint32_t supported_features; 490 491 uint32_t reserved3; 492 493 /* Indicates how many bits are used physical address access. */ 494 uint32_t phys_addr_width; 495 496 /* Indicates how many bits are used virtual address access. */ 497 uint32_t virt_addr_width; 498 499 /* unicast MAC address (in Network byte order) */ 500 uint8_t mac_addr[6]; 501 502 uint8_t reserved7[2]; 503 504 uint32_t max_mtu; 505 }; 506 507 enum ena_admin_llq_header_location { 508 /* header is in descriptor list */ 509 ENA_ADMIN_INLINE_HEADER = 1, 510 /* header in a separate ring, implies 16B descriptor list entry */ 511 ENA_ADMIN_HEADER_RING = 2, 512 }; 513 514 enum ena_admin_llq_ring_entry_size { 515 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 516 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 517 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 518 }; 519 520 enum ena_admin_llq_num_descs_before_header { 521 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 522 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 523 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 524 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 525 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 526 }; 527 528 /* packet descriptor list entry always starts with one or more descriptors, 529 * followed by a header. The rest of the descriptors are located in the 530 * beginning of the subsequent entry. Stride refers to how the rest of the 531 * descriptors are placed. This field is relevant only for inline header 532 * mode 533 */ 534 enum ena_admin_llq_stride_ctrl { 535 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 536 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 537 }; 538 539 enum ena_admin_accel_mode_feat { 540 ENA_ADMIN_DISABLE_META_CACHING = 0, 541 ENA_ADMIN_LIMIT_TX_BURST = 1, 542 }; 543 544 struct ena_admin_accel_mode_get { 545 /* bit field of enum ena_admin_accel_mode_feat */ 546 uint16_t supported_flags; 547 548 /* maximum burst size between two doorbells. The size is in bytes */ 549 uint16_t max_tx_burst_size; 550 }; 551 552 struct ena_admin_accel_mode_set { 553 /* bit field of enum ena_admin_accel_mode_feat */ 554 uint16_t enabled_flags; 555 556 uint16_t reserved; 557 }; 558 559 struct ena_admin_accel_mode_req { 560 union { 561 uint32_t raw[2]; 562 563 struct ena_admin_accel_mode_get get; 564 565 struct ena_admin_accel_mode_set set; 566 } u; 567 }; 568 569 struct ena_admin_feature_llq_desc { 570 uint32_t max_llq_num; 571 572 uint32_t max_llq_depth; 573 574 /* specify the header locations the device supports. bitfield of enum 575 * ena_admin_llq_header_location. 576 */ 577 uint16_t header_location_ctrl_supported; 578 579 /* the header location the driver selected to use. */ 580 uint16_t header_location_ctrl_enabled; 581 582 /* if inline header is specified - this is the size of descriptor list 583 * entry. If header in a separate ring is specified - this is the size 584 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. 585 * specify the entry sizes the device supports 586 */ 587 uint16_t entry_size_ctrl_supported; 588 589 /* the entry size the driver selected to use. */ 590 uint16_t entry_size_ctrl_enabled; 591 592 /* valid only if inline header is specified. First entry associated with 593 * the packet includes descriptors and header. Rest of the entries 594 * occupied by descriptors. This parameter defines the max number of 595 * descriptors precedding the header in the first entry. The field is 596 * bitfield of enum ena_admin_llq_num_descs_before_header and specify 597 * the values the device supports 598 */ 599 uint16_t desc_num_before_header_supported; 600 601 /* the desire field the driver selected to use */ 602 uint16_t desc_num_before_header_enabled; 603 604 /* valid only if inline was chosen. bitfield of enum 605 * ena_admin_llq_stride_ctrl 606 */ 607 uint16_t descriptors_stride_ctrl_supported; 608 609 /* the stride control the driver selected to use */ 610 uint16_t descriptors_stride_ctrl_enabled; 611 612 /* reserved */ 613 uint32_t reserved1; 614 615 /* accelerated low latency queues requirement. driver needs to 616 * support those requirements in order to use accelerated llq 617 */ 618 struct ena_admin_accel_mode_req accel_mode; 619 }; 620 621 struct ena_admin_queue_ext_feature_fields { 622 uint32_t max_tx_sq_num; 623 624 uint32_t max_tx_cq_num; 625 626 uint32_t max_rx_sq_num; 627 628 uint32_t max_rx_cq_num; 629 630 uint32_t max_tx_sq_depth; 631 632 uint32_t max_tx_cq_depth; 633 634 uint32_t max_rx_sq_depth; 635 636 uint32_t max_rx_cq_depth; 637 638 uint32_t max_tx_header_size; 639 640 /* Maximum Descriptors number, including meta descriptor, allowed for a 641 * single Tx packet 642 */ 643 uint16_t max_per_packet_tx_descs; 644 645 /* Maximum Descriptors number allowed for a single Rx packet */ 646 uint16_t max_per_packet_rx_descs; 647 }; 648 649 struct ena_admin_queue_feature_desc { 650 uint32_t max_sq_num; 651 652 uint32_t max_sq_depth; 653 654 uint32_t max_cq_num; 655 656 uint32_t max_cq_depth; 657 658 uint32_t max_legacy_llq_num; 659 660 uint32_t max_legacy_llq_depth; 661 662 uint32_t max_header_size; 663 664 /* Maximum Descriptors number, including meta descriptor, allowed for a 665 * single Tx packet 666 */ 667 uint16_t max_packet_tx_descs; 668 669 /* Maximum Descriptors number allowed for a single Rx packet */ 670 uint16_t max_packet_rx_descs; 671 }; 672 673 struct ena_admin_set_feature_mtu_desc { 674 /* exclude L2 */ 675 uint32_t mtu; 676 }; 677 678 struct ena_admin_get_extra_properties_strings_desc { 679 uint32_t count; 680 }; 681 682 struct ena_admin_get_extra_properties_flags_desc { 683 uint32_t flags; 684 }; 685 686 struct ena_admin_set_feature_host_attr_desc { 687 /* host OS info base address in OS memory. host info is 4KB of 688 * physically contiguous 689 */ 690 struct ena_common_mem_addr os_info_ba; 691 692 /* host debug area base address in OS memory. debug area must be 693 * physically contiguous 694 */ 695 struct ena_common_mem_addr debug_ba; 696 697 /* debug area size */ 698 uint32_t debug_area_size; 699 }; 700 701 struct ena_admin_feature_intr_moder_desc { 702 /* interrupt delay granularity in usec */ 703 uint16_t intr_delay_resolution; 704 705 uint16_t reserved; 706 }; 707 708 struct ena_admin_get_feature_link_desc { 709 /* Link speed in Mb */ 710 uint32_t speed; 711 712 /* bit field of enum ena_admin_link types */ 713 uint32_t supported; 714 715 /* 0 : autoneg 716 * 1 : duplex - Full Duplex 717 * 31:2 : reserved2 718 */ 719 uint32_t flags; 720 }; 721 722 struct ena_admin_feature_aenq_desc { 723 /* bitmask for AENQ groups the device can report */ 724 uint32_t supported_groups; 725 726 /* bitmask for AENQ groups to report */ 727 uint32_t enabled_groups; 728 }; 729 730 struct ena_admin_feature_offload_desc { 731 /* 0 : TX_L3_csum_ipv4 732 * 1 : TX_L4_ipv4_csum_part - The checksum field 733 * should be initialized with pseudo header checksum 734 * 2 : TX_L4_ipv4_csum_full 735 * 3 : TX_L4_ipv6_csum_part - The checksum field 736 * should be initialized with pseudo header checksum 737 * 4 : TX_L4_ipv6_csum_full 738 * 5 : tso_ipv4 739 * 6 : tso_ipv6 740 * 7 : tso_ecn 741 */ 742 uint32_t tx; 743 744 /* Receive side supported stateless offload 745 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 746 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 747 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 748 * 3 : RX_hash - Hash calculation 749 */ 750 uint32_t rx_supported; 751 752 uint32_t rx_enabled; 753 }; 754 755 enum ena_admin_hash_functions { 756 ENA_ADMIN_TOEPLITZ = 1, 757 ENA_ADMIN_CRC32 = 2, 758 }; 759 760 struct ena_admin_feature_rss_flow_hash_control { 761 uint32_t key_parts; 762 763 uint32_t reserved; 764 765 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS]; 766 }; 767 768 struct ena_admin_feature_rss_flow_hash_function { 769 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 770 uint32_t supported_func; 771 772 /* 7:0 : selected_func - bitmask of 773 * ena_admin_hash_functions 774 */ 775 uint32_t selected_func; 776 777 /* initial value */ 778 uint32_t init_val; 779 }; 780 781 /* RSS flow hash protocols */ 782 enum ena_admin_flow_hash_proto { 783 ENA_ADMIN_RSS_TCP4 = 0, 784 ENA_ADMIN_RSS_UDP4 = 1, 785 ENA_ADMIN_RSS_TCP6 = 2, 786 ENA_ADMIN_RSS_UDP6 = 3, 787 ENA_ADMIN_RSS_IP4 = 4, 788 ENA_ADMIN_RSS_IP6 = 5, 789 ENA_ADMIN_RSS_IP4_FRAG = 6, 790 ENA_ADMIN_RSS_NOT_IP = 7, 791 /* TCPv6 with extension header */ 792 ENA_ADMIN_RSS_TCP6_EX = 8, 793 /* IPv6 with extension header */ 794 ENA_ADMIN_RSS_IP6_EX = 9, 795 ENA_ADMIN_RSS_PROTO_NUM = 16, 796 }; 797 798 /* RSS flow hash fields */ 799 enum ena_admin_flow_hash_fields { 800 /* Ethernet Dest Addr */ 801 ENA_ADMIN_RSS_L2_DA = BIT(0), 802 /* Ethernet Src Addr */ 803 ENA_ADMIN_RSS_L2_SA = BIT(1), 804 /* ipv4/6 Dest Addr */ 805 ENA_ADMIN_RSS_L3_DA = BIT(2), 806 /* ipv4/6 Src Addr */ 807 ENA_ADMIN_RSS_L3_SA = BIT(3), 808 /* tcp/udp Dest Port */ 809 ENA_ADMIN_RSS_L4_DP = BIT(4), 810 /* tcp/udp Src Port */ 811 ENA_ADMIN_RSS_L4_SP = BIT(5), 812 }; 813 814 struct ena_admin_proto_input { 815 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 816 uint16_t fields; 817 818 uint16_t reserved2; 819 }; 820 821 struct ena_admin_feature_rss_hash_control { 822 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 823 824 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 825 826 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 827 828 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 829 }; 830 831 struct ena_admin_feature_rss_flow_hash_input { 832 /* supported hash input sorting 833 * 1 : L3_sort - support swap L3 addresses if DA is 834 * smaller than SA 835 * 2 : L4_sort - support swap L4 ports if DP smaller 836 * SP 837 */ 838 uint16_t supported_input_sort; 839 840 /* enabled hash input sorting 841 * 1 : enable_L3_sort - enable swap L3 addresses if 842 * DA smaller than SA 843 * 2 : enable_L4_sort - enable swap L4 ports if DP 844 * smaller than SP 845 */ 846 uint16_t enabled_input_sort; 847 }; 848 849 enum ena_admin_os_type { 850 ENA_ADMIN_OS_LINUX = 1, 851 ENA_ADMIN_OS_WIN = 2, 852 ENA_ADMIN_OS_DPDK = 3, 853 ENA_ADMIN_OS_FREEBSD = 4, 854 ENA_ADMIN_OS_IPXE = 5, 855 ENA_ADMIN_OS_ESXI = 6, 856 ENA_ADMIN_OS_MACOS = 7, 857 ENA_ADMIN_OS_GROUPS_NUM = 7, 858 }; 859 860 struct ena_admin_host_info { 861 /* defined in enum ena_admin_os_type */ 862 uint32_t os_type; 863 864 /* os distribution string format */ 865 uint8_t os_dist_str[128]; 866 867 /* OS distribution numeric format */ 868 uint32_t os_dist; 869 870 /* kernel version string format */ 871 uint8_t kernel_ver_str[32]; 872 873 /* Kernel version numeric format */ 874 uint32_t kernel_ver; 875 876 /* 7:0 : major 877 * 15:8 : minor 878 * 23:16 : sub_minor 879 * 31:24 : module_type 880 */ 881 uint32_t driver_version; 882 883 /* features bitmap */ 884 uint32_t supported_network_features[2]; 885 886 /* ENA spec version of driver */ 887 uint16_t ena_spec_version; 888 889 /* ENA device's Bus, Device and Function 890 * 2:0 : function 891 * 7:3 : device 892 * 15:8 : bus 893 */ 894 uint16_t bdf; 895 896 /* Number of CPUs */ 897 uint16_t num_cpus; 898 899 uint16_t reserved; 900 901 /* 0 : reserved 902 * 1 : rx_offset 903 * 2 : interrupt_moderation 904 * 3 : rx_buf_mirroring 905 * 4 : rss_configurable_function_key 906 * 5 : reserved 907 * 6 : rx_page_reuse 908 * 31:7 : reserved 909 */ 910 uint32_t driver_supported_features; 911 }; 912 913 struct ena_admin_rss_ind_table_entry { 914 uint16_t cq_idx; 915 916 uint16_t reserved; 917 }; 918 919 struct ena_admin_feature_rss_ind_table { 920 /* min supported table size (2^min_size) */ 921 uint16_t min_size; 922 923 /* max supported table size (2^max_size) */ 924 uint16_t max_size; 925 926 /* table size (2^size) */ 927 uint16_t size; 928 929 /* 0 : one_entry_update - The ENA device supports 930 * setting a single RSS table entry 931 */ 932 uint8_t flags; 933 934 uint8_t reserved; 935 936 /* index of the inline entry. 0xFFFFFFFF means invalid */ 937 uint32_t inline_index; 938 939 /* used for updating single entry, ignored when setting the entire 940 * table through the control buffer. 941 */ 942 struct ena_admin_rss_ind_table_entry inline_entry; 943 }; 944 945 /* When hint value is 0, driver should use it's own predefined value */ 946 struct ena_admin_ena_hw_hints { 947 /* value in ms */ 948 uint16_t mmio_read_timeout; 949 950 /* value in ms */ 951 uint16_t driver_watchdog_timeout; 952 953 /* Per packet tx completion timeout. value in ms */ 954 uint16_t missing_tx_completion_timeout; 955 956 uint16_t missed_tx_completion_count_threshold_to_reset; 957 958 /* value in ms */ 959 uint16_t admin_completion_tx_timeout; 960 961 uint16_t netdev_wd_timeout; 962 963 uint16_t max_tx_sgl_size; 964 965 uint16_t max_rx_sgl_size; 966 967 uint16_t reserved[8]; 968 }; 969 970 struct ena_admin_get_feat_cmd { 971 struct ena_admin_aq_common_desc aq_common_descriptor; 972 973 struct ena_admin_ctrl_buff_info control_buffer; 974 975 struct ena_admin_get_set_feature_common_desc feat_common; 976 977 uint32_t raw[11]; 978 }; 979 980 struct ena_admin_queue_ext_feature_desc { 981 /* version */ 982 uint8_t version; 983 984 uint8_t reserved1[3]; 985 986 union { 987 struct ena_admin_queue_ext_feature_fields max_queue_ext; 988 989 uint32_t raw[10]; 990 }; 991 }; 992 993 struct ena_admin_get_feat_resp { 994 struct ena_admin_acq_common_desc acq_common_desc; 995 996 union { 997 uint32_t raw[14]; 998 999 struct ena_admin_device_attr_feature_desc dev_attr; 1000 1001 struct ena_admin_feature_llq_desc llq; 1002 1003 struct ena_admin_queue_feature_desc max_queue; 1004 1005 struct ena_admin_queue_ext_feature_desc max_queue_ext; 1006 1007 struct ena_admin_feature_aenq_desc aenq; 1008 1009 struct ena_admin_get_feature_link_desc link; 1010 1011 struct ena_admin_feature_offload_desc offload; 1012 1013 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1014 1015 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1016 1017 struct ena_admin_feature_rss_ind_table ind_table; 1018 1019 struct ena_admin_feature_intr_moder_desc intr_moderation; 1020 1021 struct ena_admin_ena_hw_hints hw_hints; 1022 1023 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings; 1024 1025 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags; 1026 } u; 1027 }; 1028 1029 struct ena_admin_set_feat_cmd { 1030 struct ena_admin_aq_common_desc aq_common_descriptor; 1031 1032 struct ena_admin_ctrl_buff_info control_buffer; 1033 1034 struct ena_admin_get_set_feature_common_desc feat_common; 1035 1036 union { 1037 uint32_t raw[11]; 1038 1039 /* mtu size */ 1040 struct ena_admin_set_feature_mtu_desc mtu; 1041 1042 /* host attributes */ 1043 struct ena_admin_set_feature_host_attr_desc host_attr; 1044 1045 /* AENQ configuration */ 1046 struct ena_admin_feature_aenq_desc aenq; 1047 1048 /* rss flow hash function */ 1049 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1050 1051 /* rss flow hash input */ 1052 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1053 1054 /* rss indirection table */ 1055 struct ena_admin_feature_rss_ind_table ind_table; 1056 1057 /* LLQ configuration */ 1058 struct ena_admin_feature_llq_desc llq; 1059 } u; 1060 }; 1061 1062 struct ena_admin_set_feat_resp { 1063 struct ena_admin_acq_common_desc acq_common_desc; 1064 1065 union { 1066 uint32_t raw[14]; 1067 } u; 1068 }; 1069 1070 struct ena_admin_aenq_common_desc { 1071 uint16_t group; 1072 1073 uint16_t syndrome; 1074 1075 /* 0 : phase 1076 * 7:1 : reserved - MBZ 1077 */ 1078 uint8_t flags; 1079 1080 uint8_t reserved1[3]; 1081 1082 uint32_t timestamp_low; 1083 1084 uint32_t timestamp_high; 1085 }; 1086 1087 /* asynchronous event notification groups */ 1088 enum ena_admin_aenq_group { 1089 ENA_ADMIN_LINK_CHANGE = 0, 1090 ENA_ADMIN_FATAL_ERROR = 1, 1091 ENA_ADMIN_WARNING = 2, 1092 ENA_ADMIN_NOTIFICATION = 3, 1093 ENA_ADMIN_KEEP_ALIVE = 4, 1094 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1095 }; 1096 1097 enum ena_admin_aenq_notification_syndrome { 1098 ENA_ADMIN_UPDATE_HINTS = 2, 1099 }; 1100 1101 struct ena_admin_aenq_entry { 1102 struct ena_admin_aenq_common_desc aenq_common_desc; 1103 1104 /* command specific inline data */ 1105 uint32_t inline_data_w4[12]; 1106 }; 1107 1108 struct ena_admin_aenq_link_change_desc { 1109 struct ena_admin_aenq_common_desc aenq_common_desc; 1110 1111 /* 0 : link_status */ 1112 uint32_t flags; 1113 }; 1114 1115 struct ena_admin_aenq_keep_alive_desc { 1116 struct ena_admin_aenq_common_desc aenq_common_desc; 1117 1118 uint32_t rx_drops_low; 1119 1120 uint32_t rx_drops_high; 1121 1122 uint32_t tx_drops_low; 1123 1124 uint32_t tx_drops_high; 1125 }; 1126 1127 struct ena_admin_ena_mmio_req_read_less_resp { 1128 uint16_t req_id; 1129 1130 uint16_t reg_off; 1131 1132 /* value is valid when poll is cleared */ 1133 uint32_t reg_val; 1134 }; 1135 1136 /* aq_common_desc */ 1137 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1138 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1139 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1140 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1141 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1142 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1143 1144 /* sq */ 1145 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1146 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1147 1148 /* acq_common_desc */ 1149 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1150 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1151 1152 /* aq_create_sq_cmd */ 1153 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1154 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1155 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1156 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1157 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1158 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1159 1160 /* aq_create_cq_cmd */ 1161 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1162 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1163 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1164 1165 /* get_set_feature_common_desc */ 1166 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1167 1168 /* get_feature_link_desc */ 1169 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1170 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1171 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1172 1173 /* feature_offload_desc */ 1174 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1175 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1176 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1177 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1178 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1179 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1180 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1181 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1182 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1183 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1184 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1185 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1186 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1187 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1188 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1189 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1190 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1191 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1192 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1193 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1194 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1195 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1196 1197 /* feature_rss_flow_hash_function */ 1198 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1199 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1200 1201 /* feature_rss_flow_hash_input */ 1202 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1203 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1204 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1205 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1206 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1207 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1208 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1209 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1210 1211 /* host_info */ 1212 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1213 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1214 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1215 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1216 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1217 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1218 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1219 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1220 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1221 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1222 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1223 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1224 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1225 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1226 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1227 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1228 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1229 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1230 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1231 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1232 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 1233 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) 1234 1235 /* feature_rss_ind_table */ 1236 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0) 1237 1238 /* aenq_common_desc */ 1239 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1240 1241 /* aenq_link_change_desc */ 1242 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1243 1244 #if !defined(DEFS_LINUX_MAINLINE) 1245 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p) 1246 { 1247 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1248 } 1249 1250 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val) 1251 { 1252 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1253 } 1254 1255 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p) 1256 { 1257 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1258 } 1259 1260 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val) 1261 { 1262 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1263 } 1264 1265 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p) 1266 { 1267 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT; 1268 } 1269 1270 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val) 1271 { 1272 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK; 1273 } 1274 1275 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p) 1276 { 1277 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT; 1278 } 1279 1280 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val) 1281 { 1282 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1283 } 1284 1285 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p) 1286 { 1287 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT; 1288 } 1289 1290 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val) 1291 { 1292 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 1293 } 1294 1295 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p) 1296 { 1297 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1298 } 1299 1300 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val) 1301 { 1302 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1303 } 1304 1305 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p) 1306 { 1307 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1308 } 1309 1310 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val) 1311 { 1312 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1313 } 1314 1315 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p) 1316 { 1317 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT; 1318 } 1319 1320 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1321 { 1322 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1323 } 1324 1325 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p) 1326 { 1327 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1328 } 1329 1330 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1331 { 1332 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1333 } 1334 1335 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p) 1336 { 1337 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT; 1338 } 1339 1340 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1341 { 1342 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1343 } 1344 1345 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p) 1346 { 1347 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1348 } 1349 1350 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1351 { 1352 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1353 } 1354 1355 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p) 1356 { 1357 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT; 1358 } 1359 1360 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1361 { 1362 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1363 } 1364 1365 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p) 1366 { 1367 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1368 } 1369 1370 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1371 { 1372 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1373 } 1374 1375 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p) 1376 { 1377 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1378 } 1379 1380 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val) 1381 { 1382 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1383 } 1384 1385 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p) 1386 { 1387 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1388 } 1389 1390 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1391 { 1392 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1393 } 1394 1395 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p) 1396 { 1397 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT; 1398 } 1399 1400 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1401 { 1402 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK; 1403 } 1404 1405 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1406 { 1407 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1408 } 1409 1410 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1411 { 1412 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1413 } 1414 1415 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p) 1416 { 1417 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT; 1418 } 1419 1420 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1421 { 1422 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK; 1423 } 1424 1425 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p) 1426 { 1427 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT; 1428 } 1429 1430 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1431 { 1432 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK; 1433 } 1434 1435 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p) 1436 { 1437 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT; 1438 } 1439 1440 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1441 { 1442 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK; 1443 } 1444 1445 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p) 1446 { 1447 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT; 1448 } 1449 1450 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1451 { 1452 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK; 1453 } 1454 1455 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p) 1456 { 1457 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT; 1458 } 1459 1460 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1461 { 1462 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1463 } 1464 1465 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p) 1466 { 1467 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT; 1468 } 1469 1470 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val) 1471 { 1472 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK; 1473 } 1474 1475 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p) 1476 { 1477 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT; 1478 } 1479 1480 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val) 1481 { 1482 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK; 1483 } 1484 1485 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1486 { 1487 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1488 } 1489 1490 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1491 { 1492 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1493 } 1494 1495 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p) 1496 { 1497 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT; 1498 } 1499 1500 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1501 { 1502 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK; 1503 } 1504 1505 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p) 1506 { 1507 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT; 1508 } 1509 1510 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1511 { 1512 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK; 1513 } 1514 1515 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p) 1516 { 1517 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT; 1518 } 1519 1520 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val) 1521 { 1522 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK; 1523 } 1524 1525 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p) 1526 { 1527 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1528 } 1529 1530 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1531 { 1532 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1533 } 1534 1535 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p) 1536 { 1537 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1538 } 1539 1540 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1541 { 1542 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1543 } 1544 1545 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1546 { 1547 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT; 1548 } 1549 1550 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1551 { 1552 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK; 1553 } 1554 1555 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1556 { 1557 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT; 1558 } 1559 1560 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1561 { 1562 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 1563 } 1564 1565 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1566 { 1567 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT; 1568 } 1569 1570 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1571 { 1572 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK; 1573 } 1574 1575 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1576 { 1577 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT; 1578 } 1579 1580 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1581 { 1582 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK; 1583 } 1584 1585 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p) 1586 { 1587 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1588 } 1589 1590 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val) 1591 { 1592 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1593 } 1594 1595 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p) 1596 { 1597 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT; 1598 } 1599 1600 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val) 1601 { 1602 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK; 1603 } 1604 1605 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p) 1606 { 1607 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT; 1608 } 1609 1610 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val) 1611 { 1612 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK; 1613 } 1614 1615 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p) 1616 { 1617 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT; 1618 } 1619 1620 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val) 1621 { 1622 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK; 1623 } 1624 1625 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p) 1626 { 1627 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1628 } 1629 1630 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val) 1631 { 1632 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1633 } 1634 1635 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p) 1636 { 1637 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT; 1638 } 1639 1640 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val) 1641 { 1642 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK; 1643 } 1644 1645 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p) 1646 { 1647 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT; 1648 } 1649 1650 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val) 1651 { 1652 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK; 1653 } 1654 1655 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p) 1656 { 1657 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT; 1658 } 1659 1660 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val) 1661 { 1662 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 1663 } 1664 1665 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p) 1666 { 1667 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT; 1668 } 1669 1670 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val) 1671 { 1672 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK; 1673 } 1674 1675 static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p) 1676 { 1677 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT; 1678 } 1679 1680 static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val) 1681 { 1682 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK; 1683 } 1684 1685 static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p) 1686 { 1687 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT; 1688 } 1689 1690 static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val) 1691 { 1692 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK; 1693 } 1694 1695 static inline uint32_t get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info *p) 1696 { 1697 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK) >> ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT; 1698 } 1699 1700 static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info *p, uint32_t val) 1701 { 1702 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT) & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK; 1703 } 1704 1705 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p) 1706 { 1707 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1708 } 1709 1710 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val) 1711 { 1712 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1713 } 1714 1715 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p) 1716 { 1717 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1718 } 1719 1720 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val) 1721 { 1722 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1723 } 1724 1725 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p) 1726 { 1727 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1728 } 1729 1730 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val) 1731 { 1732 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1733 } 1734 1735 #endif /* !defined(DEFS_LINUX_MAINLINE) */ 1736 #endif /* _ENA_ADMIN_H_ */ 1737