1 /** @file 2 This header file contains all of the PXE type definitions, 3 structure prototypes, global variables and constants that 4 are needed for porting PXE to EFI. 5 6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 @par Revision Reference: 10 32/64-bit PXE specification: 11 alpha-4, 99-Dec-17. 12 13 **/ 14 15 #ifndef __EFI_PXE_H__ 16 #define __EFI_PXE_H__ 17 18 #pragma pack(1) 19 20 #define PXE_BUSTYPE(a, b, c, d) \ 21 ( \ 22 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \ 23 ((PXE_UINT32) (a) & 0xFF) \ 24 ) 25 26 /// 27 /// UNDI ROM ID and devive ID signature. 28 /// 29 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E') 30 31 /// 32 /// BUS ROM ID signatures. 33 /// 34 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R') 35 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R') 36 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R') 37 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4') 38 39 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8)) 40 41 #define PXE_SWAP_UINT32(n) \ 42 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \ 43 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \ 44 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \ 45 (((PXE_UINT32)(n) & 0xFF000000) >> 24)) 46 47 #define PXE_SWAP_UINT64(n) \ 48 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \ 49 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \ 50 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \ 51 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \ 52 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \ 53 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \ 54 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \ 55 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56)) 56 57 58 #define PXE_CPBSIZE_NOT_USED 0 ///< zero 59 #define PXE_DBSIZE_NOT_USED 0 ///< zero 60 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero 61 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero 62 #define PXE_CONST CONST 63 64 #define PXE_VOLATILE volatile 65 66 typedef VOID PXE_VOID; 67 typedef UINT8 PXE_UINT8; 68 typedef UINT16 PXE_UINT16; 69 typedef UINT32 PXE_UINT32; 70 typedef UINTN PXE_UINTN; 71 72 /// 73 /// Typedef unsigned long PXE_UINT64. 74 /// 75 typedef UINT64 PXE_UINT64; 76 77 typedef PXE_UINT8 PXE_BOOL; 78 #define PXE_FALSE 0 ///< zero 79 #define PXE_TRUE (!PXE_FALSE) 80 81 typedef PXE_UINT16 PXE_OPCODE; 82 83 /// 84 /// Return UNDI operational state. 85 /// 86 #define PXE_OPCODE_GET_STATE 0x0000 87 88 /// 89 /// Change UNDI operational state from Stopped to Started. 90 /// 91 #define PXE_OPCODE_START 0x0001 92 93 /// 94 /// Change UNDI operational state from Started to Stopped. 95 /// 96 #define PXE_OPCODE_STOP 0x0002 97 98 /// 99 /// Get UNDI initialization information. 100 /// 101 #define PXE_OPCODE_GET_INIT_INFO 0x0003 102 103 /// 104 /// Get NIC configuration information. 105 /// 106 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004 107 108 /// 109 /// Changed UNDI operational state from Started to Initialized. 110 /// 111 #define PXE_OPCODE_INITIALIZE 0x0005 112 113 /// 114 /// Re-initialize the NIC H/W. 115 /// 116 #define PXE_OPCODE_RESET 0x0006 117 118 /// 119 /// Change the UNDI operational state from Initialized to Started. 120 /// 121 #define PXE_OPCODE_SHUTDOWN 0x0007 122 123 /// 124 /// Read & change state of external interrupt enables. 125 /// 126 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008 127 128 /// 129 /// Read & change state of packet receive filters. 130 /// 131 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009 132 133 /// 134 /// Read & change station MAC address. 135 /// 136 #define PXE_OPCODE_STATION_ADDRESS 0x000A 137 138 /// 139 /// Read traffic statistics. 140 /// 141 #define PXE_OPCODE_STATISTICS 0x000B 142 143 /// 144 /// Convert multicast IP address to multicast MAC address. 145 /// 146 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C 147 148 /// 149 /// Read or change non-volatile storage on the NIC. 150 /// 151 #define PXE_OPCODE_NVDATA 0x000D 152 153 /// 154 /// Get & clear interrupt status. 155 /// 156 #define PXE_OPCODE_GET_STATUS 0x000E 157 158 /// 159 /// Fill media header in packet for transmit. 160 /// 161 #define PXE_OPCODE_FILL_HEADER 0x000F 162 163 /// 164 /// Transmit packet(s). 165 /// 166 #define PXE_OPCODE_TRANSMIT 0x0010 167 168 /// 169 /// Receive packet. 170 /// 171 #define PXE_OPCODE_RECEIVE 0x0011 172 173 /// 174 /// Last valid PXE UNDI OpCode number. 175 /// 176 #define PXE_OPCODE_LAST_VALID 0x0011 177 178 typedef PXE_UINT16 PXE_OPFLAGS; 179 180 #define PXE_OPFLAGS_NOT_USED 0x0000 181 182 // 183 // ////////////////////////////////////// 184 // UNDI Get State 185 // 186 // No OpFlags 187 188 //////////////////////////////////////// 189 // UNDI Start 190 // 191 // No OpFlags 192 193 //////////////////////////////////////// 194 // UNDI Stop 195 // 196 // No OpFlags 197 198 //////////////////////////////////////// 199 // UNDI Get Init Info 200 // 201 // No Opflags 202 203 //////////////////////////////////////// 204 // UNDI Get Config Info 205 // 206 // No Opflags 207 208 /// 209 /// UNDI Initialize 210 /// 211 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001 212 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000 213 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001 214 215 /// 216 /// 217 /// UNDI Reset 218 /// 219 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001 220 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002 221 222 /// 223 /// UNDI Shutdown. 224 /// 225 /// No OpFlags. 226 227 /// 228 /// UNDI Interrupt Enables. 229 /// 230 /// 231 /// Select whether to enable or disable external interrupt signals. 232 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS. 233 /// 234 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000 235 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000 236 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000 237 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000 238 239 /// 240 /// Enable receive interrupts. An external interrupt will be generated 241 /// after a complete non-error packet has been received. 242 /// 243 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001 244 245 /// 246 /// Enable transmit interrupts. An external interrupt will be generated 247 /// after a complete non-error packet has been transmitted. 248 /// 249 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002 250 251 /// 252 /// Enable command interrupts. An external interrupt will be generated 253 /// when command execution stops. 254 /// 255 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004 256 257 /// 258 /// Generate software interrupt. Setting this bit generates an external 259 /// interrupt, if it is supported by the hardware. 260 /// 261 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008 262 263 /// 264 /// UNDI Receive Filters. 265 /// 266 /// 267 /// Select whether to enable or disable receive filters. 268 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE. 269 /// 270 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000 271 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000 272 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000 273 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000 274 275 /// 276 /// To reset the contents of the multicast MAC address filter list, 277 /// set this OpFlag: 278 /// 279 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000 280 281 /// 282 /// Enable unicast packet receiving. Packets sent to the current station 283 /// MAC address will be received. 284 /// 285 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001 286 287 /// 288 /// Enable broadcast packet receiving. Packets sent to the broadcast 289 /// MAC address will be received. 290 /// 291 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 292 293 /// 294 /// Enable filtered multicast packet receiving. Packets sent to any 295 /// of the multicast MAC addresses in the multicast MAC address filter 296 /// list will be received. If the filter list is empty, no multicast 297 /// 298 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 299 300 /// 301 /// Enable promiscuous packet receiving. All packets will be received. 302 /// 303 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 304 305 /// 306 /// Enable promiscuous multicast packet receiving. All multicast 307 /// packets will be received. 308 /// 309 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 310 311 /// 312 /// UNDI Station Address. 313 /// 314 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000 315 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000 316 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001 317 318 /// 319 /// UNDI Statistics. 320 /// 321 #define PXE_OPFLAGS_STATISTICS_READ 0x0000 322 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001 323 324 /// 325 /// UNDI MCast IP to MAC. 326 /// 327 /// 328 /// Identify the type of IP address in the CPB. 329 /// 330 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003 331 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000 332 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001 333 334 /// 335 /// UNDI NvData. 336 /// 337 /// 338 /// Select the type of non-volatile data operation. 339 /// 340 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001 341 #define PXE_OPFLAGS_NVDATA_READ 0x0000 342 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001 343 344 /// 345 /// UNDI Get Status. 346 /// 347 /// 348 /// Return current interrupt status. This will also clear any interrupts 349 /// that are currently set. This can be used in a polling routine. The 350 /// interrupt flags are still set and cleared even when the interrupts 351 /// are disabled. 352 /// 353 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001 354 355 /// 356 /// Return list of transmitted buffers for recycling. Transmit buffers 357 /// must not be changed or unallocated until they have recycled. After 358 /// issuing a transmit command, wait for a transmit complete interrupt. 359 /// When a transmit complete interrupt is received, read the transmitted 360 /// buffers. Do not plan on getting one buffer per interrupt. Some 361 /// NICs and UNDIs may transmit multiple buffers per interrupt. 362 /// 363 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002 364 365 /// 366 /// Return current media status. 367 /// 368 #define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004 369 370 /// 371 /// UNDI Fill Header. 372 /// 373 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001 374 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001 375 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000 376 377 /// 378 /// UNDI Transmit. 379 /// 380 /// 381 /// S/W UNDI only. Return after the packet has been transmitted. A 382 /// transmit complete interrupt will still be generated and the transmit 383 /// buffer will have to be recycled. 384 /// 385 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001 386 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001 387 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000 388 389 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002 390 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002 391 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000 392 393 /// 394 /// UNDI Receive. 395 /// 396 /// No OpFlags. 397 /// 398 399 /// 400 /// PXE STATFLAGS. 401 /// 402 typedef PXE_UINT16 PXE_STATFLAGS; 403 404 #define PXE_STATFLAGS_INITIALIZE 0x0000 405 406 /// 407 /// Common StatFlags that can be returned by all commands. 408 /// 409 /// 410 /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be 411 /// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs 412 /// that support command queuing. 413 /// 414 #define PXE_STATFLAGS_STATUS_MASK 0xC000 415 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000 416 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000 417 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000 418 419 /// 420 /// UNDI Get State. 421 /// 422 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003 423 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002 424 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001 425 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000 426 427 /// 428 /// UNDI Start. 429 /// 430 /// No additional StatFlags. 431 /// 432 433 /// 434 /// UNDI Get Init Info. 435 /// 436 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001 437 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000 438 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001 439 440 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002 441 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000 442 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002 443 444 /// 445 /// UNDI Initialize. 446 /// 447 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001 448 449 /// 450 /// UNDI Reset. 451 /// 452 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001 453 454 /// 455 /// UNDI Shutdown. 456 /// 457 /// No additional StatFlags. 458 459 /// 460 /// UNDI Interrupt Enables. 461 /// 462 /// 463 /// If set, receive interrupts are enabled. 464 /// 465 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001 466 467 /// 468 /// If set, transmit interrupts are enabled. 469 /// 470 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002 471 472 /// 473 /// If set, command interrupts are enabled. 474 /// 475 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004 476 477 /// 478 /// UNDI Receive Filters. 479 /// 480 481 /// 482 /// If set, unicast packets will be received. 483 /// 484 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001 485 486 /// 487 /// If set, broadcast packets will be received. 488 /// 489 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 490 491 /// 492 /// If set, multicast packets that match up with the multicast address 493 /// filter list will be received. 494 /// 495 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 496 497 /// 498 /// If set, all packets will be received. 499 /// 500 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 501 502 /// 503 /// If set, all multicast packets will be received. 504 /// 505 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 506 507 /// 508 /// UNDI Station Address. 509 /// 510 /// No additional StatFlags. 511 /// 512 513 /// 514 /// UNDI Statistics. 515 /// 516 /// No additional StatFlags. 517 /// 518 519 /// 520 //// UNDI MCast IP to MAC. 521 //// 522 //// No additional StatFlags. 523 524 /// 525 /// UNDI NvData. 526 /// 527 /// No additional StatFlags. 528 /// 529 530 /// 531 /// UNDI Get Status. 532 /// 533 534 /// 535 /// Use to determine if an interrupt has occurred. 536 /// 537 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F 538 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000 539 540 /// 541 /// If set, at least one receive interrupt occurred. 542 /// 543 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001 544 545 /// 546 /// If set, at least one transmit interrupt occurred. 547 /// 548 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002 549 550 /// 551 /// If set, at least one command interrupt occurred. 552 /// 553 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004 554 555 /// 556 /// If set, at least one software interrupt occurred. 557 /// 558 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008 559 560 /// 561 /// This flag is set if the transmitted buffer queue is empty. This flag 562 /// will be set if all transmitted buffer addresses get written into the DB. 563 /// 564 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010 565 566 /// 567 /// This flag is set if no transmitted buffer addresses were written 568 /// into the DB. (This could be because DBsize was too small.) 569 /// 570 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020 571 572 /// 573 /// This flag is set if there is no media detected. 574 /// 575 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040 576 577 /// 578 /// UNDI Fill Header. 579 /// 580 /// No additional StatFlags. 581 /// 582 583 /// 584 /// UNDI Transmit. 585 /// 586 /// No additional StatFlags. 587 588 /// 589 /// UNDI Receive 590 ///. 591 592 /// 593 /// No additional StatFlags. 594 /// 595 typedef PXE_UINT16 PXE_STATCODE; 596 597 #define PXE_STATCODE_INITIALIZE 0x0000 598 599 /// 600 /// Common StatCodes returned by all UNDI commands, UNDI protocol functions 601 /// and BC protocol functions. 602 /// 603 #define PXE_STATCODE_SUCCESS 0x0000 604 605 #define PXE_STATCODE_INVALID_CDB 0x0001 606 #define PXE_STATCODE_INVALID_CPB 0x0002 607 #define PXE_STATCODE_BUSY 0x0003 608 #define PXE_STATCODE_QUEUE_FULL 0x0004 609 #define PXE_STATCODE_ALREADY_STARTED 0x0005 610 #define PXE_STATCODE_NOT_STARTED 0x0006 611 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007 612 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008 613 #define PXE_STATCODE_NOT_INITIALIZED 0x0009 614 #define PXE_STATCODE_DEVICE_FAILURE 0x000A 615 #define PXE_STATCODE_NVDATA_FAILURE 0x000B 616 #define PXE_STATCODE_UNSUPPORTED 0x000C 617 #define PXE_STATCODE_BUFFER_FULL 0x000D 618 #define PXE_STATCODE_INVALID_PARAMETER 0x000E 619 #define PXE_STATCODE_INVALID_UNDI 0x000F 620 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010 621 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011 622 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012 623 #define PXE_STATCODE_NO_DATA 0x0013 624 625 typedef PXE_UINT16 PXE_IFNUM; 626 627 /// 628 /// This interface number must be passed to the S/W UNDI Start command. 629 /// 630 #define PXE_IFNUM_START 0x0000 631 632 /// 633 /// This interface number is returned by the S/W UNDI Get State and 634 /// Start commands if information in the CDB, CPB or DB is invalid. 635 /// 636 #define PXE_IFNUM_INVALID 0x0000 637 638 typedef PXE_UINT16 PXE_CONTROL; 639 640 /// 641 /// Setting this flag directs the UNDI to queue this command for later 642 /// execution if the UNDI is busy and it supports command queuing. 643 /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error 644 /// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL 645 /// error is returned. 646 /// 647 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002 648 649 /// 650 /// These two bit values are used to determine if there are more UNDI 651 /// CDB structures following this one. If the link bit is set, there 652 /// must be a CDB structure following this one. Execution will start 653 /// on the next CDB structure as soon as this one completes successfully. 654 /// If an error is generated by this command, execution will stop. 655 /// 656 #define PXE_CONTROL_LINK 0x0001 657 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000 658 659 typedef PXE_UINT8 PXE_FRAME_TYPE; 660 661 #define PXE_FRAME_TYPE_NONE 0x00 662 #define PXE_FRAME_TYPE_UNICAST 0x01 663 #define PXE_FRAME_TYPE_BROADCAST 0x02 664 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03 665 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04 666 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05 667 668 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST 669 670 typedef PXE_UINT32 PXE_IPV4; 671 672 typedef PXE_UINT32 PXE_IPV6[4]; 673 #define PXE_MAC_LENGTH 32 674 675 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH]; 676 677 typedef PXE_UINT8 PXE_IFTYPE; 678 typedef UINT16 PXE_MEDIA_PROTOCOL; 679 680 /// 681 /// This information is from the ARP section of RFC 1700. 682 /// 683 /// 1 Ethernet (10Mb) [JBP] 684 /// 2 Experimental Ethernet (3Mb) [JBP] 685 /// 3 Amateur Radio AX.25 [PXK] 686 /// 4 Proteon ProNET Token Ring [JBP] 687 /// 5 Chaos [GXP] 688 /// 6 IEEE 802 Networks [JBP] 689 /// 7 ARCNET [JBP] 690 /// 8 Hyperchannel [JBP] 691 /// 9 Lanstar [TU] 692 /// 10 Autonet Short Address [MXB1] 693 /// 11 LocalTalk [JKR1] 694 /// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM] 695 /// 13 Ultra link [RXD2] 696 /// 14 SMDS [GXC1] 697 /// 15 Frame Relay [AGM] 698 /// 16 Asynchronous Transmission Mode (ATM) [JXB2] 699 /// 17 HDLC [JBP] 700 /// 18 Fibre Channel [Yakov Rekhter] 701 /// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach] 702 /// 20 Serial Line [JBP] 703 /// 21 Asynchronous Transmission Mode (ATM) [MXB1] 704 /// 705 /// * Other names and brands may be claimed as the property of others. 706 /// 707 #define PXE_IFTYPE_ETHERNET 0x01 708 #define PXE_IFTYPE_TOKENRING 0x04 709 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12 710 711 typedef struct s_pxe_hw_undi { 712 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE. 713 PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI). 714 PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero. 715 PXE_UINT8 Rev; ///< PXE_ROMID_REV. 716 PXE_UINT8 IFcnt; ///< physical connector count lower byte. 717 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER. 718 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER. 719 PXE_UINT8 IFcntExt; ///< physical connector count upper byte. 720 PXE_UINT8 reserved; ///< zero, not used. 721 PXE_UINT32 Implementation; ///< implementation flags. 722 ///< reserved ///< vendor use. 723 ///< UINT32 Status; ///< status port. 724 ///< UINT32 Command; ///< command port. 725 ///< UINT64 CDBaddr; ///< CDB address port. 726 ///< 727 } PXE_HW_UNDI; 728 729 /// 730 /// Status port bit definitions. 731 /// 732 733 /// 734 /// UNDI operation state. 735 /// 736 #define PXE_HWSTAT_STATE_MASK 0xC0000000 737 #define PXE_HWSTAT_BUSY 0xC0000000 738 #define PXE_HWSTAT_INITIALIZED 0x80000000 739 #define PXE_HWSTAT_STARTED 0x40000000 740 #define PXE_HWSTAT_STOPPED 0x00000000 741 742 /// 743 /// If set, last command failed. 744 /// 745 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000 746 747 /// 748 /// If set, identifies enabled receive filters. 749 /// 750 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000 751 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800 752 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400 753 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200 754 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100 755 756 /// 757 /// If set, identifies enabled external interrupts. 758 /// 759 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080 760 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040 761 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020 762 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010 763 764 /// 765 /// If set, identifies pending interrupts. 766 /// 767 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008 768 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004 769 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002 770 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001 771 772 /// 773 /// Command port definitions. 774 /// 775 776 /// 777 /// If set, CDB identified in CDBaddr port is given to UNDI. 778 /// If not set, other bits in this word will be processed. 779 /// 780 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000 781 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000 782 783 /// 784 /// Use these to enable/disable receive filters. 785 /// 786 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000 787 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800 788 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400 789 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200 790 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100 791 792 /// 793 /// Use these to enable/disable external interrupts. 794 /// 795 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080 796 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040 797 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020 798 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010 799 800 /// 801 /// Use these to clear pending external interrupts. 802 /// 803 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008 804 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004 805 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002 806 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001 807 808 typedef struct s_pxe_sw_undi { 809 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE. 810 PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI). 811 PXE_UINT8 Fudge; ///< makes 8-bit cksum zero. 812 PXE_UINT8 Rev; ///< PXE_ROMID_REV. 813 PXE_UINT8 IFcnt; ///< physical connector count lower byte. 814 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER. 815 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER. 816 PXE_UINT8 IFcntExt; ///< physical connector count upper byte. 817 PXE_UINT8 reserved1; ///< zero, not used. 818 PXE_UINT32 Implementation; ///< Implementation flags. 819 PXE_UINT64 EntryPoint; ///< API entry point. 820 PXE_UINT8 reserved2[3]; ///< zero, not used. 821 PXE_UINT8 BusCnt; ///< number of bustypes supported. 822 PXE_UINT32 BusType[1]; ///< list of supported bustypes. 823 } PXE_SW_UNDI; 824 825 typedef union u_pxe_undi { 826 PXE_HW_UNDI hw; 827 PXE_SW_UNDI sw; 828 } PXE_UNDI; 829 830 /// 831 /// Signature of !PXE structure. 832 /// 833 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E') 834 835 /// 836 /// !PXE structure format revision 837 ///. 838 #define PXE_ROMID_REV 0x02 839 840 /// 841 /// UNDI command interface revision. These are the values that get sent 842 /// in option 94 (Client Network Interface Identifier) in the DHCP Discover 843 /// and PXE Boot Server Request packets. 844 /// 845 #define PXE_ROMID_MAJORVER 0x03 846 #define PXE_ROMID_MINORVER 0x01 847 848 /// 849 /// Implementation flags. 850 /// 851 #define PXE_ROMID_IMP_HW_UNDI 0x80000000 852 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000 853 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000 854 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000 855 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000 856 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000 857 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000 858 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00 859 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00 860 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800 861 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400 862 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000 863 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200 864 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100 865 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080 866 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040 867 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020 868 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010 869 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008 870 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004 871 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002 872 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001 873 874 typedef struct s_pxe_cdb { 875 PXE_OPCODE OpCode; 876 PXE_OPFLAGS OpFlags; 877 PXE_UINT16 CPBsize; 878 PXE_UINT16 DBsize; 879 PXE_UINT64 CPBaddr; 880 PXE_UINT64 DBaddr; 881 PXE_STATCODE StatCode; 882 PXE_STATFLAGS StatFlags; 883 PXE_UINT16 IFnum; 884 PXE_CONTROL Control; 885 } PXE_CDB; 886 887 typedef union u_pxe_ip_addr { 888 PXE_IPV6 IPv6; 889 PXE_IPV4 IPv4; 890 } PXE_IP_ADDR; 891 892 typedef union pxe_device { 893 /// 894 /// PCI and PC Card NICs are both identified using bus, device 895 /// and function numbers. For PC Card, this may require PC 896 /// Card services to be loaded in the BIOS or preboot 897 /// environment. 898 /// 899 struct { 900 /// 901 /// See S/W UNDI ROMID structure definition for PCI and 902 /// PCC BusType definitions. 903 /// 904 PXE_UINT32 BusType; 905 906 /// 907 /// Bus, device & function numbers that locate this device. 908 /// 909 PXE_UINT16 Bus; 910 PXE_UINT8 Device; 911 PXE_UINT8 Function; 912 } 913 PCI, PCC; 914 915 } PXE_DEVICE; 916 917 /// 918 /// cpb and db definitions 919 /// 920 #define MAX_PCI_CONFIG_LEN 64 ///< # of dwords. 921 #define MAX_EEPROM_LEN 128 ///< # of dwords. 922 #define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done. 923 #define MAX_MCAST_ADDRESS_CNT 8 924 925 typedef struct s_pxe_cpb_start_30 { 926 /// 927 /// PXE_VOID Delay(UINTN microseconds); 928 /// 929 /// UNDI will never request a delay smaller than 10 microseconds 930 /// and will always request delays in increments of 10 microseconds. 931 /// The Delay() CallBack routine must delay between n and n + 10 932 /// microseconds before returning control to the UNDI. 933 /// 934 /// This field cannot be set to zero. 935 /// 936 UINT64 Delay; 937 938 /// 939 /// PXE_VOID Block(UINT32 enable); 940 /// 941 /// UNDI may need to block multi-threaded/multi-processor access to 942 /// critical code sections when programming or accessing the network 943 /// device. To this end, a blocking service is needed by the UNDI. 944 /// When UNDI needs a block, it will call Block() passing a non-zero 945 /// value. When UNDI no longer needs a block, it will call Block() 946 /// with a zero value. When called, if the Block() is already enabled, 947 /// do not return control to the UNDI until the previous Block() is 948 /// disabled. 949 /// 950 /// This field cannot be set to zero. 951 /// 952 UINT64 Block; 953 954 /// 955 /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr); 956 /// 957 /// UNDI will pass the virtual address of a buffer and the virtual 958 /// address of a 64-bit physical buffer. Convert the virtual address 959 /// to a physical address and write the result to the physical address 960 /// buffer. If virtual and physical addresses are the same, just 961 /// copy the virtual address to the physical address buffer. 962 /// 963 /// This field can be set to zero if virtual and physical addresses 964 /// are equal. 965 /// 966 UINT64 Virt2Phys; 967 /// 968 /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port, 969 /// UINT64 buf_addr); 970 /// 971 /// UNDI will read or write the device io space using this call back 972 /// function. It passes the number of bytes as the len parameter and it 973 /// will be either 1,2,4 or 8. 974 /// 975 /// This field can not be set to zero. 976 /// 977 UINT64 Mem_IO; 978 } PXE_CPB_START_30; 979 980 typedef struct s_pxe_cpb_start_31 { 981 /// 982 /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds); 983 /// 984 /// UNDI will never request a delay smaller than 10 microseconds 985 /// and will always request delays in increments of 10 microseconds. 986 /// The Delay() CallBack routine must delay between n and n + 10 987 /// microseconds before returning control to the UNDI. 988 /// 989 /// This field cannot be set to zero. 990 /// 991 UINT64 Delay; 992 993 /// 994 /// PXE_VOID Block(UINT64 unq_id, UINT32 enable); 995 /// 996 /// UNDI may need to block multi-threaded/multi-processor access to 997 /// critical code sections when programming or accessing the network 998 /// device. To this end, a blocking service is needed by the UNDI. 999 /// When UNDI needs a block, it will call Block() passing a non-zero 1000 /// value. When UNDI no longer needs a block, it will call Block() 1001 /// with a zero value. When called, if the Block() is already enabled, 1002 /// do not return control to the UNDI until the previous Block() is 1003 /// disabled. 1004 /// 1005 /// This field cannot be set to zero. 1006 /// 1007 UINT64 Block; 1008 1009 /// 1010 /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr); 1011 /// 1012 /// UNDI will pass the virtual address of a buffer and the virtual 1013 /// address of a 64-bit physical buffer. Convert the virtual address 1014 /// to a physical address and write the result to the physical address 1015 /// buffer. If virtual and physical addresses are the same, just 1016 /// copy the virtual address to the physical address buffer. 1017 /// 1018 /// This field can be set to zero if virtual and physical addresses 1019 /// are equal. 1020 /// 1021 UINT64 Virt2Phys; 1022 /// 1023 /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port, 1024 /// UINT64 buf_addr); 1025 /// 1026 /// UNDI will read or write the device io space using this call back 1027 /// function. It passes the number of bytes as the len parameter and it 1028 /// will be either 1,2,4 or 8. 1029 /// 1030 /// This field can not be set to zero. 1031 /// 1032 UINT64 Mem_IO; 1033 /// 1034 /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size, 1035 /// UINT32 Direction, UINT64 mapped_addr); 1036 /// 1037 /// UNDI will pass the virtual address of a buffer, direction of the data 1038 /// flow from/to the mapped buffer (the constants are defined below) 1039 /// and a place holder (pointer) for the mapped address. 1040 /// This call will Map the given address to a physical DMA address and write 1041 /// the result to the mapped_addr pointer. If there is no need to 1042 /// map the given address to a lower address (i.e. the given address is 1043 /// associated with a physical address that is already compatible to be 1044 /// used with the DMA, it converts the given virtual address to it's 1045 /// physical address and write that in the mapped address pointer. 1046 /// 1047 /// This field can be set to zero if there is no mapping service available. 1048 /// 1049 UINT64 Map_Mem; 1050 1051 /// 1052 /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size, 1053 /// UINT32 Direction, UINT64 mapped_addr); 1054 /// 1055 /// UNDI will pass the virtual and mapped addresses of a buffer. 1056 /// This call will un map the given address. 1057 /// 1058 /// This field can be set to zero if there is no unmapping service available. 1059 /// 1060 UINT64 UnMap_Mem; 1061 1062 /// 1063 /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual, 1064 /// UINT32 size, UINT32 Direction, UINT64 mapped_addr); 1065 /// 1066 /// UNDI will pass the virtual and mapped addresses of a buffer. 1067 /// This call will synchronize the contents of both the virtual and mapped. 1068 /// buffers for the given Direction. 1069 /// 1070 /// This field can be set to zero if there is no service available. 1071 /// 1072 UINT64 Sync_Mem; 1073 1074 /// 1075 /// protocol driver can provide anything for this Unique_ID, UNDI remembers 1076 /// that as just a 64bit value associated to the interface specified by 1077 /// the ifnum and gives it back as a parameter to all the call-back routines 1078 /// when calling for that interface! 1079 /// 1080 UINT64 Unique_ID; 1081 } PXE_CPB_START_31; 1082 1083 #define TO_AND_FROM_DEVICE 0 1084 #define FROM_DEVICE 1 1085 #define TO_DEVICE 2 1086 1087 #define PXE_DELAY_MILLISECOND 1000 1088 #define PXE_DELAY_SECOND 1000000 1089 #define PXE_IO_READ 0 1090 #define PXE_IO_WRITE 1 1091 #define PXE_MEM_READ 2 1092 #define PXE_MEM_WRITE 4 1093 1094 typedef struct s_pxe_db_get_init_info { 1095 /// 1096 /// Minimum length of locked memory buffer that must be given to 1097 /// the Initialize command. Giving UNDI more memory will generally 1098 /// give better performance. 1099 /// 1100 /// If MemoryRequired is zero, the UNDI does not need and will not 1101 /// use system memory to receive and transmit packets. 1102 /// 1103 PXE_UINT32 MemoryRequired; 1104 1105 /// 1106 /// Maximum frame data length for Tx/Rx excluding the media header. 1107 /// 1108 PXE_UINT32 FrameDataLen; 1109 1110 /// 1111 /// Supported link speeds are in units of mega bits. Common ethernet 1112 /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero 1113 /// filled. 1114 /// 1115 PXE_UINT32 LinkSpeeds[4]; 1116 1117 /// 1118 /// Number of non-volatile storage items. 1119 /// 1120 PXE_UINT32 NvCount; 1121 1122 /// 1123 /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4 1124 /// 1125 PXE_UINT16 NvWidth; 1126 1127 /// 1128 /// Media header length. This is the typical media header length for 1129 /// this UNDI. This information is needed when allocating receive 1130 /// and transmit buffers. 1131 /// 1132 PXE_UINT16 MediaHeaderLen; 1133 1134 /// 1135 /// Number of bytes in the NIC hardware (MAC) address. 1136 /// 1137 PXE_UINT16 HWaddrLen; 1138 1139 /// 1140 /// Maximum number of multicast MAC addresses in the multicast 1141 /// MAC address filter list. 1142 /// 1143 PXE_UINT16 MCastFilterCnt; 1144 1145 /// 1146 /// Default number and size of transmit and receive buffers that will 1147 /// be allocated by the UNDI. If MemoryRequired is non-zero, this 1148 /// allocation will come out of the memory buffer given to the Initialize 1149 /// command. If MemoryRequired is zero, this allocation will come out of 1150 /// memory on the NIC. 1151 /// 1152 PXE_UINT16 TxBufCnt; 1153 PXE_UINT16 TxBufSize; 1154 PXE_UINT16 RxBufCnt; 1155 PXE_UINT16 RxBufSize; 1156 1157 /// 1158 /// Hardware interface types defined in the Assigned Numbers RFC 1159 /// and used in DHCP and ARP packets. 1160 /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros. 1161 /// 1162 PXE_UINT8 IFtype; 1163 1164 /// 1165 /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below. 1166 /// 1167 PXE_UINT8 SupportedDuplexModes; 1168 1169 /// 1170 /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below. 1171 /// 1172 PXE_UINT8 SupportedLoopBackModes; 1173 } PXE_DB_GET_INIT_INFO; 1174 1175 #define PXE_MAX_TXRX_UNIT_ETHER 1500 1176 1177 #define PXE_HWADDR_LEN_ETHER 0x0006 1178 #define PXE_MAC_HEADER_LEN_ETHER 0x000E 1179 1180 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1 1181 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2 1182 1183 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1 1184 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2 1185 1186 typedef struct s_pxe_pci_config_info { 1187 /// 1188 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union. 1189 /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI. 1190 /// 1191 UINT32 BusType; 1192 1193 /// 1194 /// This identifies the PCI network device that this UNDI interface. 1195 /// is bound to. 1196 /// 1197 UINT16 Bus; 1198 UINT8 Device; 1199 UINT8 Function; 1200 1201 /// 1202 /// This is a copy of the PCI configuration space for this 1203 /// network device. 1204 /// 1205 union { 1206 UINT8 Byte[256]; 1207 UINT16 Word[128]; 1208 UINT32 Dword[64]; 1209 } Config; 1210 } PXE_PCI_CONFIG_INFO; 1211 1212 typedef struct s_pxe_pcc_config_info { 1213 /// 1214 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union. 1215 /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC. 1216 /// 1217 PXE_UINT32 BusType; 1218 1219 /// 1220 /// This identifies the PCC network device that this UNDI interface 1221 /// is bound to. 1222 /// 1223 PXE_UINT16 Bus; 1224 PXE_UINT8 Device; 1225 PXE_UINT8 Function; 1226 1227 /// 1228 /// This is a copy of the PCC configuration space for this 1229 /// network device. 1230 /// 1231 union { 1232 PXE_UINT8 Byte[256]; 1233 PXE_UINT16 Word[128]; 1234 PXE_UINT32 Dword[64]; 1235 } Config; 1236 } PXE_PCC_CONFIG_INFO; 1237 1238 typedef union u_pxe_db_get_config_info { 1239 PXE_PCI_CONFIG_INFO pci; 1240 PXE_PCC_CONFIG_INFO pcc; 1241 } PXE_DB_GET_CONFIG_INFO; 1242 1243 typedef struct s_pxe_cpb_initialize { 1244 /// 1245 /// Address of first (lowest) byte of the memory buffer. This buffer must 1246 /// be in contiguous physical memory and cannot be swapped out. The UNDI 1247 /// will be using this for transmit and receive buffering. 1248 /// 1249 PXE_UINT64 MemoryAddr; 1250 1251 /// 1252 /// MemoryLength must be greater than or equal to MemoryRequired 1253 /// returned by the Get Init Info command. 1254 /// 1255 PXE_UINT32 MemoryLength; 1256 1257 /// 1258 /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100 1259 /// and 1000. Setting a value of zero will auto-detect and/or use the 1260 /// default link speed (operation depends on UNDI/NIC functionality). 1261 /// 1262 PXE_UINT32 LinkSpeed; 1263 1264 /// 1265 /// Suggested number and size of receive and transmit buffers to 1266 /// allocate. If MemoryAddr and MemoryLength are non-zero, this 1267 /// allocation comes out of the supplied memory buffer. If MemoryAddr 1268 /// and MemoryLength are zero, this allocation comes out of memory 1269 /// on the NIC. 1270 /// 1271 /// If these fields are set to zero, the UNDI will allocate buffer 1272 /// counts and sizes as it sees fit. 1273 /// 1274 PXE_UINT16 TxBufCnt; 1275 PXE_UINT16 TxBufSize; 1276 PXE_UINT16 RxBufCnt; 1277 PXE_UINT16 RxBufSize; 1278 1279 /// 1280 /// The following configuration parameters are optional and must be zero 1281 /// to use the default values. 1282 /// 1283 PXE_UINT8 DuplexMode; 1284 1285 PXE_UINT8 LoopBackMode; 1286 } PXE_CPB_INITIALIZE; 1287 1288 #define PXE_DUPLEX_DEFAULT 0x00 1289 #define PXE_FORCE_FULL_DUPLEX 0x01 1290 #define PXE_ENABLE_FULL_DUPLEX 0x02 1291 #define PXE_FORCE_HALF_DUPLEX 0x04 1292 #define PXE_DISABLE_FULL_DUPLEX 0x08 1293 1294 #define LOOPBACK_NORMAL 0 1295 #define LOOPBACK_INTERNAL 1 1296 #define LOOPBACK_EXTERNAL 2 1297 1298 typedef struct s_pxe_db_initialize { 1299 /// 1300 /// Actual amount of memory used from the supplied memory buffer. This 1301 /// may be less that the amount of memory suppllied and may be zero if 1302 /// the UNDI and network device do not use external memory buffers. 1303 /// 1304 /// Memory used by the UNDI and network device is allocated from the 1305 /// lowest memory buffer address. 1306 /// 1307 PXE_UINT32 MemoryUsed; 1308 1309 /// 1310 /// Actual number and size of receive and transmit buffers that were 1311 /// allocated. 1312 /// 1313 PXE_UINT16 TxBufCnt; 1314 PXE_UINT16 TxBufSize; 1315 PXE_UINT16 RxBufCnt; 1316 PXE_UINT16 RxBufSize; 1317 } PXE_DB_INITIALIZE; 1318 1319 typedef struct s_pxe_cpb_receive_filters { 1320 /// 1321 /// List of multicast MAC addresses. This list, if present, will 1322 /// replace the existing multicast MAC address filter list. 1323 /// 1324 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; 1325 } PXE_CPB_RECEIVE_FILTERS; 1326 1327 typedef struct s_pxe_db_receive_filters { 1328 /// 1329 /// Filtered multicast MAC address list. 1330 /// 1331 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; 1332 } PXE_DB_RECEIVE_FILTERS; 1333 1334 typedef struct s_pxe_cpb_station_address { 1335 /// 1336 /// If supplied and supported, the current station MAC address 1337 /// will be changed. 1338 /// 1339 PXE_MAC_ADDR StationAddr; 1340 } PXE_CPB_STATION_ADDRESS; 1341 1342 typedef struct s_pxe_dpb_station_address { 1343 /// 1344 /// Current station MAC address. 1345 /// 1346 PXE_MAC_ADDR StationAddr; 1347 1348 /// 1349 /// Station broadcast MAC address. 1350 /// 1351 PXE_MAC_ADDR BroadcastAddr; 1352 1353 /// 1354 /// Permanent station MAC address. 1355 /// 1356 PXE_MAC_ADDR PermanentAddr; 1357 } PXE_DB_STATION_ADDRESS; 1358 1359 typedef struct s_pxe_db_statistics { 1360 /// 1361 /// Bit field identifying what statistic data is collected by the 1362 /// UNDI/NIC. 1363 /// If bit 0x00 is set, Data[0x00] is collected. 1364 /// If bit 0x01 is set, Data[0x01] is collected. 1365 /// If bit 0x20 is set, Data[0x20] is collected. 1366 /// If bit 0x21 is set, Data[0x21] is collected. 1367 /// Etc. 1368 /// 1369 PXE_UINT64 Supported; 1370 1371 /// 1372 /// Statistic data. 1373 /// 1374 PXE_UINT64 Data[64]; 1375 } PXE_DB_STATISTICS; 1376 1377 /// 1378 /// Total number of frames received. Includes frames with errors and 1379 /// dropped frames. 1380 /// 1381 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00 1382 1383 /// 1384 /// Number of valid frames received and copied into receive buffers. 1385 /// 1386 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01 1387 1388 /// 1389 /// Number of frames below the minimum length for the media. 1390 /// This would be <64 for ethernet. 1391 /// 1392 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02 1393 1394 /// 1395 /// Number of frames longer than the maxminum length for the 1396 /// media. This would be >1500 for ethernet. 1397 /// 1398 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03 1399 1400 /// 1401 /// Valid frames that were dropped because receive buffers were full. 1402 /// 1403 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04 1404 1405 /// 1406 /// Number of valid unicast frames received and not dropped. 1407 /// 1408 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05 1409 1410 /// 1411 /// Number of valid broadcast frames received and not dropped. 1412 /// 1413 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06 1414 1415 /// 1416 /// Number of valid mutlicast frames received and not dropped. 1417 /// 1418 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07 1419 1420 /// 1421 /// Number of frames w/ CRC or alignment errors. 1422 /// 1423 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08 1424 1425 /// 1426 /// Total number of bytes received. Includes frames with errors 1427 /// and dropped frames. 1428 /// 1429 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09 1430 1431 /// 1432 /// Transmit statistics. 1433 /// 1434 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A 1435 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B 1436 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C 1437 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D 1438 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E 1439 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F 1440 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10 1441 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11 1442 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12 1443 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13 1444 1445 /// 1446 /// Number of collisions detection on this subnet. 1447 /// 1448 #define PXE_STATISTICS_COLLISIONS 0x14 1449 1450 /// 1451 /// Number of frames destined for unsupported protocol. 1452 /// 1453 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15 1454 1455 /// 1456 /// Number of valid frames received that were duplicated. 1457 /// 1458 #define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16 1459 1460 /// 1461 /// Number of encrypted frames received that failed to decrypt. 1462 /// 1463 #define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17 1464 1465 /// 1466 /// Number of frames that failed to transmit after exceeding the retry limit. 1467 /// 1468 #define PXE_STATISTICS_TX_ERROR_FRAMES 0x18 1469 1470 /// 1471 /// Number of frames transmitted successfully after more than one attempt. 1472 /// 1473 #define PXE_STATISTICS_TX_RETRY_FRAMES 0x19 1474 1475 typedef struct s_pxe_cpb_mcast_ip_to_mac { 1476 /// 1477 /// Multicast IP address to be converted to multicast MAC address. 1478 /// 1479 PXE_IP_ADDR IP; 1480 } PXE_CPB_MCAST_IP_TO_MAC; 1481 1482 typedef struct s_pxe_db_mcast_ip_to_mac { 1483 /// 1484 /// Multicast MAC address. 1485 /// 1486 PXE_MAC_ADDR MAC; 1487 } PXE_DB_MCAST_IP_TO_MAC; 1488 1489 typedef struct s_pxe_cpb_nvdata_sparse { 1490 /// 1491 /// NvData item list. Only items in this list will be updated. 1492 /// 1493 struct { 1494 /// 1495 /// Non-volatile storage address to be changed. 1496 /// 1497 PXE_UINT32 Addr; 1498 1499 /// 1500 /// Data item to write into above storage address. 1501 /// 1502 union { 1503 PXE_UINT8 Byte; 1504 PXE_UINT16 Word; 1505 PXE_UINT32 Dword; 1506 } Data; 1507 } Item[MAX_EEPROM_LEN]; 1508 } PXE_CPB_NVDATA_SPARSE; 1509 1510 /// 1511 /// When using bulk update, the size of the CPB structure must be 1512 /// the same size as the non-volatile NIC storage. 1513 /// 1514 typedef union u_pxe_cpb_nvdata_bulk { 1515 /// 1516 /// Array of byte-wide data items. 1517 /// 1518 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; 1519 1520 /// 1521 /// Array of word-wide data items. 1522 /// 1523 PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; 1524 1525 /// 1526 /// Array of dword-wide data items. 1527 /// 1528 PXE_UINT32 Dword[MAX_EEPROM_LEN]; 1529 } PXE_CPB_NVDATA_BULK; 1530 1531 typedef struct s_pxe_db_nvdata { 1532 /// 1533 /// Arrays of data items from non-volatile storage. 1534 /// 1535 union { 1536 /// 1537 /// Array of byte-wide data items. 1538 /// 1539 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; 1540 1541 /// 1542 /// Array of word-wide data items. 1543 /// 1544 PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; 1545 1546 /// 1547 /// Array of dword-wide data items. 1548 /// 1549 PXE_UINT32 Dword[MAX_EEPROM_LEN]; 1550 } Data; 1551 } PXE_DB_NVDATA; 1552 1553 typedef struct s_pxe_db_get_status { 1554 /// 1555 /// Length of next receive frame (header + data). If this is zero, 1556 /// there is no next receive frame available. 1557 /// 1558 PXE_UINT32 RxFrameLen; 1559 1560 /// 1561 /// Reserved, set to zero. 1562 /// 1563 PXE_UINT32 reserved; 1564 1565 /// 1566 /// Addresses of transmitted buffers that need to be recycled. 1567 /// 1568 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS]; 1569 } PXE_DB_GET_STATUS; 1570 1571 typedef struct s_pxe_cpb_fill_header { 1572 /// 1573 /// Source and destination MAC addresses. These will be copied into 1574 /// the media header without doing byte swapping. 1575 /// 1576 PXE_MAC_ADDR SrcAddr; 1577 PXE_MAC_ADDR DestAddr; 1578 1579 /// 1580 /// Address of first byte of media header. The first byte of packet data 1581 /// follows the last byte of the media header. 1582 /// 1583 PXE_UINT64 MediaHeader; 1584 1585 /// 1586 /// Length of packet data in bytes (not including the media header). 1587 /// 1588 PXE_UINT32 PacketLen; 1589 1590 /// 1591 /// Protocol type. This will be copied into the media header without 1592 /// doing byte swapping. Protocol type numbers can be obtained from 1593 /// the Assigned Numbers RFC 1700. 1594 /// 1595 PXE_UINT16 Protocol; 1596 1597 /// 1598 /// Length of the media header in bytes. 1599 /// 1600 PXE_UINT16 MediaHeaderLen; 1601 } PXE_CPB_FILL_HEADER; 1602 1603 #define PXE_PROTOCOL_ETHERNET_IP 0x0800 1604 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806 1605 #define MAX_XMIT_FRAGMENTS 16 1606 1607 typedef struct s_pxe_cpb_fill_header_fragmented { 1608 /// 1609 /// Source and destination MAC addresses. These will be copied into 1610 /// the media header without doing byte swapping. 1611 /// 1612 PXE_MAC_ADDR SrcAddr; 1613 PXE_MAC_ADDR DestAddr; 1614 1615 /// 1616 /// Length of packet data in bytes (not including the media header). 1617 /// 1618 PXE_UINT32 PacketLen; 1619 1620 /// 1621 /// Protocol type. This will be copied into the media header without 1622 /// doing byte swapping. Protocol type numbers can be obtained from 1623 /// the Assigned Numbers RFC 1700. 1624 /// 1625 PXE_MEDIA_PROTOCOL Protocol; 1626 1627 /// 1628 /// Length of the media header in bytes. 1629 /// 1630 PXE_UINT16 MediaHeaderLen; 1631 1632 /// 1633 /// Number of packet fragment descriptors. 1634 /// 1635 PXE_UINT16 FragCnt; 1636 1637 /// 1638 /// Reserved, must be set to zero. 1639 /// 1640 PXE_UINT16 reserved; 1641 1642 /// 1643 /// Array of packet fragment descriptors. The first byte of the media 1644 /// header is the first byte of the first fragment. 1645 /// 1646 struct { 1647 /// 1648 /// Address of this packet fragment. 1649 /// 1650 PXE_UINT64 FragAddr; 1651 1652 /// 1653 /// Length of this packet fragment. 1654 /// 1655 PXE_UINT32 FragLen; 1656 1657 /// 1658 /// Reserved, must be set to zero. 1659 /// 1660 PXE_UINT32 reserved; 1661 } FragDesc[MAX_XMIT_FRAGMENTS]; 1662 } 1663 PXE_CPB_FILL_HEADER_FRAGMENTED; 1664 1665 typedef struct s_pxe_cpb_transmit { 1666 /// 1667 /// Address of first byte of frame buffer. This is also the first byte 1668 /// of the media header. 1669 /// 1670 PXE_UINT64 FrameAddr; 1671 1672 /// 1673 /// Length of the data portion of the frame buffer in bytes. Do not 1674 /// include the length of the media header. 1675 /// 1676 PXE_UINT32 DataLen; 1677 1678 /// 1679 /// Length of the media header in bytes. 1680 /// 1681 PXE_UINT16 MediaheaderLen; 1682 1683 /// 1684 /// Reserved, must be zero. 1685 /// 1686 PXE_UINT16 reserved; 1687 } PXE_CPB_TRANSMIT; 1688 1689 typedef struct s_pxe_cpb_transmit_fragments { 1690 /// 1691 /// Length of packet data in bytes (not including the media header). 1692 /// 1693 PXE_UINT32 FrameLen; 1694 1695 /// 1696 /// Length of the media header in bytes. 1697 /// 1698 PXE_UINT16 MediaheaderLen; 1699 1700 /// 1701 /// Number of packet fragment descriptors. 1702 /// 1703 PXE_UINT16 FragCnt; 1704 1705 /// 1706 /// Array of frame fragment descriptors. The first byte of the first 1707 /// fragment is also the first byte of the media header. 1708 /// 1709 struct { 1710 /// 1711 /// Address of this frame fragment. 1712 /// 1713 PXE_UINT64 FragAddr; 1714 1715 /// 1716 /// Length of this frame fragment. 1717 /// 1718 PXE_UINT32 FragLen; 1719 1720 /// 1721 /// Reserved, must be set to zero. 1722 /// 1723 PXE_UINT32 reserved; 1724 } FragDesc[MAX_XMIT_FRAGMENTS]; 1725 } 1726 PXE_CPB_TRANSMIT_FRAGMENTS; 1727 1728 typedef struct s_pxe_cpb_receive { 1729 /// 1730 /// Address of first byte of receive buffer. This is also the first byte 1731 /// of the frame header. 1732 /// 1733 PXE_UINT64 BufferAddr; 1734 1735 /// 1736 /// Length of receive buffer. This must be large enough to hold the 1737 /// received frame (media header + data). If the length of smaller than 1738 /// the received frame, data will be lost. 1739 /// 1740 PXE_UINT32 BufferLen; 1741 1742 /// 1743 /// Reserved, must be set to zero. 1744 /// 1745 PXE_UINT32 reserved; 1746 } PXE_CPB_RECEIVE; 1747 1748 typedef struct s_pxe_db_receive { 1749 /// 1750 /// Source and destination MAC addresses from media header. 1751 /// 1752 PXE_MAC_ADDR SrcAddr; 1753 PXE_MAC_ADDR DestAddr; 1754 1755 /// 1756 /// Length of received frame. May be larger than receive buffer size. 1757 /// The receive buffer will not be overwritten. This is how to tell 1758 /// if data was lost because the receive buffer was too small. 1759 /// 1760 PXE_UINT32 FrameLen; 1761 1762 /// 1763 /// Protocol type from media header. 1764 /// 1765 PXE_MEDIA_PROTOCOL Protocol; 1766 1767 /// 1768 /// Length of media header in received frame. 1769 /// 1770 PXE_UINT16 MediaHeaderLen; 1771 1772 /// 1773 /// Type of receive frame. 1774 /// 1775 PXE_FRAME_TYPE Type; 1776 1777 /// 1778 /// Reserved, must be zero. 1779 /// 1780 PXE_UINT8 reserved[7]; 1781 1782 } PXE_DB_RECEIVE; 1783 1784 #pragma pack() 1785 1786 #endif 1787