1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2022 StarFive Technology Co., Ltd. 4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/starfive,jh7110-crg.h> 9#include <dt-bindings/reset/starfive,jh7110-crg.h> 10 11/ { 12 compatible = "starfive,jh7110"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 S7_0: cpu@0 { 21 compatible = "sifive,s7", "riscv"; 22 reg = <0>; 23 device_type = "cpu"; 24 i-cache-block-size = <64>; 25 i-cache-sets = <64>; 26 i-cache-size = <16384>; 27 next-level-cache = <&ccache>; 28 riscv,isa = "rv64imac_zba_zbb"; 29 status = "disabled"; 30 31 cpu0_intc: interrupt-controller { 32 compatible = "riscv,cpu-intc"; 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 }; 37 38 U74_1: cpu@1 { 39 compatible = "sifive,u74-mc", "riscv"; 40 reg = <1>; 41 d-cache-block-size = <64>; 42 d-cache-sets = <64>; 43 d-cache-size = <32768>; 44 d-tlb-sets = <1>; 45 d-tlb-size = <40>; 46 device_type = "cpu"; 47 i-cache-block-size = <64>; 48 i-cache-sets = <64>; 49 i-cache-size = <32768>; 50 i-tlb-sets = <1>; 51 i-tlb-size = <40>; 52 mmu-type = "riscv,sv39"; 53 next-level-cache = <&ccache>; 54 riscv,isa = "rv64imafdc_zba_zbb"; 55 tlb-split; 56 operating-points-v2 = <&cpu_opp>; 57 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 58 clock-names = "cpu"; 59 60 cpu1_intc: interrupt-controller { 61 compatible = "riscv,cpu-intc"; 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 }; 65 }; 66 67 U74_2: cpu@2 { 68 compatible = "sifive,u74-mc", "riscv"; 69 reg = <2>; 70 d-cache-block-size = <64>; 71 d-cache-sets = <64>; 72 d-cache-size = <32768>; 73 d-tlb-sets = <1>; 74 d-tlb-size = <40>; 75 device_type = "cpu"; 76 i-cache-block-size = <64>; 77 i-cache-sets = <64>; 78 i-cache-size = <32768>; 79 i-tlb-sets = <1>; 80 i-tlb-size = <40>; 81 mmu-type = "riscv,sv39"; 82 next-level-cache = <&ccache>; 83 riscv,isa = "rv64imafdc_zba_zbb"; 84 tlb-split; 85 operating-points-v2 = <&cpu_opp>; 86 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 87 clock-names = "cpu"; 88 89 cpu2_intc: interrupt-controller { 90 compatible = "riscv,cpu-intc"; 91 interrupt-controller; 92 #interrupt-cells = <1>; 93 }; 94 }; 95 96 U74_3: cpu@3 { 97 compatible = "sifive,u74-mc", "riscv"; 98 reg = <3>; 99 d-cache-block-size = <64>; 100 d-cache-sets = <64>; 101 d-cache-size = <32768>; 102 d-tlb-sets = <1>; 103 d-tlb-size = <40>; 104 device_type = "cpu"; 105 i-cache-block-size = <64>; 106 i-cache-sets = <64>; 107 i-cache-size = <32768>; 108 i-tlb-sets = <1>; 109 i-tlb-size = <40>; 110 mmu-type = "riscv,sv39"; 111 next-level-cache = <&ccache>; 112 riscv,isa = "rv64imafdc_zba_zbb"; 113 tlb-split; 114 operating-points-v2 = <&cpu_opp>; 115 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 116 clock-names = "cpu"; 117 118 cpu3_intc: interrupt-controller { 119 compatible = "riscv,cpu-intc"; 120 interrupt-controller; 121 #interrupt-cells = <1>; 122 }; 123 }; 124 125 U74_4: cpu@4 { 126 compatible = "sifive,u74-mc", "riscv"; 127 reg = <4>; 128 d-cache-block-size = <64>; 129 d-cache-sets = <64>; 130 d-cache-size = <32768>; 131 d-tlb-sets = <1>; 132 d-tlb-size = <40>; 133 device_type = "cpu"; 134 i-cache-block-size = <64>; 135 i-cache-sets = <64>; 136 i-cache-size = <32768>; 137 i-tlb-sets = <1>; 138 i-tlb-size = <40>; 139 mmu-type = "riscv,sv39"; 140 next-level-cache = <&ccache>; 141 riscv,isa = "rv64imafdc_zba_zbb"; 142 tlb-split; 143 operating-points-v2 = <&cpu_opp>; 144 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; 145 clock-names = "cpu"; 146 147 cpu4_intc: interrupt-controller { 148 compatible = "riscv,cpu-intc"; 149 interrupt-controller; 150 #interrupt-cells = <1>; 151 }; 152 }; 153 154 cpu-map { 155 cluster0 { 156 core0 { 157 cpu = <&S7_0>; 158 }; 159 160 core1 { 161 cpu = <&U74_1>; 162 }; 163 164 core2 { 165 cpu = <&U74_2>; 166 }; 167 168 core3 { 169 cpu = <&U74_3>; 170 }; 171 172 core4 { 173 cpu = <&U74_4>; 174 }; 175 }; 176 }; 177 }; 178 179 cpu_opp: opp-table-0 { 180 compatible = "operating-points-v2"; 181 opp-shared; 182 opp-375000000 { 183 opp-hz = /bits/ 64 <375000000>; 184 opp-microvolt = <800000>; 185 }; 186 opp-500000000 { 187 opp-hz = /bits/ 64 <500000000>; 188 opp-microvolt = <800000>; 189 }; 190 opp-750000000 { 191 opp-hz = /bits/ 64 <750000000>; 192 opp-microvolt = <800000>; 193 }; 194 opp-1500000000 { 195 opp-hz = /bits/ 64 <1500000000>; 196 opp-microvolt = <1040000>; 197 }; 198 }; 199 200 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { 201 compatible = "fixed-clock"; 202 clock-output-names = "gmac0_rgmii_rxin"; 203 #clock-cells = <0>; 204 }; 205 206 gmac0_rmii_refin: gmac0-rmii-refin-clock { 207 compatible = "fixed-clock"; 208 clock-output-names = "gmac0_rmii_refin"; 209 #clock-cells = <0>; 210 }; 211 212 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { 213 compatible = "fixed-clock"; 214 clock-output-names = "gmac1_rgmii_rxin"; 215 #clock-cells = <0>; 216 }; 217 218 gmac1_rmii_refin: gmac1-rmii-refin-clock { 219 compatible = "fixed-clock"; 220 clock-output-names = "gmac1_rmii_refin"; 221 #clock-cells = <0>; 222 }; 223 224 i2srx_bclk_ext: i2srx-bclk-ext-clock { 225 compatible = "fixed-clock"; 226 clock-output-names = "i2srx_bclk_ext"; 227 #clock-cells = <0>; 228 }; 229 230 i2srx_lrck_ext: i2srx-lrck-ext-clock { 231 compatible = "fixed-clock"; 232 clock-output-names = "i2srx_lrck_ext"; 233 #clock-cells = <0>; 234 }; 235 236 i2stx_bclk_ext: i2stx-bclk-ext-clock { 237 compatible = "fixed-clock"; 238 clock-output-names = "i2stx_bclk_ext"; 239 #clock-cells = <0>; 240 }; 241 242 i2stx_lrck_ext: i2stx-lrck-ext-clock { 243 compatible = "fixed-clock"; 244 clock-output-names = "i2stx_lrck_ext"; 245 #clock-cells = <0>; 246 }; 247 248 mclk_ext: mclk-ext-clock { 249 compatible = "fixed-clock"; 250 clock-output-names = "mclk_ext"; 251 #clock-cells = <0>; 252 }; 253 254 osc: oscillator { 255 compatible = "fixed-clock"; 256 clock-output-names = "osc"; 257 #clock-cells = <0>; 258 }; 259 260 rtc_osc: rtc-oscillator { 261 compatible = "fixed-clock"; 262 clock-output-names = "rtc_osc"; 263 #clock-cells = <0>; 264 }; 265 266 tdm_ext: tdm-ext-clock { 267 compatible = "fixed-clock"; 268 clock-output-names = "tdm_ext"; 269 #clock-cells = <0>; 270 }; 271 272 soc { 273 compatible = "simple-bus"; 274 interrupt-parent = <&plic>; 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 279 clint: timer@2000000 { 280 compatible = "starfive,jh7110-clint", "sifive,clint0"; 281 reg = <0x0 0x2000000 0x0 0x10000>; 282 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 283 <&cpu1_intc 3>, <&cpu1_intc 7>, 284 <&cpu2_intc 3>, <&cpu2_intc 7>, 285 <&cpu3_intc 3>, <&cpu3_intc 7>, 286 <&cpu4_intc 3>, <&cpu4_intc 7>; 287 }; 288 289 ccache: cache-controller@2010000 { 290 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; 291 reg = <0x0 0x2010000 0x0 0x4000>; 292 interrupts = <1>, <3>, <4>, <2>; 293 cache-block-size = <64>; 294 cache-level = <2>; 295 cache-sets = <2048>; 296 cache-size = <2097152>; 297 cache-unified; 298 }; 299 300 plic: interrupt-controller@c000000 { 301 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; 302 reg = <0x0 0xc000000 0x0 0x4000000>; 303 interrupts-extended = <&cpu0_intc 11>, 304 <&cpu1_intc 11>, <&cpu1_intc 9>, 305 <&cpu2_intc 11>, <&cpu2_intc 9>, 306 <&cpu3_intc 11>, <&cpu3_intc 9>, 307 <&cpu4_intc 11>, <&cpu4_intc 9>; 308 interrupt-controller; 309 #interrupt-cells = <1>; 310 #address-cells = <0>; 311 riscv,ndev = <136>; 312 }; 313 314 uart0: serial@10000000 { 315 compatible = "snps,dw-apb-uart"; 316 reg = <0x0 0x10000000 0x0 0x10000>; 317 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, 318 <&syscrg JH7110_SYSCLK_UART0_APB>; 319 clock-names = "baudclk", "apb_pclk"; 320 resets = <&syscrg JH7110_SYSRST_UART0_APB>; 321 interrupts = <32>; 322 reg-io-width = <4>; 323 reg-shift = <2>; 324 status = "disabled"; 325 }; 326 327 uart1: serial@10010000 { 328 compatible = "snps,dw-apb-uart"; 329 reg = <0x0 0x10010000 0x0 0x10000>; 330 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, 331 <&syscrg JH7110_SYSCLK_UART1_APB>; 332 clock-names = "baudclk", "apb_pclk"; 333 resets = <&syscrg JH7110_SYSRST_UART1_APB>; 334 interrupts = <33>; 335 reg-io-width = <4>; 336 reg-shift = <2>; 337 status = "disabled"; 338 }; 339 340 uart2: serial@10020000 { 341 compatible = "snps,dw-apb-uart"; 342 reg = <0x0 0x10020000 0x0 0x10000>; 343 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, 344 <&syscrg JH7110_SYSCLK_UART2_APB>; 345 clock-names = "baudclk", "apb_pclk"; 346 resets = <&syscrg JH7110_SYSRST_UART2_APB>; 347 interrupts = <34>; 348 reg-io-width = <4>; 349 reg-shift = <2>; 350 status = "disabled"; 351 }; 352 353 i2c0: i2c@10030000 { 354 compatible = "snps,designware-i2c"; 355 reg = <0x0 0x10030000 0x0 0x10000>; 356 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; 357 clock-names = "ref"; 358 resets = <&syscrg JH7110_SYSRST_I2C0_APB>; 359 interrupts = <35>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 i2c1: i2c@10040000 { 366 compatible = "snps,designware-i2c"; 367 reg = <0x0 0x10040000 0x0 0x10000>; 368 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; 369 clock-names = "ref"; 370 resets = <&syscrg JH7110_SYSRST_I2C1_APB>; 371 interrupts = <36>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 i2c2: i2c@10050000 { 378 compatible = "snps,designware-i2c"; 379 reg = <0x0 0x10050000 0x0 0x10000>; 380 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; 381 clock-names = "ref"; 382 resets = <&syscrg JH7110_SYSRST_I2C2_APB>; 383 interrupts = <37>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 status = "disabled"; 387 }; 388 389 uart3: serial@12000000 { 390 compatible = "snps,dw-apb-uart"; 391 reg = <0x0 0x12000000 0x0 0x10000>; 392 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, 393 <&syscrg JH7110_SYSCLK_UART3_APB>; 394 clock-names = "baudclk", "apb_pclk"; 395 resets = <&syscrg JH7110_SYSRST_UART3_APB>; 396 interrupts = <45>; 397 reg-io-width = <4>; 398 reg-shift = <2>; 399 status = "disabled"; 400 }; 401 402 uart4: serial@12010000 { 403 compatible = "snps,dw-apb-uart"; 404 reg = <0x0 0x12010000 0x0 0x10000>; 405 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, 406 <&syscrg JH7110_SYSCLK_UART4_APB>; 407 clock-names = "baudclk", "apb_pclk"; 408 resets = <&syscrg JH7110_SYSRST_UART4_APB>; 409 interrupts = <46>; 410 reg-io-width = <4>; 411 reg-shift = <2>; 412 status = "disabled"; 413 }; 414 415 uart5: serial@12020000 { 416 compatible = "snps,dw-apb-uart"; 417 reg = <0x0 0x12020000 0x0 0x10000>; 418 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, 419 <&syscrg JH7110_SYSCLK_UART5_APB>; 420 clock-names = "baudclk", "apb_pclk"; 421 resets = <&syscrg JH7110_SYSRST_UART5_APB>; 422 interrupts = <47>; 423 reg-io-width = <4>; 424 reg-shift = <2>; 425 status = "disabled"; 426 }; 427 428 i2c3: i2c@12030000 { 429 compatible = "snps,designware-i2c"; 430 reg = <0x0 0x12030000 0x0 0x10000>; 431 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; 432 clock-names = "ref"; 433 resets = <&syscrg JH7110_SYSRST_I2C3_APB>; 434 interrupts = <48>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 i2c4: i2c@12040000 { 441 compatible = "snps,designware-i2c"; 442 reg = <0x0 0x12040000 0x0 0x10000>; 443 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; 444 clock-names = "ref"; 445 resets = <&syscrg JH7110_SYSRST_I2C4_APB>; 446 interrupts = <49>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 i2c5: i2c@12050000 { 453 compatible = "snps,designware-i2c"; 454 reg = <0x0 0x12050000 0x0 0x10000>; 455 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; 456 clock-names = "ref"; 457 resets = <&syscrg JH7110_SYSRST_I2C5_APB>; 458 interrupts = <50>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 i2c6: i2c@12060000 { 465 compatible = "snps,designware-i2c"; 466 reg = <0x0 0x12060000 0x0 0x10000>; 467 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; 468 clock-names = "ref"; 469 resets = <&syscrg JH7110_SYSRST_I2C6_APB>; 470 interrupts = <51>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 syscrg: clock-controller@13020000 { 477 compatible = "starfive,jh7110-syscrg"; 478 reg = <0x0 0x13020000 0x0 0x10000>; 479 clocks = <&osc>, <&gmac1_rmii_refin>, 480 <&gmac1_rgmii_rxin>, 481 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, 482 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, 483 <&tdm_ext>, <&mclk_ext>; 484 clock-names = "osc", "gmac1_rmii_refin", 485 "gmac1_rgmii_rxin", 486 "i2stx_bclk_ext", "i2stx_lrck_ext", 487 "i2srx_bclk_ext", "i2srx_lrck_ext", 488 "tdm_ext", "mclk_ext"; 489 #clock-cells = <1>; 490 #reset-cells = <1>; 491 }; 492 493 sysgpio: pinctrl@13040000 { 494 compatible = "starfive,jh7110-sys-pinctrl"; 495 reg = <0x0 0x13040000 0x0 0x10000>; 496 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; 497 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; 498 interrupts = <86>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 }; 504 505 watchdog@13070000 { 506 compatible = "starfive,jh7110-wdt"; 507 reg = <0x0 0x13070000 0x0 0x10000>; 508 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, 509 <&syscrg JH7110_SYSCLK_WDT_CORE>; 510 clock-names = "apb", "core"; 511 resets = <&syscrg JH7110_SYSRST_WDT_APB>, 512 <&syscrg JH7110_SYSRST_WDT_CORE>; 513 }; 514 515 aoncrg: clock-controller@17000000 { 516 compatible = "starfive,jh7110-aoncrg"; 517 reg = <0x0 0x17000000 0x0 0x10000>; 518 clocks = <&osc>, <&gmac0_rmii_refin>, 519 <&gmac0_rgmii_rxin>, 520 <&syscrg JH7110_SYSCLK_STG_AXIAHB>, 521 <&syscrg JH7110_SYSCLK_APB_BUS>, 522 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, 523 <&rtc_osc>; 524 clock-names = "osc", "gmac0_rmii_refin", 525 "gmac0_rgmii_rxin", "stg_axiahb", 526 "apb_bus", "gmac0_gtxclk", 527 "rtc_osc"; 528 #clock-cells = <1>; 529 #reset-cells = <1>; 530 }; 531 532 aongpio: pinctrl@17020000 { 533 compatible = "starfive,jh7110-aon-pinctrl"; 534 reg = <0x0 0x17020000 0x0 0x10000>; 535 resets = <&aoncrg JH7110_AONRST_IOMUX>; 536 interrupts = <85>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 }; 542 543 pwrc: power-controller@17030000 { 544 compatible = "starfive,jh7110-pmu"; 545 reg = <0x0 0x17030000 0x0 0x10000>; 546 interrupts = <111>; 547 #power-domain-cells = <1>; 548 }; 549 }; 550}; 551