xref: /freebsd/sys/contrib/device-tree/src/riscv/sophgo/cv18xx.dtsi (revision 9bc300465e48e19d794d88d0c158a2adb92c7197)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12
13	cpus: cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16		timebase-frequency = <25000000>;
17
18		cpu0: cpu@0 {
19			compatible = "thead,c906", "riscv";
20			device_type = "cpu";
21			reg = <0>;
22			d-cache-block-size = <64>;
23			d-cache-sets = <512>;
24			d-cache-size = <65536>;
25			i-cache-block-size = <64>;
26			i-cache-sets = <128>;
27			i-cache-size = <32768>;
28			mmu-type = "riscv,sv39";
29			riscv,isa = "rv64imafdc";
30			riscv,isa-base = "rv64i";
31			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
32					       "zifencei", "zihpm";
33
34			cpu0_intc: interrupt-controller {
35				compatible = "riscv,cpu-intc";
36				interrupt-controller;
37				#interrupt-cells = <1>;
38			};
39		};
40	};
41
42	osc: oscillator {
43		compatible = "fixed-clock";
44		clock-output-names = "osc_25m";
45		#clock-cells = <0>;
46	};
47
48	soc {
49		compatible = "simple-bus";
50		interrupt-parent = <&plic>;
51		#address-cells = <1>;
52		#size-cells = <1>;
53		dma-noncoherent;
54		ranges;
55
56		gpio0: gpio@3020000 {
57			compatible = "snps,dw-apb-gpio";
58			reg = <0x3020000 0x1000>;
59			#address-cells = <1>;
60			#size-cells = <0>;
61
62			porta: gpio-controller@0 {
63				compatible = "snps,dw-apb-gpio-port";
64				gpio-controller;
65				#gpio-cells = <2>;
66				ngpios = <32>;
67				reg = <0>;
68				interrupt-controller;
69				#interrupt-cells = <2>;
70				interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
71			};
72		};
73
74		gpio1: gpio@3021000 {
75			compatible = "snps,dw-apb-gpio";
76			reg = <0x3021000 0x1000>;
77			#address-cells = <1>;
78			#size-cells = <0>;
79
80			portb: gpio-controller@0 {
81				compatible = "snps,dw-apb-gpio-port";
82				gpio-controller;
83				#gpio-cells = <2>;
84				ngpios = <32>;
85				reg = <0>;
86				interrupt-controller;
87				#interrupt-cells = <2>;
88				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
89			};
90		};
91
92		gpio2: gpio@3022000 {
93			compatible = "snps,dw-apb-gpio";
94			reg = <0x3022000 0x1000>;
95			#address-cells = <1>;
96			#size-cells = <0>;
97
98			portc: gpio-controller@0 {
99				compatible = "snps,dw-apb-gpio-port";
100				gpio-controller;
101				#gpio-cells = <2>;
102				ngpios = <32>;
103				reg = <0>;
104				interrupt-controller;
105				#interrupt-cells = <2>;
106				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
107			};
108		};
109
110		gpio3: gpio@3023000 {
111			compatible = "snps,dw-apb-gpio";
112			reg = <0x3023000 0x1000>;
113			#address-cells = <1>;
114			#size-cells = <0>;
115
116			portd: gpio-controller@0 {
117				compatible = "snps,dw-apb-gpio-port";
118				gpio-controller;
119				#gpio-cells = <2>;
120				ngpios = <32>;
121				reg = <0>;
122				interrupt-controller;
123				#interrupt-cells = <2>;
124				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
125			};
126		};
127
128		uart0: serial@4140000 {
129			compatible = "snps,dw-apb-uart";
130			reg = <0x04140000 0x100>;
131			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
132			clocks = <&osc>;
133			reg-shift = <2>;
134			reg-io-width = <4>;
135			status = "disabled";
136		};
137
138		uart1: serial@4150000 {
139			compatible = "snps,dw-apb-uart";
140			reg = <0x04150000 0x100>;
141			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
142			clocks = <&osc>;
143			reg-shift = <2>;
144			reg-io-width = <4>;
145			status = "disabled";
146		};
147
148		uart2: serial@4160000 {
149			compatible = "snps,dw-apb-uart";
150			reg = <0x04160000 0x100>;
151			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
152			clocks = <&osc>;
153			reg-shift = <2>;
154			reg-io-width = <4>;
155			status = "disabled";
156		};
157
158		uart3: serial@4170000 {
159			compatible = "snps,dw-apb-uart";
160			reg = <0x04170000 0x100>;
161			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
162			clocks = <&osc>;
163			reg-shift = <2>;
164			reg-io-width = <4>;
165			status = "disabled";
166		};
167
168		uart4: serial@41c0000 {
169			compatible = "snps,dw-apb-uart";
170			reg = <0x041c0000 0x100>;
171			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
172			clocks = <&osc>;
173			reg-shift = <2>;
174			reg-io-width = <4>;
175			status = "disabled";
176		};
177
178		plic: interrupt-controller@70000000 {
179			reg = <0x70000000 0x4000000>;
180			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
181			interrupt-controller;
182			#address-cells = <0>;
183			#interrupt-cells = <2>;
184			riscv,ndev = <101>;
185		};
186
187		clint: timer@74000000 {
188			reg = <0x74000000 0x10000>;
189			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
190		};
191	};
192};
193