1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/Five SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9 10#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) 11 12#include <arm64/renesas/r9a07g043.dtsi> 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <12000000>; 19 20 cpu0: cpu@0 { 21 compatible = "andestech,ax45mp", "riscv"; 22 device_type = "cpu"; 23 #cooling-cells = <2>; 24 reg = <0x0>; 25 status = "okay"; 26 riscv,isa = "rv64imafdc"; 27 mmu-type = "riscv,sv39"; 28 i-cache-size = <0x8000>; 29 i-cache-line-size = <0x40>; 30 d-cache-size = <0x8000>; 31 d-cache-line-size = <0x40>; 32 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 33 operating-points-v2 = <&cluster0_opp>; 34 35 cpu0_intc: interrupt-controller { 36 #interrupt-cells = <1>; 37 compatible = "riscv,cpu-intc"; 38 interrupt-controller; 39 }; 40 }; 41 }; 42}; 43 44&soc { 45 interrupt-parent = <&plic>; 46 47 plic: interrupt-controller@12c00000 { 48 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; 49 #interrupt-cells = <2>; 50 #address-cells = <0>; 51 riscv,ndev = <511>; 52 interrupt-controller; 53 reg = <0x0 0x12c00000 0 0x400000>; 54 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; 55 power-domains = <&cpg>; 56 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; 57 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; 58 }; 59}; 60